M50LPW012 2 Mbit (256Kb x8, Boot Block) 3V Supply Low Pin Count Flash Memory PRELIMINARY DATA ■ SUPPLY VOLTAGE – VCC = 3V to 3.6V for Program, Erase and Read Operations ■ – VPP = 12V for Fast Program and Fast Erase LOW PIN COUNT (LPC) – Standard Interface for embedded operation with PC Chipsets that are without automapping memory features ■ ADDRESS/ADDRESS MULTIPLEXED (A/A MUX) PLCC32 (K) – Interface for programming equipment compatibility ■ LOW PIN COUNT (LPC) HARDWARE INTERFACE MODE – 5 Signal Communication Interface supporting Read and Write Operations Figure 1. Logic Diagram (LPC Interface) – Hardware Write Protect Pins for Block Protection VCC VPP – Register Based Read and Write Protection – 5 Additional General Purpose Inputs for platform design flexibility – Synchronized with 33MHz PCI clock ■ BYTE PROGRAMMING TIME – Single Byte Mode 10µs typical 4 4 LAD0LAD3 ID0-ID3 5 GPI0GPI4 WP – Quadruple Byte Mode 2.5µs typical ■ 7 MEMORY BLOCKS – 1 Boot Block – 4 Main Blocks and 2 Parameter Blocks ■ PROGRAM/ERASE CONTROLLER – Embedded Byte Program and Block/Chip Erase algorithms LFRAME M50LPW012 TBL CLK IC RP INIT – Status Register Bits ■ PROGRAM and ERASE SUSPEND ■ FOR USE in PC BIOS APPLICATIONS ■ ELECTRONIC SIGNATURE VSS AI06949 – Manufacturer Code: 20h – Device Code: 3Bh September 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/35 M50LPW012 Figure 2. Logic Diagram (A/A Mux Interface) DESCRIPTION The M50LPW012 is a 2Mbit (256Kb x8) nonvolatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming and fast erasing in production lines an optional 12V power supply can be used to reduce the programming and the erasing times. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Blocks can be protected individually to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. Two different bus interfaces are supported by the memory. The primary interface is the Low Pin Count (or LPC) Standard Interface. This has been designed to remove the need for the ISA bus in VCC VPP 11 8 DQ0-DQ7 A0-A10 RC IC M50LPW012 RB G W RP VSS AI06950 A8 A9 RP VPP VCC RC A10 Figure 3. PLCC Connections A/A Mux GPI2 GPI3 RP VPP VCC CLK GPI4 A/A Mux 1 32 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 GPI1 GPI0 WP TBL ID3 ID2 ID1 ID0 LAD0 9 M50LPW012 25 IC (VIL) NC NC VSS VCC INIT LFRAME RFU RFU IC (VIH) NC NC VSS VCC G W RB DQ7 A/A Mux DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 LAD1 LAD2 VSS LAD3 RFU RFU RFU 17 A/A Mux AI06951 Note: Pins 27 and 28 are not internally connected. 2/35 M50LPW012 current PC Chipsets; the M50LPW012 acts as the PC BIOS on the Low Pin Count bus for these PC Chipsets. The secondary interface, the Address/Address Multiplexed (or A/A Mux) Interface, is designed to be compatible with current Flash Programmers for production line programming prior to fitting to a PC Motherboard. The memory is offered in a PLCC32 package and is supplied with all the bits erased (set to 1). System Memory Mapping The LPC address sequence is 32 bits long. The M50LPW012 responds to addresses mapped to the top of the 4 GByte memory space, from FFFF FFFFh. Address bits A31-A24, A22 must be set to 1. A23 is set to 1 for array access, and to 0 for register access. The M50LPW012 also responds to addresses mapped to the bottom of the 4 GByte memory space, from 0000 0000h. Address bits A31-A24, A22 must be set to 0. A23 is set to 0 for array access, and to 1 for register access. For A21-A18, see Table 2. A17-A0 are for array addresses. Table 1. Signal Names (LPC Interface) Memory LAD0-LAD3 Input/Output Communications LFRAME Input Communication Frame ID0-ID3 Identification Inputs GPI0-GPI4 General Purpose Inputs IC Interface Configuration RP Interface Reset INIT CPU Reset CLK Clock TBL Top Block Lock WP Write Protect RFU Reserved for Future Use. Leave disconnected or set at VIL or VIH. VCC Supply Voltage VPP Optional Supply Voltage for Fast Erase Operations VSS Ground NC Not Connected Internally Table 2. Memory Identification Input Configuration Top Memory Number ID2 ID2 ID1 ID0 Bottom A 21 A 20 A 19 A 18 A 21 A 20 A 19 A 18 VIL or floating VIL or floating VIL or floating VIL or floating 1 1 1 1 0 0 1 1 2 VIL or floating VIL or floating VIL or floating VIH 1 1 1 0 0 0 1 0 3 VIL or floating VIL or floating VIH VIL or floating 1 1 0 1 0 0 0 1 4 VIL or floating VIL or floating VIH VIH 1 1 0 0 0 0 0 0 5 VIL or floating VIH VIL or floating VIL or floating 1 0 1 1 0 1 1 1 6 VIL or floating VIH VIL or floating VIH 1 0 1 0 0 1 1 0 7 VIL or floating VIH VIH VIL or floating 1 0 0 1 0 1 0 1 8 VIL or floating VIH VIH VIH 1 0 0 0 0 1 0 0 9 VIH VIL or floating VIL or floating VIL or floating 0 1 1 1 1 0 1 1 10 VIH VIL or floating VIL or floating VIH 0 1 1 0 1 0 1 0 11 VIH VIL or floating VIH VIL or floating 0 1 0 1 1 0 0 1 12 VIH VIL or floating VIH VIH 0 1 0 0 1 0 0 0 13 VIH VIH VIL or floating VIL or floating 0 0 1 1 1 1 1 1 14 VIH VIH VIL or floating VIH 0 0 1 0 1 1 1 0 15 VIH VIH VIH VIL or floating 0 0 0 1 1 1 0 1 16 VIH VIH VIH VIH 0 0 0 0 1 1 0 0 1 (Boot) 3/35 M50LPW012 Table 3. System Memory Map A23 A31:24, A22 Array Register Top FFh, 1b 1 0 Bottom 00h, 0b 0 1 SIGNAL DESCRIPTIONS There are two different bus interfaces available on this part. The active interface is selected before power-up or during Reset using the Interface Configuration Pin, IC. The signals for each interface are discussed in the Low Pin Count (LPC) Signal Descriptions section and the Address/Address Multiplexed (A/A Mux) Signal Descriptions section below. The supply signals are discussed in the Supply Signal Descriptions section below. Low Pin Count (LPC) Signal Descriptions For the Low Pin Count (LPC) Interface see Figure 1, Logic Diagram, and Table 1, Signal Names. Input/Output Communications (LAD0-LAD3). All Input and Output Communication with the memory take place on these pins. Addresses and Data for Bus Read and Bus Write operations are encoded on these pins. Input Communication Frame (LFRAME). The Input Communication Frame (LFRAME) signals the start of a bus operation. When Input Communication Frame is Low, VIL, on the rising edge of the Clock a new bus operation is initiated. If Input Communication Frame is Low, VIL, during a bus operation then the operation is aborted. When Input Communication Frame is High, VIH, the current bus operation is proceeding or the bus is idle. Identification Inputs (ID0-ID3). The Identification Inputs (ID0-ID3) allow to address up to 16 memories on a bus. The value on addresses A18A21 is compared to the hardware strapping on the ID0-ID3 pins to select which memory is being addressed, as shown in Table 2. General Purpose Inputs (GPI0-GPI4). The General Purpose Inputs can be used as digital inputs for the CPU to read. The General Purpose Input Register holds the values on these pins. The pins must have stable data from before the start of the cycle that reads the General Purpose Input Register until after the cycle is complete. These pins must not be left to float, they should be driven Low, V IL, or High, V IH. Interface Configuration (IC). The Interface Configuration input selects whether the Low Pin Count (LPC) or the Address/Address Multiplexed (A/A Mux) Interface is used. The chosen interface must be selected before power-up or during a Reset 4/35 and, thereafter, cannot be changed. The state of the Interface Configuration, IC, should not be changed during operation. To select the Low Pin Count (LPC) Interface the Interface Configuration pin should be left to float or driven Low, VIL; to select the Address/Address Multiplexed (A/A Mux) Interface the pin should be driven High, VIH. An internal pull-down resistor is included with a value of RIL; there will be a leakage current of ILI2 through each pin when pulled to VIH; see Table 21. Interface Reset (RP). The Interface Reset (RP) input is used to reset the memory. When Interface Reset (RP) is set Low, VIL, the memory is in Reset mode: the outputs are put to high impedance and the current consumption is minimized. When RP is set High, V IH, the memory is in normal operation. After exiting Reset mode, the memory enters Read mode. CPU Reset (INIT). The CPU Reset, INIT, pin is used to Reset the memory when the CPU is reset. It behaves identically to Interface Reset, RP, and the internal Reset line is the logical OR (electrical AND) of RP and INIT. Clock (CLK). The Clock, CLK, input is used to clock the signals in and out of the Input/Output Communication Pins, LAD0-LAD3. The Clock conforms to the PCI specification. Top Block Lock (TBL). The Top Block Lock input is used to prevent the Top Block (Block 6) from being changed. When Top Block Lock, TBL, is set Low, VIL, Program and Block Erase operations in the Top Block have no effect, regardless of the state of the Lock Register. When Top Block Lock, TBL, is set High, V IH, the protection of the Block is determined by the Lock Register. The state of Top Block Lock, TBL, does not affect the protection of the Main Blocks (Blocks 0 to 5). Top Block Lock, TBL, must be set prior to a Program or Block Erase operation is initiated and must not be changed until the operation completes or unpredictable results may occur. Care should be taken to avoid unpredictable behavior by changing TBL during Program or Erase Suspend. Write Protect (WP). The Write Protect input is used to prevent the Main Blocks (Blocks 0 to 5) from being changed. When Write Protect, WP, is set Low, V IL, Program and Block Erase operations in the Main Blocks have no effect, regardless of the state of the Lock Register. When Write Protect, WP, is set High, VIH, the protection of the Block is determined by the Lock Register. The state of Write Protect, WP, does not affect the protection of the Top Block (Block 6). Write Protect, WP, must be set prior to a Program or Block Erase operation is initiated and must not M50LPW012 be changed until the operation completes or unpredictable results may occur. Care should be taken to avoid unpredictable behavior by changing WP during Program or Erase Suspend. Reserved for Future Use (RFU). These pins do not have assigned functions in this revision of the part. They may be left disconnected or driven Low, VIL, or High, VIH. Address/Address Multiplexed (A/A Mux) Signal Descriptions For the Address/Address Multiplexed (A/A Mux) Interface see Figure 2, Logic Diagram, and Table 4, Signal Names. Address Inputs (A0-A10). The Address Inputs are used to set the Row Address bits (A0-A10) and the Column Address bits (A11-A17). They are latched during any bus operation by the Row/Column Address Select input, RC. Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs hold the data that is written to or read from the memory. They output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. The Data Inputs/Outputs, DQ0-DQ7, are latched during a Bus Write operation. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface. Row/Column Address Select (RC). The Row/ Column Address Select input selects whether the Address Inputs should be latched into the Row Address bits (A0-A10) or the Column Address bits (A11-A17). The Row Address bits are latched on the falling edge of RC whereas the Column Address bits are latched on the rising edge. Ready/Busy Output (RB). The Ready/Busy pin gives the status of the memory’s Program/Erase Controller. When Ready/Busy is Low, VOL, the memory is busy with a Program or Erase operation and it will not accept any additional Program or Erase command except the Program/Erase Suspend command. When Ready/Busy is High, VOH, the memory is ready for any Read, Program or Erase operation. Supply Signal Descriptions The Supply Signals are the same for both interfaces. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, Table 4. Signal Names (A/A Mux Interface) IC Interface Configuration A0-A10 Address Inputs DQ0-DQ7 Data Inputs/Outputs G Output Enable W Write Enable RC Row/Column Address Select RB Ready/Busy Output RP Interface Reset VCC Supply Voltage VPP Optional Supply Voltage for Fast Program and Fast Erase Operations VSS Ground NC Not Connected Internally VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. After VCC becomes valid the Command Interface is reset to Read mode. A 0.1µF capacitor should be connected between the VCC Supply Voltage pins and the VSS Ground pin to decouple the current surges from the power supply. Both V CC Supply Voltage pins must be connected to the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations. VPP Optional Supply Voltage. The VPP Optional Supply Voltage pin is used to select the Fast Program (see the Quadruple Byte Program Command description) and Fast Erase options of the memory. VPP can be left floating. When VPP = VPPH Fast Program (if a Quadruple Byte Program Command is performed) and Fast Erase operations are used. VPP should not be set to V PPH for more than 80 hours during the life of the memory. VSS Ground. VSS is the reference for all the voltage measurements. 5/35 M50LPW012 Table 5. Absolute Maximum Ratings (1) Symbol TA Parameter Ambient Operating Temperature Value Unit 0 to 70 °C TBIAS Temperature Under Bias –50 to 125 °C TSTG Storage Temperature –65 to 150 °C VIO (2) Input or Output Voltage –0.6 to VCC + 0.6 V VCC Supply Voltage –0.6 to 4 V VPP Program Voltage –0.6 to 13 V Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to -2V and for less than 20ns during transitions. Maximum Voltage may overshoot to V CC +2V and for less than 20ns during transitions. BUS OPERATIONS The two interfaces have similar bus operations but the signals and timings are completely different. The Low Pin Count (LPC) Interface is the usual interface and all of the functionality of the part is available through this interface. Only a subset of functions are available through the Address/ Address Multiplexed (A/A Mux) Interface. Follow the section Low Pin Count (LPC) Bus Operations below and the section Address/ Address Multiplexed (A/A Mux) Interface Bus Operations below for a description of the bus operations on each interface. Low Pin Count (LPC) Bus Operations The Low Pin Count (LPC) Interface consists of four data signals (LAD0-LAD3), one control line (LFRAME) and a clock (CLK). In addition protection against accidental or malicious data corruption can be achieved using two further signals (TBL and WP). Finally two reset signals (RP and INIT) are available to put the memory into a known state. The data signals, control signal and clock are designed to be compatible with PCI electrical specifications. The interface operates with clock speeds up to 33MHz. The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Standby, Reset and Block Protection. Bus Read. Bus Read operations read from the memory cells, specific registers in the Command Interface or Low Pin Count Registers. A valid Bus Read operation starts when Input Communication Frame, LFRAME, is Low, VIL, as Clock rises and the correct Start cycle is on LAD0-LAD3. On the 6/35 following clock cycles the Host will send the Cycle Type + Dir, Address and other control bits on LAD0-LAD3. The memory responds by outputting Sync data until the wait-states have elapsed followed by Data0-Data3 and Data4-Data7. Refer to Table 7, LPC Bus Read Field Definitions, and Figure 4, LPC Bus Read Waveforms, for a description of the Field definitions for each clock cycle of the transfer. See Table 23, LPC Interface AC Signal Timing Characteristics and Figure 9, LPC Interface AC Signal Timing Waveforms, for details on the timings of the signals. Bus Write. Bus Write operations write to the Command Interface or Low Pin Count Registers. A valid Bus Write operation starts when Input Communication Frame, LFRAME, is Low, VIL, as Clock rises and the correct Start cycle is on LAD0LAD3. On the following Clock cycles the Host will send the Cycle Type + Dir, Address, other control bits, Data0-Data3 and Data4-Data7 on LAD0LAD3. The memory outputs Sync data until the wait-states have elapsed. Refer to Table 8, LPC Bus Write Field Definitions, and Figure 5, LPC Bus Write Waveforms, for a description of the Field definitions for each clock cycle of the transfer. See Table 23, LPC Interface AC Signal Timing Characteristics and Figure 9, LPC Interface AC Signal Timing Waveforms, for details on the timings of the signals. Bus Abort. The Bus Abort operation can be used to immediately abort the current bus operation. A Bus Abort occurs when LFRAME is driven Low, VIL, during the bus operation; the memory will tristate the Input/Output Communication pins, LAD0-LAD3. M50LPW012 Table 6. Block Addresses Size (KBytes) Address Range Block Number Block Type 16 3C000h-3FFFFh 6 Boot Block 8 3A000h-3BFFFh 5 Parameter Block 8 38000h-39FFFh 4 Parameter Block 32 30000h-37FFFh 3 Main Block 64 20000h-2FFFFh 2 Main Block 64 10000h-1FFFFh 1 Main Block 64 00000h-0FFFFh 0 Main Block Note: For A19:18 values, refer to Table 2. Note that, during a Bus Write operation, the Command Interface starts executing the command as soon as the data is fully received; a Bus Abort during the final TAR cycles is not guaranteed to abort the command; the bus, however, will be released immediately. Standby. When LFRAME is High, VIH, the memory is put into Standby mode where LAD0LAD3 are put into a high-impedance state and the Supply Current is reduced to the Standby level, ICC1. Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. The memory is in Reset mode when Interface Reset, RP, or CPU Reset, INIT, is Low, VIL. RP or INIT must be held Low, V IL, for tPLPH. The memory resets to Read mode upon return from Reset mode and the Lock Registers return to their default states regardless of their state before Reset, see Table 16. If RP or INIT goes Low, VIL, during a Program or Erase operation, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to tPLRH to abort a Program or Erase operation. Block Protection. Block Protection can be forced using the signals Top Block Lock, TBL, and Write Protect, WP, regardless of the state of the Lock Registers. Address/Address Multiplexed (A/A Mux) Bus Operations The Address/Address Multiplexed (A/A Mux) Interface has a more traditional style interface. The signals consist of a multiplexed address signals (A0-A10), data signals, (DQ0-DQ7) and three control signals (RC, G, W). An additional signal, RP, can be used to reset the memory. The Address/Address Multiplexed (A/A Mux) Interface is included for use by Flash Programming equipment for faster factory programming. Only a subset of the features available to the Low Pin Count (LPC) Interface are available; these include all the Commands but exclude the Security features and other registers. The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Output Disable and Reset. When the Address/Address Multiplexed (A/A Mux) Interface is selected all the blocks are unprotected. It is not possible to protect any blocks through this interface. Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature and the Status Register. A valid Bus Read operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC. Then Write Enable (W) and Interface Reset (RP) must be High, VIH, and Output Enable, G, Low, VIL, in order to perform a Bus Read operation. The Data Inputs/Outputs will output the value, see Figure 11, A/A Mux Interface Read AC Waveforms, and Table 25, A/A Mux Interface Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC. The data should be set up on the Data Inputs/Outputs; Output Enable, G, and Interface Reset, RP, must be High, VIH and Write Enable, W, must be Low, V IL. The Data Inputs/ Outputs are latched on the rising edge of Write Enable, W. See Figure 12, A/A Mux Interface Write AC Waveforms, and Table 26, A/A Mux Interface Write AC Characteristics, for details of the timing requirements. Output Disable. The data outputs are high-impedance when the Output Enable, G, is at VIH. Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. The memory is in Reset mode when RP is Low, VIL. RP must be held Low, VIL for tPLPH. If RP is goes Low, VIL, during a Program or Erase operation, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to tPLRH to abort a Program or Erase operation. 7/35 M50LPW012 Table 7. LPC Bus Read Field Definitions Clock Cycle Number Clock Cycle Count Field LAD0LAD3 Memory I/O Description 1 1 START 0000b I On the rising edge of CLK with LFRAME Low, the contents of LAD0-LAD3 must be 0000b to indicate the start of a LPC cycle. 2 1 CYCTY PE + DIR 0100b I Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1 indicates the direction of transfer: 0b for read. Bit 0 is ‘0’. 3-10 8 ADDR XXXX I A 32-bit address phase is transferred starting with the most significant nibble first. See Tables 3, 2 and 6 for the field description. 11 1 TAR 1111b I The host drives LAD0-LAD3 to 1111b to indicate a turnaround cycle. 12 1 TAR 1111b (float) O The LPC Flash Memory takes control of LAD0-LAD3 during this cycle. 13-14 2 WSYNC 0101b O The LPC Flash Memory drives LAD0-LAD3 to 0101b (short wait-sync) for two clock cycles, indicating that the data is not yet available. Two wait-states are always included. 15 1 RSYNC 0000b O The LPC Flash Memory drives LAD0-LAD3 to 0000b, indicating that data will be available during the next clock cycle. 16-17 2 DATA XXXX O Data transfer is two CLK cycles, starting with the least significant nibble. 18 1 TAR 1111b O The LPC Flash Memory drives LAD0-LAD3 to 1111b to indicate a turnaround cycle. 19 1 TAR 1111b (float) N/A The LPC Flash Memory floats its outputs, the host takes control of LAD0-LAD3. Figure 4. LPC Bus Read Waveforms CLK LFRAME LAD0-LAD3 START CYCTYPE + DIR ADDR TAR SYNC DATA TAR Number of clock cycles 1 1 8 2 3 2 2 AI04429 8/35 M50LPW012 Table 8. LPC Bus Write Field Definitions Clock Cycle Number Clock Cycle Count Field LAD0LAD3 Memory I/O Description 1 1 START 0000b I On the rising edge of CLK with LFRAME Low, the contents of LAD0-LAD3 must be 0000b to indicate the start of a LPC cycle. 2 1 CYCTY PE + DIR 011Xb I Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1 indicates the direction of transfer: 1b for write. Bit 0 is don’t care (X). 3-10 8 ADDR XXXX I A 32-bit address phase is transferred starting with the most significant nibble first. See Tables 3, 2 and 6 for the field description. 11-12 2 DATA XXXX I Data transfer is two cycles, starting with the least significant nibble. 13 1 TAR 1111b I The host drives LAD0-LAD3 to 1111b to indicate a turnaround cycle. 14 1 TAR 1111b (float) O The LPC Flash Memory takes control of LAD0-LAD3 during this cycle. 15 1 SYNC 0000b O The LPC Flash Memory drives LAD0-LAD3 to 0000b, indicating it has received data or a command. 16 1 TAR 1111b O The LPC Flash Memory drives LAD0-LAD3 to 1111b, indicating a turnaround cycle. 17 1 TAR 1111b (float) N/A The LPC Flash Memory floats its outputs and the host takes control of LAD0-LAD3. Figure 5. LPC Bus Write Waveforms CLK LFRAME LAD0-LAD3 START CYCTYPE + DIR ADDR DATA TAR SYNC TAR Number of clock cycles 1 1 8 2 2 1 2 AI04430 9/35 M50LPW012 Table 9. A/A Mux Bus Operations G W RP VPP DQ7-DQ0 Bus Read VIL VIH VIH Don’t Care Data Output Bus Write VIH VIL VIH Float or VCC or VPPH Data Input Output Disable VIH VIH VIH Don’t Care Hi-Z VIL or VIH VIL or VIH VIL Don’t Care Hi-Z Operation Reset Table 10. Manufacturer and Device Codes G W RP A18-A1 A0 DQ7-DQ0 Manufacturer Code VIL VIH VIH VIL VIL 20h Device Code VIL VIH VIH VIL VIH 3Bh Operation COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. After power-up or a Reset operation the memory enters Read mode. The commands are summarized in Table 12, Commands. Refer to Table 12 in conjunction with the text descriptions below. Read Memory Array Command. The Read Memory Array command returns the memory to its Read mode where it behaves like a ROM or EPROM. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Once the command is issued the memory remains in Read mode until another command is issued. From Read mode Bus Read operations will access the memory array. While the Program/Erase Controller is executing a Program or Erase operation the memory will not accept the Read Memory Array command until the operation completes. Read Status Register Command. The Read Status Register command is used to read the Status Register. One Bus Write cycle is required to issue the Read Status Register command. Once the command is issued subsequent Bus Read operations read the Status Register until another command is issued. See the section on the Status Register for details on the definitions of the Status Register bits. Read Electronic Signature Command. The Read Electronic Signature command is used to read the Manufacturer Code and the Device Code. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the 10/35 command is issued subsequent Bus Read operations read the Manufacturer Code or the Device Code until another command is issued. After the Read Electronic Signature Command is issued the Manufacturer Code and Device Code can be read using Bus Read operations using the addresses in Table 11. Program Command. The Program command can be used to program a value to one address in the memory array at a time. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the address and data in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. If the address falls in a protected block then the Program operation will abort, the data in the memory array will not be changed and the Status Register will output the error. During the Program operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Program times are given in Table 13. Note that the Program command cannot change a bit set at ‘0’ back to ‘1’ and attempting to do so will not cause any modification on its value. One of the Erase commands must be used to set all of the bits in the block to ‘1’. See Figure 13, Program Flowchart and Pseudo Code, for a suggested flowchart on using the Program command. M50LPW012 Quadruple Byte Program Command. The Quadruple Byte Program Command can be only used in A/A Mux mode to program four adjacent Bytes in the memory array at a time. The four Bytes must differ only for the addresses A0 and A1. Programming should not be attempted when VPP is not at V PPH. The operation can also be executed if V PP is below VPPH, but result could be uncertain. Five Bus Write operations are required to issue the command. The second, the third and the fourth Bus Write cycle latches respectively the address and data of the first, the second and the third Byte in the internal state machine. The fifth Bus Write cycle latches the address and data of the fourth Byte in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Quadruple Byte Program operation the memory will only accept the Read Status register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Quadruple Byte Program times are given in Table 13. Note that the Quadruple Byte Program command cannot change a bit set to ‘0’ back to ‘1’ and attempting to do so will not cause any modification on its value. One of the Erase commands must be used to set all of the bits in the block to ‘1’. See Figure 14, Quadruple Byte Program Flowchart and Pseudo Code, for a suggested flowchart on using the Quadruple Byte Program command. Chip Erase Command. The Chip Erase Command can be only used in A/A Mux mode to erase the entire chip at a time. Erasing should not be attempted when VPP is not at VPPH. The operation can also be executed if V PP is below VPPH, but result could be uncertain. Two Bus Write operations are required to issue the command and start the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Chip Erase operation the memory will only accept the Read Status Register command. All other commands will be ignored. Typical Chip Erase times are given in Table 13. The Chip Erase command sets all of the bits in the memory to ‘1’. See Figure 16, Chip Erase Flowchart and Pseudo Code, for a suggested flowchart on using the Chip Erase command. Block Erase Command. The Block Erase command can be used to erase a block. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the block address in the internal state machine and starts the Pro- Table 11. Read Electronic Signature Code Address Data Manufacturer Code 00000h 20h Device Code 00001h 3Bh Note: For A19:18 values, see Table 2. gram/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. If the block is protected then the Block Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. During the Block Erase operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Block Erase times are given in Table 13. The Block Erase command sets all of the bits in the block to ‘1’. All previous data in the block is lost. See Figure 17, Block Erase Flowchart and Pseudo Code, for a suggested flowchart on using the Block Erase command. Clear Status Register Command. The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to ‘0’. One Bus Write is required to issue the Clear Status Register command. Once the command is issued the memory returns to its previous mode, subsequent Bus Read operations continue to output the same data. The bits in the Status Register are sticky and do not automatically return to ‘0’ when a new Program or Erase command is issued. If an error occurs then it is essential to clear any error bits in the Status Register by issuing the Clear Status Register command before attempting a new Program or Erase command. Program/Erase Suspend Command. The Program/Erase Suspend command can be used to pause a Program or Block Erase operation. One Bus Write cycle is required to issue the Program/ Erase Suspend command and pause the Program/Erase Controller. Once the command is issued it is necessary to poll the Program/Erase Controller Status bit to find out when the Program/ Erase Controller has paused; no other commands will be accepted until the Program/Erase Controller has paused. After the Program/Erase Controller has paused, the memory will continue to output the Status Register until another command is issued. 11/35 M50LPW012 Command Cycles Table 12. Commands Bus Write Operations 1st 2nd Addr Data 3rd Addr Data Read Memory Array 1 X FFh Read Status Register 1 X 70h 1 X 90h 1 X 98h 2 X 40h PA PD 2 X 10h PA PD Quadruple Byte Program 5 X 30h A1 PD Chip Erase 2 X 80h X 10h Block Erase 2 X 20h BA D0h Clear Status Register 1 X 50h Program/Erase Suspend 1 X B0h Program/Erase Resume 1 X D0h 1 X 00h 1 X 01h 1 X 60h 1 X 2Fh 1 X C0h Read Electronic Signature 4th 5th Addr Data Addr Data Addr Data A2 PD A3 PD A4 PD Program Invalid/Reserved Note: X Don’t Care, PA Program Address, PD Program Data, A1,2,3,4 Consecutive Addresses, BA Any address in the Block. Read Memory Array. After a Read Memory Array command, read the memory as normal until another command is issued. Read Status Register. After a Read Status Register command, read the Status Register as normal until another command is issued. Read Electronic Signature. After a Read Electronic Signature command, read Manufacturer Code, Device Code until another command is issued. Block Erase, Program. After these commands read the Status Register until the command completes and another command is issued. Quadruple Byte Program. This command is only valid in A/A Mux mode. Addresses A 1, A2, A3 and A4 must be consecutive addresses differing only for address bit A0 and A1. After this command read the Status Register until the command completes and another command is issued. Chip Erase. This command is only valid in A/A Mux mode. After this command read the Status Register until the command completes and another command is issued. Clear Status Register. After the Clear Status Register command bits 1, 3, 4 and 5 in the Status Register are reset to ‘0’. Program/Erase Suspend. After the Program/Erase Suspend command has been accepted, issue Read Memory Array, Read Status Register, Program (during Erase suspend) and Program/Erase resume commands. Program/Erase Resume. After the Program/Erase Resume command the suspended Program/Erase operation resumes, read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Invalid/Reserved. Do not use Invalid or Reserved commands. 12/35 M50LPW012 Table 13. Program and Erase Times (TA = 0 to 70°C; VCC = 3.0 to 3.6V) Parameter Interface Test Condition Byte Program Min Typ (1) Max Unit 10 200 µs 200 µs Quadruple Byte Program A/A Mux VPP = 12V ± 5% 10(4) Chip Erase A/A Mux VPP = 12V ± 5% 3 A/A Mux VPP = 12V ± 5% 0.1 (2) 5 sec VPP < 12V – 5% 0.4 5 sec VPP = 12V ± 5% 0.75 8 sec VPP < 12V – 5% 1 10 sec Program/Erase Suspend to Program pause (3) 5 µs Program/Erase Suspend to Block Erase pause (3) 30 µs Block Program (64 KBytes) sec Block Erase (64 KBytes) Note: 1. 2. 3. 4. TA = 25°C, VCC = 3.3V This time is obtained executing the Quadruple Byte Program Command. Sampled only, not 100% tested. 10µs to program 4 Bytes. During the polling period between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing it is possible for the operation to complete. Once Program/Erase Controller Status bit indicates that the Program/ Erase Controller is no longer active, the Program Suspend Status bit or the Erase Suspend Status bit can be used to determine if the operation has completed or is suspended. For timing on the delay between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing see Table 13. During Program/Erase Suspend the Read Memory Array, Read Status Register, Read Electronic Signature and Program/Erase Resume commands will be accepted by the Command Interface. Additionally, if the suspended operation was Block Erase then the Program command will also be accepted; only the blocks not being erased may be read or programmed correctly. See Figures 15, Program Suspend & Resume Flowchart and Pseudo Code, and 18, Erase Suspend & Resume Flowchart and Pseudo Code, for suggested flowcharts on using the Program/ Erase Suspend command. Program/Erase Resume Command. The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend has paused it. One Bus Write cycle is required to issue the Program/Erase Resume command. Once the command is issued subsequent Bus Read operations read the Status Register. STATUS REGISTER The Status Register provides information on the current or previous Program or Erase operation. Different bits in the Status Register convey different information and errors on the operation. To read the Status Register the Read Status Register command can be issued. The Status Register is automatically read after Program, Erase and Program/Erase Resume commands are issued. The Status Register can be read from any address. The Status Register bits are summarized in Table 14, Status Register Bits. Refer to Table 14 in conjunction with the text descriptions below. Program/Erase Controller Status (Bit 7). The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is ‘0’, the Program/Erase Controller is active; when the bit is ‘1’, the Program/Erase Controller is inactive. The Program/Erase Controller Status is ‘0’ immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is ‘1’. During Program and Erase operation the Program/Erase Controller Status bit can be polled to find the end of the operation. The other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is ‘1’. 13/35 M50LPW012 Table 14. Status Register Bits Operation Bit 7 Bit 6 Bit 5 Bit 4 Bit 2 Bit 1 Program active 0 X(1) 0 0 0 0 Program suspended 1 X(1) 0 0 1 0 Program completed successfully 1 X(1) 0 0 0 0 Program failure due to Block Protection (LPC Interface only) 1 X(1) 0 0 0 1 Program failure due to cell failure 1 X(1) 0 1 0 0 Erase active 0 0 0 0 0 0 Block Erase suspended 1 1 0 0 0 0 Erase completed successfully 1 0 0 0 0 0 Block Erase failure due to Block Protection (LPC Interface only) 1 0 0 0 0 1 Erase failure due to failed cell(s) 1 0 1 0 0 0 Note: 1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwise Bit 6 is ‘0’. After the Program/Erase Controller completes its operation the Erase Status, Program Status and Block Protection Status bits should be tested for errors. Erase Suspend Status (Bit 6). The Erase Suspend Status bit indicates that a Block Erase operation has been suspended and is waiting to be resumed. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Erase Suspend Status bit is ‘0’ the Program/Erase Controller is active or has completed its operation; when the bit is ‘1’ a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns to ‘0’. Erase Status (Bit 5). The Erase Status bit can be used to identify if the memory has applied the maximum number of erase pulses to the block(s) and still failed to verify that the block(s) has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive). When the Erase Status bit is ‘0’ the memory has successfully verified that the block(s) has erased correctly; when the Erase Status bit is ‘1’ the Program/Erase Controller has applied the maximum number of pulses to the block(s) and still failed to verify that the block(s) has erased correctly. Once the Erase Status bit is set to ‘1’ it can only be reset to ‘0’ by a Clear Status Register command or 14/35 a hardware reset. If it is set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status (Bit 4). The Program Status bit can be used to identify if the memory has applied the maximum number of program pulses to the Byte and still failed to verify that the Byte has programmed correctly. The Program Status bit should be read once the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive). When the Program Status bit is ‘0’ the memory has successfully verified that the Byte has programmed correctly; when the Program Status bit is ‘1’ the Program/Erase Controller has applied the maximum number of pulses to the Byte and still failed to verify that the Byte has programmed correctly. Once the Program Status bit is set to ‘1’ it can only be reset to ‘0’ by a Clear Status Register command or a hardware reset. If it is set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Reserved (Bit 3). This status bit is reserved for future use. Its value should be masked out whenever the status register is read. Program Suspend Status (Bit 2). The Program Suspend Status bit indicates that a Program operation has been suspended and is waiting to be resumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. M50LPW012 When the Program Suspend Status bit is ‘0’ the Program/Erase Controller is active or has completed its operation; when the bit is ‘1’ a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Program Suspend Status bit returns to ‘0’. Block Protection Status (Bit 1). The Block Protection Status bit can be used to identify if the Program or Block Erase operation has tried to modify the contents of a protected block. When the Block Protection Status bit is to ‘0’ no Program or Block Erase operations have been attempted to protected blocks since the last Clear Status Register command or hardware reset; when the Block Protection Status bit is ‘1’ a Program or Block Erase operation has been attempted on a protected block. Once it is set to ‘1’ the Block Protection Status bit can only be reset to ‘0’ by a Clear Status Register command or a hardware reset. If it is set to ‘1’ it should be reset before a new Program or Block Erase command is issued, otherwise the new command will appear to fail. Using the A/A Mux Interface the Block Protection Status bit is always ‘0’. Reserved (Bit 0). Bit 0 of the Status Register is reserved. Its value should be masked. LOW PIN COUNT (LPC) INTERFACE CONFIGURATION REGISTERS When the Low Pin Count Interface is selected several additional registers can be accessed. These registers control the protection status of the Blocks and read the General Purpose Input pins. See Table 15 for an example of the Register Configuration map, valid for the boot memory, that is, ID0ID3 can be left floating or driven Low, VIL. Lock Registers The Lock Registers control the protection status of the Blocks. Each Block has its own Lock Register. Three bits within each Lock Register control the protection of each block, the Write Lock Bit, the Read Lock Bit and the Lock Down Bit. The Lock Registers can be read and written, though care should be taken when writing as, once the Lock Down Bit is set, ‘1’, further modifications to the Lock Register cannot be made until cleared, to ‘0’, by a reset or power-up. See Table 16 for details on the bit definitions of the Lock Registers. Write Lock. The Write Lock Bit determines whether the contents of the Block can be modified (using the Program or Block Erase Command). When the Write Lock Bit is set, ‘1’, the block is write protected; any operations that attempt to change the data in the block will fail and the Status Register will report the error. When the Write Lock Bit is reset, ‘0’, the block is not write protected through the Lock Register and may be modified unless write protected through some other means. If Top Block Lock, TBL, is Low, VIL, then the Boot Block (Block 6) is write protected and cannot be modified. Similarly, if Write Protect, WP, is Low, VIL, then the Main Blocks (Blocks 0 to 5) are write protected and cannot be modified. After power-up or reset the Write Lock Bit is always set to ‘1’ (write protected). Read Lock. The Read Lock bit determines whether the contents of the Block can be read (from Read mode). When the Read Lock Bit is set, ‘1’, the block is read protected; any operation that attempts to read the contents of the block will read 00h instead. When the Read Lock Bit is reset, ‘0’, read operations in the Block return the data programmed into the block as expected. After power-up or reset the Read Lock Bit is always reset to ‘0’ (not read protected). Lock Down. The Lock Down Bit provides a mechanism for protecting software data from simple hacking and malicious attack. When the Lock Down Bit is set, ‘1’, further modification to the Write Lock, Read Lock and Lock Down Bits cannot be performed. A reset or power-up is required before changes to these bits can be made. When the Lock Down Bit is reset, ‘0’, the Write Lock, Read Lock and Lock Down Bits can be changed. General Purpose Input Register The General Purpose Input Register holds the state of the General Purpose Input pins, GPI0GPI4. When this register is read, the state of these pins is returned. This register is read-only and writing to it has no effect. The signals on the General Purpose Input pins should remain constant throughout the whole Bus Read cycle in order to guarantee that the correct data is read. 15/35 M50LPW012 Table 15. Low Pin Count Register Configuration Map(1) Memory Address Top Bottom Default Value Access Top Block Lock Register (Block 6) FF7FC002h 008FC002h 01h R/W T_MINUS01_LK Top Block [-1] Lock Register (Block 5) FF7FA002h 008FA002h 01h R/W T_MINUS02_LK Top Block [-2] Lock Register (Block 4) FF7F8002h 008F8002h 01h R/W T_MINUS03_LK Top Block [-3] Lock Register (Block 3) FF7F0002h 008F0002h 01h R/W T_MINUS04_LK Top Block [-4] Lock Register (Block 2) FF7E0002h 008E0002h 01h R/W T_MINUS05_LK Top Block [-5] Lock Register (Block 1) FF7D0002h 008D0002h 01h R/W T_MINUS06_LK Top Block [-6] Lock Register (Block 0) FF7C0002h 008C0002h 01h R/W General Purpose Input Register FF7C0100h 008C0100h N/A R Mnemonic T_BLOCK_LK GPI_REG Register Name Note: 1. This map is referred to the boot memory (ID0-ID3 floating or driven, Low). 16/35 M50LPW012 Table 16. Lock Register Bit Definitions(1) Bit Bit Name Value 7-3 2 1 0 Function Reserved ‘1’ Bus Read operations in this Block always return 00h. ‘0’ Bus read operations in this Block return the Memory Array contents. (Default value). ‘1’ Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a ‘1’ is written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset to ‘0’ following a Reset (using RP or INIT) or after power-up. ‘0’ Read-Lock and Write-Lock can be changed by writing new values to them. (Default value). ‘1’ Program and Block Erase operations in this Block will set an error in the Status Register. The memory contents will not be changed. (Default value). ‘0’ Program and Block Erase operations in this Block are executed and will modify the Block contents. Read-Lock Lock-Down Write-Lock Note: 1. Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-6] Lock Register (T_MINUS06_LK). Table 17. General Purpose Input Register Definition (1) Bit Bit Name Value 7-5 4 3 2 1 0 Function Reserved ‘1’ Input Pin GPI4 is at VIH ‘0’ Input Pin GPI4 is at VIL ‘1’ Input Pin GPI3 is at VIH ‘0’ Input Pin GPI3 is at VIL ‘1’ Input Pin GPI2 is at VIH ‘0’ Input Pin GPI2 is at VIL ‘1’ Input Pin GPI1 is at VIH ‘0’ Input Pin GPI1 is at VIL ‘1’ Input Pin GPI0 is at VIH ‘0’ Input Pin GPI0 is at VIL GPI4 GPI3 GPI2 GPI1 GPI0 Note: 1. Applies to the General Purpose Input Register (GPI_REG). 17/35 M50LPW012 Table 18. LPC Interface AC Measurement Conditions Parameter Value Unit 3.0 to 3.6 V 10 pF ≤ 1.4 ns 0.2 VCC and 0.6 VCC V 0.4 VCC V VCC Supply Voltage Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Figure 6. LPC Interface AC Testing Input Output Waveforms 0.6 VCC 0.4 VCC 0.2 VCC Input and Output AC Testing Waveform IO < ILO IO > ILO IO < ILO Output AC Tri-state Testing Waveform AI03404 18/35 M50LPW012 Table 19. A/A Mux Interface AC Measurement Conditions Parameter Value Unit 3.0 to 3.6 V 30 pF Input Rise and Fall Times ≤ 10 ns Input Pulse Voltages 0 to 3 V 1.5 V VCC Supply Voltage Load Capacitance (CL) Input and Output Timing Ref. Voltages Figure 7. A/A Mux Interface AC Testing Input Output Waveform 3V 1.5V 0V AI01417 Table 20. Impedance (TA = 25 °C, f = 1 MHz) Symbol Parameter Test Condition CIN(1) Input Capacitance VIN = 0V CCLK(1) Clock Capacitance VIN = 0V LPIN(2) Recommended Pin Inductance Min 3 Max Unit 13 pF 12 pF 20 nH Note: 1. Sampled only, not 100% tested. 2. See PCI Specification. 19/35 M50LPW012 Table 21. DC Characteristics (TA = 0 to 70°C; VCC = 3.0 to 3.6V) Symbol VIH VIL Parameter Input High Voltage Input Low Voltage Interface Test Condition Min Max Unit LPC 0.5 VCC VCC + 0.5 V A/A Mux 0.7 VCC VCC + 0.3 V LPC –0.5 0.3 VCC V A/A Mux -0.5 0.8 V VIH(INIT) INIT Input High Voltage LPC 1.35 VCC + 0.5 V VIL(INIT) INIT Input Low Voltage LPC –0.5 0.2 VCC V ILI(2) Input Leakage Current 0V ≤ VIN ≤ VCC ±10 µA ILI2 IC, IDx Input Leakage Current IC, ID0, ID1, ID2, ID3 = VCC 200 µA RIL IC, IDx Input Pull Low Resistor 100 kΩ VOH Output High Voltage VOL ILO 20 LPC IOH = –500µA 0.9 VCC V A/A Mux IOH = –100µA VCC – 0.4 V LPC IOL = 1.5mA 0.1 VCC V A/A Mux IOL = 1.8mA 0.45 V 0V ≤ VOUT ≤ VCC ±10 µA Output Low Voltage Output Leakage Current VPPH VPP Voltage (Fast Program/Fast Erase) 11.4 12.6 V VLKO(1) VCC Lockout Voltage 1.8 2.3 V ICC1 Supply Current (Standby) LPC LFRAME = 0.9 VCC All other inputs 0.9 VCC to 0.1 VCC VCC = 3.6V, f(CLK) = 33MHz 100 µA ICC2 Supply Current (Standby) LPC LFRAME = 0.1 VCC All other inputs 0.9 VCC to 0.1 VCC VCC = 3.6V, f(CLK) = 33MHz 10 mA ICC3 Supply Current (Any internal operation active) LPC VCC = VCC max f(CLK) = 33MHz IOUT = 0mA 60 mA ICC4 Supply Current (Read) A/A Mux G = VIH, f = 6MHz 20 mA Supply Current (Program/Erase) A/A Mux Program/Erase Controller Active 20 mA VPP Supply Current (Read/Standby) VPP > VCC 400 µA VPP Supply Current (Program/Erase active) VPP = VCC 5 µA VPP = 12V ± 5% 15 mA ICC5(1) IPP IPP1(1) Note: 1. Sampled only, not 100% tested. 2. Input leakage currents include High-Z output leakage for all bi-directional buffers with tri-state outputs. 20/35 M50LPW012 Table 22. LPC Interface Clock Characteristics (TA = 0 to 70°C; VCC = 3.0 to 3.6V) Symbol Parameter Test Condition Value Unit tCYC CLK Cycle Time(1) Min 30 ns tHIGH CLK High Time Min 11 ns tLOW CLK Low Time Min 11 ns Min 1 V/ns Max 4 V/ns CLK Slew Rate peak to peak Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed by design rather than tested. Refer to PCI Specification. Figure 8. LPC Interface Clock Waveform tCYC tHIGH 0.6 VCC 0.5 VCC 0.4 VCC tLOW 0.4 VCC, p-to-p (minimum) 0.3 VCC 0.2 VCC AI03403 21/35 M50LPW012 Table 23. LPC Interface AC Signal Timing Characteristics (TA = 0 to 70°C; VCC = 3.0 to 3.6V) Symbol PCI Symbol tCHQV tval CLK to Data Out tCHQX(1) ton tCHQZ Parameter Test Condition Value Unit Min 2 ns Max 11 ns CLK to Active (Float to Active Delay) Min 2 ns toff CLK to Inactive (Active to Float Delay) Max 28 ns tAVCH tDVCH tsu Input Set-up Time(2) Min 7 ns tCHAX tCHDX th Input Hold Time(2) Min 0 ns Note: 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current specification. 2. Applies to all inputs except CLK. Figure 9. LPC Interface AC Signal Timing Waveforms CLK tCHQV tCHQZ tCHQX LAD0-LAD3 tDVCH tCHDX VALID VALID OUTPUT DATA FLOAT OUTPUT DATA VALID INPUT DATA AI04431 22/35 M50LPW012 Table 24. Reset AC Characteristics (TA = 0 to 70°C; VCC = 3.0 to 3.6V) Symbol Parameter tPLPH RP or INIT Reset Pulse Width tPLRH RP or INIT Low to Reset Test Condition RP or INIT Slew Rate(1) Value Unit Min 100 ns Program/Erase Inactive Max 100 ns Program/Erase Active Max 30 µs Rising edge only Min 50 mV/ns tPHFL RP or INIT High to LFRAME Low LPC Interface only Min 30 µs tPHWL tPHGL RP High to Write Enable or Output Enable Low A/A Mux Interface only Min 50 µs Note: 1. See Chapter 4 of the PCI Specification. Figure 10. Reset AC Waveforms RP, INIT tPLPH W, G, LFRAME tPHWL, tPHGL, tPHFL tPLRH RB AI04432 23/35 M50LPW012 Table 25. A/A Mux Interface Read AC Characteristics (TA = 0 to 70°C; VCC = 3.0 to 3.6V) Symbol Parameter Test Condition Value Unit tAVAV Read Cycle Time Min 250 ns tAVCL Row Address Valid to RC Low Min 50 ns tCLAX RC Low to Row Address Transition Min 50 ns tAVCH Column Address Valid to RC high Min 50 ns tCHAX RC High to Column Address Transition Min 50 ns tCHQV(1) RC High to Output Valid Max 150 ns tGLQV(1) Output Enable Low to Output Valid Max 50 ns tPHAV RP High to Row Address Valid Min 1 µs tGLQX Output Enable Low to Output Transition Min 0 ns tGHQZ Output Enable High to Output Hi-Z Max 50 ns tGHQX Output Hold from Output Enable High Min 0 ns Note: 1. G may be delayed up to tCHQV – t GLQV after the rising edge of RC without impact on t CHQV. Figure 11. A/A Mux Interface Read AC Waveforms tAVAV ROW ADDR VALID A0-A10 tAVCL NEXT ADDR VALID COLUMN ADDR VALID tAVCH tCLAX tCHAX RC tCHQV G tGLQV tGHQZ tGLQX tGHQX VALID DQ0-DQ7 W tPHAV RP AI03406 24/35 M50LPW012 Table 26. A/A Mux Interface Write AC Characteristics (TA = 0 to 70°C; VCC = 3.0 to 3.6V) Symbol Parameter Test Condition Value Unit tWLWH Write Enable Low to Write Enable High Min 100 ns tDVWH Data Valid to Write Enable High Min 50 ns tWHDX Write Enable High to Data Transition Min 5 ns tAVCL Row Address Valid to RC Low Min 50 ns tCLAX RC Low to Row Address Transition Min 50 ns tAVCH Column Address Valid to RC High Min 50 ns tCHAX RC High to Column Address Transition Min 50 ns tWHWL Write Enable High to Write Enable Low Min 100 ns tCHWH RC High to Write Enable High Min 50 ns tWHGL Write Enable High to Output Enable Low Min 30 ns tWHRL Write Enable High to RB Low Min 0 ns 25/35 M50LPW012 Figure 12. A/A Mux Interface Write AC Waveforms Write erase or program setup A0-A10 Write erase confirm or valid address and data C1 R2 tCLAX tAVCH R1 tAVCL Automated erase or program delay Read Status Register Data Ready to write another command C2 tCHAX RC tWHWL tWLWH tCHWH W tWHGL G tWHRL RB tDVWH DQ0-DQ7 DIN1 tWHDX DIN2 VALID SRD AI06817 26/35 M50LPW012 Figure 13. Program Flowchart and Pseudo Code Start Program command: – write 40h or 10h – write Address & Data (memory enters read status state after the Program command) Write 40h or 10h Write Address & Data do: –read Status Register if Program/Erase Suspend command given execute suspend program loop NO Read Status Register Suspend b7 = 1 NO YES Suspend Loop while b7 = 1 YES b4 = 0 NO Program Error (1, 2) NO Program to Protected Block Error (1, 2) If b4 = 1, Program error: – error handler YES LPC Interface Only b1 = 0 If b1 = 1, Program to protected block error: – error handler YES End AI06818 Note: 1. A Status check of b1 (Protected Block) and b4 (Program Error) can be made after each Program operation by following the correct command sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 27/35 M50LPW012 Figure 14. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) Start Write 30h Write Address 1 & Data 1 (3) Quadruple Byte Program command: – write 30h – write Address 1 & Data 1 (3) – write Address 2 & Data 2 (3) – write Address 3 & Data 3 (3) – write Address 4 & Data 4 (3) Write Address 2 & Data 2 (3) (memory enters read status state after the Quadruple Byte Program command) Write Address 3 & Data 3 (3) Write Address 4 & Data 4 (3) do: – read Status Register if Program/Erase Suspend command given execute suspend program loop NO Read Status Register Suspend b7 = 1 NO YES Suspend Loop while b7 = 1 YES b4 = 0 NO Program Error (1, 2) If b4 = 1, Program error: – error handler YES End AI06819 Note: 1. A Status check of b4 (Program Error) can be made after each Program operation by following the correct command sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Address 1, Address 2, Address 3 and Address 4 must be consecutive addresses differing only for address bits A0 and A1. 28/35 M50LPW012 Figure 15. Program Suspend and Resume Flowchart, and Pseudo Code Start Write B0h Program/Erase Suspend command: – write B0h – write 70h Write 70h do: – read Status Register Read Status Register b7 = 1 NO while b7 = 1 YES b2 = 1 NO Program Complete If b2 = 0 Program completed YES Write a read Command Read data from another address Write D0h Write FFh Program Continues Read Data Program/Erase Resume command: – write D0h to resume the program – if the Program operation completed then this is not necessary. The device returns to Read as normal (as if the Program/Erase suspend was not issued). AI03408 29/35 M50LPW012 Figure 16. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) Start Chip Erase command: – write 80h – write 10h (memory enters read Status Register after the Chip Erase command) Write 80h Write 10h do: – read Status Register Read Status Register b7 = 1 NO while b7 = 1 YES b4, b5 = 0 NO Command Sequence Error (1) If b4, b5 = 1, Command sequence error: – error handler YES b5 = 0 NO Erase Error (1) If b5 = 1, Erase error: – error handler YES End AI06820 Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 30/35 M50LPW012 Figure 17. Block Erase Flowchart and Pseudo Code Start Block Erase command: – write 20h – write Block Address & D0h (memory enters read Status Register after the Block Erase command) Write 20h Write Block Address & D0h Suspend b7 = 1 do: – read Status Register – if Program/Erase Suspend command given execute suspend erase loop NO Read Status Register NO YES Suspend Loop while b7 = 1 YES b4, b5 = 0 NO Command Sequence Error (1) If b4, b5 = 1, Command sequence error: – error handler YES b5 = 0 NO Erase Error (1) If b5 = 1, Erase error: – error handler YES LPC Interface Only b1 = 0 NO Erase to Protected Block Error (1) If b1 = 1, Erase to protected block error: – error handler YES End AI04434 Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 31/35 M50LPW012 Figure 18. Erase Suspend and Resume Flowchart, and Pseudo Code Start Write B0h Program/Erase Suspend command: – write B0h – write 70h Write 70h do: – read Status Register Read Status Register b7 = 1 NO while b7 = 1 YES b6 = 1 NO Erase Complete If b6 = 0, Erase completed YES Read data from another block or Program Write D0h Write FFh Erase Continues Read Data Program/Erase Resume command: – write D0h to resume erase – if the Erase operation completed then this is not necessary. The device returns to Read as normal (as if the Program/Erase suspend was not issued). AI03410 32/35 M50LPW012 Table 27. Ordering Information Scheme Example: M50LPW012 K 1 T Device Type M50 Architecture LP = Low Pin Count Interface Operating Voltage W = 3.0 to 3.6V Device Function 012 = 2 Mbit (256Kb x8), Boot Block Package K = PLCC32 Temperature Range 1 = 0 to 70 °C Option T = Tape & Reel Packing For a list of available options or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. Table 28. Revision History Date Version 17-Jun-2002 -01 29-Aug-2002 1.1 16-Sep-2002 1.2 Revision Details First Issue PC Chipsets without automapping memory features mentioned on page 1 Value of A19 inverted for Memory Identification Input Configuration (and Register Configuration Map) for Bottom Boot Block devices 33/35 M50LPW012 PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Outline D D1 A1 A2 1 N B1 E2 E3 e E1 E F B 0.51 (.020) E2 1.14 (.045) A D3 R D2 CP D2 PLCC-A Note: Drawing is not to scale. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data Symbol millimeters Typ Min Max Min Max A 3.18 3.56 0.125 0.140 A1 1.53 2.41 0.060 0.095 A2 B 0.38 – 0.015 – 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 CP Typ 0.10 0.004 D 12.32 12.57 0.485 0.495 D1 11.35 11.51 0.447 0.453 D2 4.78 5.66 0.188 0.223 – – – – E 14.86 15.11 0.585 0.595 E1 13.89 14.05 0.547 0.553 E2 6.05 6.93 0.238 0.273 D3 7.62 0.300 E3 10.16 – – 0.400 – – e 1.27 – – 0.050 – – F 0.00 0.13 0.000 0.005 N 32 R 34/35 inches 0.89 – 32 – 0.035 – – M50LPW012 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners © 2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com 35/35