M58BF008 8 Mbit (256Kb x32, Burst) Flash Memory PRELIMINARY DATA ■ SUPPLY VOLTAGE – VDD = 5V Supply Voltage – VDDQ = 3.3V Input/Output Supply Voltage – Optional VPP = 12V for fast Program and Erase ■ CONFIGURABLE OPTIONS BGA – Synchronous or Asynchronous write mode – Burst Wrap/No-wrap default – Critical Word X (3 or 4) and Burst Word Y (1 or 2) latency times ■ ACCESS TIME LBGA80 (ZA) 10 x 8 solder balls PQFP80 (D) – Synchronous X-Y-Y-Y Burst Read up to 40MHz – Asynchronous Read: 100ns ■ PROGRAMMING TIME: 10µs typical ■ MEMORY BLOCKS Figure 1. Logic Diagram – 32 equal Main blocks of 256 Kbit VDD VDDQ VPP – One Overlay block of 256 Kbit ■ 18 ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: F0h 32 A17-A0 DQ31-DQ0 CLK – Version Code: 0-7h RP DESCRIPTION The M58BF008 is a family of 8 Mbit non-volatile Flash memories that can be erased electrically at the block level and programmed in-system. Family members are configured during product testing for a specific Synchronous or Asynchronous Write mode, a Burst default of Wrap or No-wrap and for Critical Word X = 3 or 4 and Burst Word Y = 1 or 2 latency times. The Main memory array matrix allows each of the 32 equal blocks of 256 Kbit to be erased separately and re-programmed without affecting other blocks. The memory features a 256 Kbit Overlay block having the same address space as the first Main memory block. The Overlay block provides a secure storage area that is controlled by special Instructions and an external input. A separate supply VDDQ allows the Input/ Output signals to be at 3.3V levels, while the main supply VDD is 5V. E G M58BF008 GD W LBA WR BAA VSS VSSQ AI02656B February 2000 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/36 M58BF008 Figure 2. LBGA Connections (Top view through package) 1 2 3 4 5 6 7 8 A A16 A15 A13 A11 A9 A8 A4 A3 B A17 A14 A12 A10 A7 A6 A1 A2 C DQ1 DQ2 DQ0 VDD VSS A0 A5 DQ31 D DQ4 DQ3 VDDQ DU VPP VDDQ DQ30 DQ28 E DQ7 DQ5 VSSQ DU DU VSSQ DQ29 DQ27 F DQ8 DQ6 VDDQ DU DU VSSQ DQ26 DQ25 G DQ10 DQ9 VSSQ VDDQ DU VDDQ DQ23 DQ24 H DQ11 DQ12 BAA VSS VDD DQ22 DQ201 DQ19 J DQ14 DQ13 CLK G W DQ18 DQ21 DQ17 K DQ15 RP LBA E WR GD DU DQ16 AI02668 2/36 M58BF008 NC NC GD WR W G E VDD BAA VSS LBA NC NC CLK RP VDDQ Figure 3. PQFP Connections 73 1 12 M58BF008 53 DQ15 DQ14 DQ13 DQ12 VSSQ VDDQ DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 VSSQ VDDQ DQ3 DQ2 DQ1 DQ0 NC NC A17 A16 VSS VPP VDD A9 A10 A11 A12 A13 A14 A15 32 A3 A4 A5 A6 A7 A8 DQ16 DQ17 DQ18 DQ19 VDDQ VSSQ DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 VDDQ VSSQ DQ28 DQ29 DQ30 DQ31 NC A0 A1 A2 AI02661 3/36 M58BF008 Table 1. Signal Names A0-A17 Address Inputs DQ0-DQ31 Data Input/Output CLK System Clock RP Reset/Power-down E Chip Enable G Output Enable GD Output Disable W Write Enable LBA Load Burst Address WR Write/Read BAA Burst Address Advance VDD Supply Voltage VDDQ Supply Voltage for Input/Output Buffers VPP Program Supply Voltage VSS Ground VSSQ Input/Output Ground NC Not Connected Internally DU Don’t Use as Internally Connected A Command Interface decodes the Instructions written to the memory to access or modify the memory content, to toggle the enable/disable of read access to the Overlay block, to toggle the burst Wrap/No-wrap or to toggle the Synchronous or Asynchronous Read mode. A Program/Erase Controller (P/E.C.) executes the algorithms taking care of the timings necessary for program and erase operations. The P/E.C. also takes care of verification to unburden the system microprocessor, while a Status Register tracks the status of each operation. The following Instructions are executed by the memory in either Asynchronous or Synchronous mode. Access or modify memory content: - Read Array - Read or Clear Status Register - Read Electronic Signature - Erase Main memory block or Overlay block - Program Main memory or Overlay memory - Program Erase Suspend or Resume Toggle: – Asynchronous/Synchronous Read – Overlay Block Read Enable/Disable – Burst Wrap/No-wrap The M58BF008 devices are offered in PQFP80 and LBGA80 1.0mm ball pitch packages. When the VPP supply is at VSS this prevents programming and erasure of the memory blocks and, in addition, it prevents reading of the Overlay block. When the VPP supply is at 5V it enables both in-system program/erase and read access to the Overlay block. For a limited time and number of program/erase cycles the VPP supply may be raised to 12V to provide fast program and erase times. Table 2. Absolute Maximum Ratings (1) Symbol Value Unit Ambient Operating Temperature –40 to 125 °C TBIAS Temperature Under Bias –40 to 125 °C TSTG Storage Temperature –55 to 150 °C V IO Input Output Voltage –0.6 to VDDQ +0.6 V –0.6 to 7 V –0.6 to 13.5 V TA VDD, VDDQ V PP Parameter Supply Voltage Program Voltage Note: 1. Stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. 4/36 M58BF008 ORGANISATION The M58BF008 has a data path width of 32 bit (Double-Word) and is organised as a Main memory array of 32 blocks of 256 Kbit plus an Overlay block of 256 Kbit having the same address space as the first Main memory block. The memory map is shown in Table 3. The memory is addressed by A0-A17 which are static for Asynchronous or latched for Synchronous operation. Data Input/Output is static or latched on DQ0-DQ31, these signals output data, Table 3. Block Addresses # Size (Kbit) 31 256 3E000-3FFFF 30 256 3C000-3DFFF 29 256 3A000-3BFFF 28 256 38000-39FFF 27 256 36000-37FFF 26 256 34000-35FFF 25 256 32000-33FFF 24 256 30000-31FFF 23 256 2E000-2FFFF 22 256 2C000-2DFFF 21 256 2A000-2BFFF 20 256 28000-29FFF 19 256 26000-27FFF 18 256 24000-25FFF 17 256 22000-23FFF 16 256 20000-21FFF 15 256 1E000-1FFFF 14 256 1C000-1DFFF 13 256 1A000-1BFFF 12 256 18000-19FFF 11 256 16000-17FFF Address Range 10 256 14000-15FFF 9 256 12000-13FFF 8 256 10000-11FFF 7 256 0E000-0FFFF 6 256 0C000-0DFFF 5 256 0A000-0BFFF 4 256 08000-09FFF 3 256 06000-07FFF 2 256 04000-05FFF 1 256 02000-03FFF 0 256 00000-01FFF Overlay Block 256 00000-01FFF status or signatures read from the memory, or they input data to be programmed or Instruction commands to the Command Interface. Asynchronous mode Memory control is provided by Chip Enable E, Output Enable G and Write Enable W for read and write operations. Synchronous mode Memory control is provided by Load Burst Address LBA which loads a read or write address. A Synchronous Single Read or a Synchronous Burst Read is performed under control of Output Enable G. Synchronous Write is controlled by Write/Read Enable WR, Load Burst Address LBA and Write Enable W. Internal advance of the burst address is controlled by Burst Address Advance BAA. SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs (A0-A17). The address signal A17 is the MSB and A0 the LSB. In the Asynchronous mode the addresses must be stable before Chip Enable E and Write Enable W go to VIL. They must remain stable during the read or write cycle. In the Synchronous modes, the addresses are latched by the rising edge of the System Clock CLK when both Latch Burst Address LBA and Chip Enable E are at VIL. The addresses are latched for a read operation if Write/Read WR is at VIH or for a write operation when it is at VIL. Data Input/Output (DQ0-DQ31). The data signal DQ31 is the MSB and DQ0 the LSB. Commands are input on DQ0-DQ7. Data input is a Double-Word to be programmed in the memory or an Instruction command to the Command Interface. Data is read from the Main or Overlay memory blocks, the Status Register or the Electronic Signature. In the Asynchronous mode data is read when the addresses are stable and Chip Enable E and Output Enable G are at VIL. Commands or address/ data are written when Chip Enable E and Write W are at VIL. In the Synchronous mode, after addresses are latched, data is read on a rising edge of the System Clock CLK when Chip Enable E is at VIL and if Output Enable was at VIL on the previous rising clock edge. Data is written on a rising edge of the System Clock CLK when Chip Enable E and Write Enable W are at VIL. The outputs are high impedance when Chip Enable E or Output Enable G are at VIH, or when Output Disable GD is at VIL. Outputs are also high impedance when System Reset RP is at VIL. 5/36 M58BF008 System Clock (CLK). All synchronous signals are input and output relative to the System Clock. Synchronous input signals must respect the setup and hold times relative to the System Clock rising edge. Reset/Power-down (RP). The Reset/Powerdown RP input provides a hardware reset for the memory. When Reset/Power-down RP is at VIL the memory is reset and in the Power-down mode. In this mode the outputs are high impedance and the current consumption is minimised. When Reset/Power-down RP is at VIH the memory is in the normal operating mode. When leaving the Powerdown mode the memory enters the Asynchronous Read Array mode. Reset/Power-down has a weak pull-up resistor to VDDQ and will assume a high level if not connected. Chip Enable (E). When the Chip Enable E input is at VIL it activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable E is at VIH the memory is deselected and the power consumption is reduced to the standby level. Output Enable (G). Output Enable G controls the data output buffers. In the Asynchronous mode data is output when Output Enable G is at VIL. In the Synchronous mode, Output Enable G is sampled on the rising edge of the System Clock CLK. If Output Enable E is at VIL then valid output data on DQ0-DQ31 can be read at the next rising edge of the System Clock CLK. Output Disable (GD). In the Asynchronous mode the data outputs DQ0-DQ31 are high impedance when Output Disable GD is at VIL, irrespective of the state of Output Enable G. In Synchronous mode Output Disable GD is sampled, together with Output Enable G, on the rising edge of the System Clock CLK. If Output Disable is at VIL then the data outputs DQ0-DQ31 are high impedance at the next rising edge of the System Clock CLK, irrespective of the state of Output Enable G. Output Disable has a weak pull-up resistor to VDDQ and will assume a high level if not externally connected. Write Enable (W). The Write Enable W input controls the writing of commands or input data. In the Asynchronous mode commands or data are written when Chip Enable E and Write Enable W are at VIL. In the Synchronous mode with Chip Enable E at VIL, input data is sampled if Write Enable W is at VIL on the rising edge of the System Clock CLK. 6/36 Load Burst Address (LBA). In the Asynchronous mode Load Burst Address LBA is Don’t Care (but if it falls during an asynchronous read then a new read cycle is started). In the Synchronous mode Load Burst Address LBA enables latching of the burst starting address for Synchronous read or write. The address is latched on the rising edge of the System Clock CLK if Load Burst Address LBA is at VIL. Write/Read (WR). Write/Read WR is used in Synchronous mode to control write or read operations. If Load Burst Address LBA is at VIL and Write/Read is at VIL then the rising edge of the System Clock CLK latches a write address. If Write/Read is at VIH then a read address is latched. Write/Read has a weak pull-up resistor to VDDQ and will assume a high level if not externally connected. Burst Address Advance (BAA). When Burst Address Advance BAA is at VIL, the rising edge of the System Clock CLK advances the burst address. When Burst Address Advance BAA is at VIH the advance is suspended. VDD Supply Voltage. The supply VDD provides the power to the internal circuits of the memory. The V DD supply voltage is 4.5 to 5.5V. VDDQ Input/Output Supply Voltage. The Input/ Output supply VDDQ provides the power for the input/outputs of the memory, independent from the supply VDD. The Input/Output supply VDDQ may be connected to the VDD supply or it can use a separate supply of 3.0 to 3.6V. VPP Program/Erase Supply Voltage. The Program/Erase supply VPP is used for programming and erase operations. The memory normally executes program and erase operations at the supply VPP1 voltage levels. In a manufacturing environment, programming may be speeded up by applying a higher VPPH level to the VPP Program/Erase Supply. This is not intended for extended use. The VPPH supply may be applied for a total of 80 hours maximum and during program and erase for a maximum of 1000 cycles. Stressing the device beyond these limits could damage the device. When VPP Program/Erase supply is at VSS all blocks are protected from programming or erase. Leaving VPP floating is equivalent to connecting it to VSS due to an internal pull-down circuit. Ground (V SS and VSSQ ). The Ground VSS is the reference for the internal supply voltage VDD . The Ground VSSQ is the reference for the Input/Output supply VDDQ. M58BF008 DEVICE OPERATIONS See Table 4 for Asynchronous or Synchronous Bus Operations. In the Asynchronous mode the memory is selected with Chip Enable E Low. The data outputs are enabled by Output Enable G Low or disabled by Output Disable GD Low. Data is input by Write Enable W Low. In the Synchronous mode the memory latches addresses and data (input or output) on the rising edge of the System Clock CLK. Burst address latching is enabled by Load Burst Address LBA Low with Write/Read WR Low for a write cycle or High for a read cycle. Data outputs are enabled for reading on the rising edge of the System Clock CLK when Output Enable G is low. Data is input on the rising edge of the System Clock CLK when Write Enable W is Low. The memory is deselected and in standby mode when Chip Enable E is High, and it is reset or in power-down mode when Reset/Power-Down RP is Low. Read. Read operations are used to output the contents of the memory, the Electronic Signature or the Status Register. The data read depends on the previous Instruction given to the memory. Read operations can be Asynchronous or Synchronous, with a single or burst read. On power-up the device is in Asynchronous read mode, the Instruction Asynchronous/Synchronous Read Toggle ART can be used to enter the Synchronous read mode. – Asynchronous Read. To read a data DoubleWord in Asynchronous mode the address inputs must be stable and Chip Enable E must be Low during the read cycle. Output Enable G must be Low and Output Disable GD High. The Load Burst Address LBA is Don’t Care, but its falling edge will start a new read cycle. Table 4. Bus Operations (1,2) Operation RP CLK E LBA WR W GD G DQ0-DQ31 Asynchronous Read V IH X V IL X X VIH VIH VIL Data Output Asynchronous Write V IH X V IL X X VIL VIH VIH Data Input Synchronous Read V IH V IL VIH V IH X VIH VIL Data Output Synchronous Write Address for Read V IH V IL VIL V IH X VIH VIH X Synchronous Write Address for Command V IH V IL VIL VIL X VIH VIH X Synchronous Data Write V IH V IL VIH V IH VIL VIH VIH Data Input Output Disabled by G V IH X V IL X X X VIH VIH Hi-Z Output Disabled by GD V IH X V IL X X X V IL X Hi-Z Standby V IH X VIH X X X X X Hi-Z Reset / Power-down VIL X X X X X X X Hi-Z Note: 1. See Device Operations, Instructions and Commands, sections for more details. 2. X=VIL or VIH. Table 5. Read Electronic Signature Code RP E G W A0 A1 A2-A17 DQ0-DQ31 Manufacturer VIH VIL VIL VIH VIL V IL Don’t Care 00000020h Device VIH VIL VIL VIH V IH V IL Don’t Care 000000F0h Version VIH VIL VIL VIH VIL VIH Don’t Care 0000000xh Note: ”x” = version level. The first version is ”0” and it can have a value up to ”7”. 7/36 M58BF008 – Synchronous Single Read. To read a single data Double-Word in Synchronous mode Chip Enable E must be Low. Load Burst Address LBA must be Low for one System Clock CLK rising edge with Write/Read WR High. This latches the read address, after which the address bus inputs are Don’t Care. The Output Enable G is Low for a single System Clock CLK cycle. The Double-Word of valid data is output on the next System Clock CLK rising edge. – Synchronous Burst Read. To read a burst of four Double-Words in Synchronous mode Chip Enable /E must be Low. Load Burst Address LBA must be Low for one System Clock CLK rising edge with Write/Read WR High. This latches the first address of the burst sequence, after which the address bus inputs are Don’t Care. The Output Enable G is driven Low before the burst output sequence. Four Double-Words of data are output on the subsequent System Clock CLK rising edges if Burst Address Advance BAA is maintained Low. The address advance for synchronous burst read is suspended if Burst Address Advance BAA goes High and the output data remains constant. The data bus will go high impedance on the rising edge of the System Clock CLK after Output Enable G goes High. The burst timing depends on the device configuration for the Critical Word X and Burst Word Y latency times and the choice of wrap or no-wrap for burst addresses. The operation burst wrap is shown in Table 13. The wrap sequence uses only the address bits A0 and A1 and does not repeat after the last Double-Word has been output. Read Overlay Block. The Overlay block can be read, as for a Main block, after it has been enabled. To enable the Overlay block the Overlay Block Enable bit OBEB and the Overlay Block Status bit OBS in the Status Register must be set to ’1’ - see Table 9. The Overlay Block Enable bit OBEB can be set to ’1’ in three ways - see Table 10: – By Toggling the Reset/Power-Down signal RP with the VPP Program/Erase supply in the range VPP1 or VPPH. VPP out of range will reset the OBEB bit to ’0’. – By a leaving power-on reset with VPP Program/ Erase supply in the range VPP1 or VPPH. VPP out of range will reset the OBEB bit to ’0’. – By giving the Overlay Block Enable/Disable for Read Instruction OBT. The Overlay Block Status bit OBS monitors the VPP Program/Erase supply and will be set to ’1’ when in the range VPP1 or VPPH. The Overlay block is enabled with OBEB at ’1’ but will not be read unless OBS status bit is also at ’1’. If it is not 8/36 then a read operation will read the contents of the Main block at the same address. When the Overlay block is enabled for reading, only this one block of 256 Kbit is accesible and none of the other Main blocks may be accessed, the address signals A13-A17 are Don’t Care. Read Electronic Signature. The memory contains three Electronic Signature codes identifying the manufacturer, device and version, which can be read after giving the Instruction RSIG. The manufacturer code 00000020h is read when the address inputs A0 and A1 are at VIL. The device code 000000F0h is read when A0 is at V IH and A1 is at VIL. The version code 0000000xh is read when A0 is at VIL and A1 is at VIH. The codes are read on DQ0-DQ31, all other address signal inputs are Don’t Care. See Table 5. Write. Write operations are used to give commands to the memory that latch input data and addresses to program or block addresses to erase. – Asynchronous Write. To write data in the Asynchronous mode the address inputs must be stable and Chip Enable E must be Low during the write cycle. Write W must be Low and input data valid on the rising edge is Write W. – Synchronous Write. To write input data in Synchronous mode Chip Enable E must be Low. Load Burst Address LBA must be Low for one System Clock CLK rising edge with Write/ Read WR Low. This latches the write address, after which the address bus inputs are Don’t Care. When Write Enable W is Low input data is latched on the next System Clock CLK rising edge. Output Disable. The data outputs are high impedance when the Output Enable G is High or when the Output Disable GD is Low, independent of the level on Output Enable G. Standby. The memory is in standby when the P/ E.C. is not running, the memory is in read mode and Chip Enable E is High. The power consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable G or Write Enable W inputs. If Chip Enable goes High during a program or erase operation the device enters the standby mode when the internal algorithm has finished. Reset/Power-down. During power-down all internal circuits are switched off, the memory is deselected and the outputs are high impedance. The memory is in Power-down mode when Reset/Power-down RP is Low. The power consumption is reduced to the power-down level, independent of the Chip Enable E, Load Burst Address LBA, Output Enable G or Write Enable W inputs. If Reset/Power-down RP is pulled Low during a program or erase operation this is aborted and the memory content is no longer valid. M58BF008 INSTRUCTIONS AND COMMANDS The Instructions are listed in Tables 6 and 7. They may be broadly divided into two types, those that access or modify the memory content and those that toggle a mode or function. The Instructions that access or modify the memory content include: – Read Memory Array (RD) – Read Status Register (RSR) and Clear Status Register (CLRS) – Read Electronic Signature (RSIG) – Erase (EE) and Overlay Block Erase (OBEE) – Program (PG) and Overlay Block Program (OBPG) – Program or Erase Suspend (PES) and Program or Erase Resume (PER) The Instructions that toggle a mode or function include: – Asynchronous/Synchronous Read mode Toggle (ART) – Wrap/No-wrap Burst mode Toggle (WBT) – Overlay Block Enable/Disable function Toggle (OBT) Instructions are written, in one or more write cycles, to the memory Command Interface (C.I.) for decoding. The Command Interface is reset to Read Memory Array at power-up, when exiting from power-down. Any invalid sequence of commands will also reset the Command Interface to Read Memory Array. A Program/Erase Controller (P/E.C.) handles all the timing and verifies the correct execution of the Program or Erase instructions. The P/E.C. has a Status Register which monitors the operations and which may be read at any time during program or erase. The Status Register bits indicate the operation and exit status of the internal algorithms. The V PP Program and Erase Supply Voltage must be within the range VPP1 or VPPH for programming or erasure. If VPP out of range, the program or erase algorithms do not start and Status Register bit VPP Status VPPS will be set to ’1’. Table 6. Commands Code Command 02h Overlay Block Erase Set-up 04h Overlay Block Program Set-up 06h Overlay Block Read Enable/ Disable 0Dh Overlay Block Erase Confirm 20h Erase Set-up 30h Wrap/No-wrap Burst Toggle 40h Program Set-up 50h Clear Status Register 60h Asynchronous/Synchronous Read Toggle 70h Read Status Register 90h Read Electronic Signature B0h Program/Erase Suspend D0h Program/Erase Resume or Erase Confirm FFh Read Memory Array 9/36 M58BF008 Table 7. Instructions 1st Cycle Mnemonic Instruction RD Read Memory Array RSR 2nd Cycle Cycles Operation Address Data Operation Address. Data 1+ Write 00000h FFh Read Read Address Data Output Read Status Register 1+ Write 00000h 70h Read X Status Register CLRS Clear Status Register 1 Write 00000h 50h RSIG Read Electronic Signature 1+++ Write 00000h 90h Read Signature Address Electronic Signature EE Erase 2 Write 00000h 20h Write Block Address D0h OBEE Overlay Block Erase 2 Write 00000h 02h Write Overlay Block Address 0Dh PG Program 2 Write 00000h 40h Write Program Address Data Input OBPG Overlay Block Program 2 Write 00000h 04h Write Overlay Block Program Address Data Input PES Program/Erase Suspend 1 Write 00000h B0h PER Program/Erase Resume 1 Write 00000h D0h ART Asynch/Synch Read Toggle 1 Write 00000h 60h WBT Wrap//No-wrap Burst Toggle 1 Write 00000h 30h OBT Overlay Block Read En/Dis Toggle 1+ Write 00000h 06h Read Read Address Data Output Read Memory Array (RD). The Read Memory Array instruction consists of one write cycle giving the command FFh at the address 00000h. Subsequent read operations will read the addressed location and output the memory data. The data can be read from the Main memory Array or the Overlay memory block if it is enabled. Read Status Register (RSR). The Read Status Register instruction consists of one write cycle giving the command 70h at the address 00000h. Subsequent read operations will output the Status Register contents. See Table 8 for an explanation of the Status Register bits. The Status Register indicates when a program or Erase operation is complete and its success or failure. The Status Register also indicates if the Overlay block is accessible for reading. The Read Status Register instruction may be given at any time, including while a program or erase operation in progress. 10/36 Clear Status Register (CLRS). The Clear Status Register instruction consists of one write cycle giving the command 50h at the address 00000h. The Clear Status Register command clears the bits 3, 4 and 5 of the Status Register if they have been set to ’1’ by the P/E.C. operation. The Clear Status Register command should be given after an error has been detected and before any new operation is attempted. A Read Memory Array command should also be given before data can be read from the memory array. Read Electronic Signature (RSIG). The Read Electronic Signature instruction consists of a first write cycle giving the command 90h at the address 00000h. This is followed by three read operations at addresses xxxx0h, xxxx1h and xxxx2h which output the manufacturer, device and version codes respectively. M58BF008 Table 8. Status Register Bits Mnemonic Bit P/ECS 7 PESS ES PS VPPS 6 5 4 3 Reserved 2 OBEB 1 OBS 0 Name Logic Level Definiti on ’1’ Ready ’0’ Busy ‘1’ Suspend ‘0’ In Progress or Completed Indicates the P/E.C. status, check during Program or Erase P/E.C. Status Program/Erase Suspend Status Note On Program/Erase Suspend instruction both P/ECS and PESS bits are set to ‘1’. Either ES bit or PS bit is set to ‘1’. PESS and either ES or PS bits remain at ‘1’ until Erase Resume instruction is given. ’1’ Erase Error or Erase Suspend ’0’ Erase Success ’1’ ’0’ Program Error or PS bit is set to ‘1’ if either PESS instruction is Program Suspend given or Program operation fails. If PS bit is ‘1’, Program Success check PESS bit. ’1’ VPP Invalid ’0’ VPP OK Overlay Block Enable Bit ’1’ Enabled ’0’ Disabled Overlay Block Status ’1’ Activated ’0’ Not Activated Erase Status Program Status VPP Status Erase (EE). The Erase instruction consists of two write cycles, the first is the erase set-up command 20h at the address 00000h. This is followed by the Erase Confirm command D0h written to an address within the block to be erased. If the second is not the Erase Confirm command the Status Register bits 4 and 5 are set to ’1’ and the instruction aborts. While erasing is in progress only the Read Status Register and Erase Suspend instructions are valid. Blocks are erased one at a time. An erase operation sets all bits in a block to ’1’. The erase algorithm automatically programs all bits to ’0’ before erasing the block to all ’1’s. Read operations output the Status Register after the erase operation has started. The Status Register bit 7 is ’0’ while the erase is in progress and is set to ’1’ when it is completed. After completion the Status Register bit 5 is set to ’1’ if there has been an erase failure. Erasure should not be attempted when the VPP Program/Erase Supply Voltage is out of the range VPP1 or VPPH as the results will be uncertain. The ES bit is set to ‘1’ if either PESS instruction is given or Erase operation fails. If ES bit is ‘1’, check PESS bit. VPPS bit is set to ‘1’ if initially VPP is not VPPH nor VPP1, when Program or Erase Instruction are executed. OBEB bit is set to ‘1’ when Overlay Block is Enabled. OBS bit is set to ‘1’ when OBEB is ‘1’ and VPP is in the range VPP1 or V PPH. Status Register bit 3 is set to ’1’ if VPP is not within the allowed ranges when erasing is attempted or if it falls out of the ranges during erase execution. The erase operation aborts if VPP drops out of the allowed range or if Reset/Power-down RP falls to VIL. As data integrity cannot be guaranteed when the erase operation is aborted, the erase must be repeated. A Clear Status Register instruction must be given to clear the Status Register bits. Overlay Block Erase (OBEE). The Overlay Block Erase instruction consists of two write cycles, the first is the Overlay block erase set-up command 02h at the address 00000h. This is followed by the Overlay Block Erase Confirm command 0Dh written to an address within the Overlay block. If the second is not the Overlay Block Erase Confirm command the Status Register bit 5 is set to ’1’ and the instruction aborts. While erasing is in progress only the Read Status Register instruction is valid. The operation is executed as described for the Erase (EE) instruction of the Main memory array. A Clear Status Register instruction must be given to clear the Status Register bits. 11/36 M58BF008 Program (PG). The Program instruction consists of two write cycles, the first is the program set-up command 40h at the address 00000h. This is followed by a second write cycle to latch the address and data to be programmed. This second command starts the P/E.C. A program operation can be aborted by writing FFFFFFFFh to any address after the program set-up command has been given. While programming is in progress only the Read Status Register and Program Suspend instructions are valid. Read operations output the Status Register after the program operation has started. The Status Register bit 7 is ’0’ while programming is in progress and is set to ’1’ when it is completed. After completion the Status Register bit 4 is set to ’1’ if there has been a programming failure. Programming should not be attempted when the VPP Program/Erase Supply Voltage is out of the range VPP1 or VPPH as the results will be uncertain. The Status Register bit 3 is set to ’1’ if VPP is not within the allowed ranges when programming is attempted or if it falls out of the ranges during program execution. The program operation aborts if VPP drops out of the allowed ranges or if Reset/Power-Down RP falls to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory block must be erased and programming repeated. A Clear Status Register instruction must be given to clear the Status Register bits. Overlay Block Program (OBPG). The Overlay Block Program instruction consists of two write cycles, the first is the program set-up command 04h at the address 00000h. This is followed by a second write cycle to latch the address and data to be programmed. This second command starts the P/ E.C. The operation is executed as described for the Program (PG) instruction of the Main memory array. While programming of the Overlay block in progress only the Read Status Register instruction is valid. Program/Erase Suspend (PES). As memory erasure takes of the order of seconds to complete and programming a few microseconds, a Program/Erase Suspend instruction is implemented. Program/Erase Suspend interrupts the operations to allow reading or programming in a block other than one in which program or erase is suspended. A Program/Erase Suspend instruction is accepted only during a Program or Erase instruction. When the Program/Erase Suspend command is written to the Command Interface, the P/E.C. freezes the 12/36 program or erase operation. The suspended program or erase operation may be restarted by using the Program/Erase Resume instruction. Program/ Erase Suspend is not allowed during the Overlay block program/erase operation and the command is ignored. The Program/Erase Suspend instruction consists of one write cycle giving the command B0h at the address 00000h. If a program operation is in progress when the instruction is given, the Status Register bits 4 and 6 are set to ’1’ after it has been suspended. If an erase operation is in progress when the instruction is given, the Status Register bits 5 and 6 are set to ’1’ after it has been suspended. The valid instructions that may be given to the memory while programing is suspended are – Read Memory Array (RD) – Read Status Register (RSR) – Read Electronic Signature (RSIG) – Program/Erase Resume (PER) In addition, while erasure is suspended, the Program (PG) instruction may be given. In Program/Erase Suspend mode the memory can be placed in a pseudo-standby mode by taking Chip Enable /E to VIH to reduce power consumption. Program/Erase Resume (PER). If a Program/ Erase Suspend instruction has previously been executed, then the operation may be resumed by giving the command D0h at the address 00000h. The Status Register bits 4, 5 and 6 are cleared when program or erase resumes. A Read Memory Array instruction will output the Status Register after program or erase is resumed. Suggested flow charts for software that uses programming, erasure and program/erase suspend/ resume operations are shown in Figures 11, 12, 13 and 14. Asynchronous/Synchronous Read Toggle (ART). Asynchronous Read Memory Array is the memory default at power-up or when returning from PowerDown. To read data in Synchronous mode, either single or burst, the Asynchronous/Synchronous Read Toggle instruction must be used. The Asynchronous/Synchronous Read Toggle instruction consists of one write cycle giving the command 60h at the address 00000h. Two consecutive instructions are not recognised and another Instruction, for example the Read Memory Array, must be given before another Asynchronous/Synchronous Read Toggle will be recognised. M58BF008 Wrap/No-wrap Burst Toggle (WBT). The default for burst read is set by the device configuration. The Wrap/No-wrap Burst Toggle can be used to toggle the burst wrap operation. The Wrap/No-wrap Burst Toggle instruction consists of one write cycle giving the command 30h at the address 00000h. Two consecutive instructions are not recognised and another Instruction, for example the Read Memory Array, must be given before another Wrap/No-wrap Burst Toggle will be recognised. Overlay Block Read Enable/Disable Toggle (OBT). Read operations in the Overlay block can be enabled or disabled using the Overlay Block Read Enable/Disable Toggle instruction. This toggle instruction consists of one write cycle giving the command 06h at the address 00000h. Two consecutive instructions are not recognised. The Status Register bit 1 is set to ’1’ when the Overlay block is enabled. Table 9. Read Access to Overlay Block or Main Block OBEB Status Bit VPP OBS Status Bit Read Access 1 In the range VPP1 or VPPH 1 Overlay Block 1 Out of the range VPP1 or VPPH 0 Main Block 0 X 0 Main Block 1 Unknown Not guaranteed Unknown Table 10. Overlay Block Enable/Disable Bit (OBEB) OBEB Status Bit Method Toggle RP (1) VPP Prior state of OBEB Next state of OBEB In the range VPP1 or VPPH X 1 Out of the range VPP1 or VPPH X 0 In the range VPP1 or VPPH X 1 Out of the range VPP1 or VPPH X 0 – 0 1 – 1 0 Power-on-reset Overlay Block Read Enable/Disable instruction OBT Note: 1. Toggle H-L-H for tPLPH minimum. 13/36 M58BF008 CONFIGURATION The M58BF008 is configured during testing which sets the default for the write and burst interface. The settings are: Write Interface. The write interface can be set permanently to either Asynchronous or Synchronous. Note that the read interface is not affected by this configuration and defaults to Asynchronous read at power-up, it can be toggled to Synchronous read and back using the Asynchronous/Synchronous Read Toggle Instruction. Wrap/No-Wrap. The burst function can be set to default to wrap or no-wrap. The behaviour is shown in Table 13. Wrap/No-wrap can be toggled using the Wrap/No-wrap Burst Toggle Instruction. Critical Word and Burst Word Latency Times. The Critical Word and Burst Word latency times can be set permanently to – Critical Word Latency Time X = 3 or 4 – Burst Word Latency Time Y = 1 or 2 A burst sequence is described as X-Y-Y-Y. Table 11. Configuration Name Option 1 Optio n 2 Synchronous Asynchronous Wrap No-wrap Critical Word Latency Time (X) 4 3 Burst Word Latency Time (Y) 1 2 Write Interface Wrap/No-wrap Burst Table 12. Wrap/No-wrap Burst Sequence First Burst Address A1-A0 Data Wrap 00 Double-Word 0 ⇒ 1 ⇒ 2 ⇒ 3 Double-Word 0 ⇒ 1 ⇒ 2 ⇒ 3 01 Double-Word 1 ⇒ 2 ⇒ 3 ⇒ 0 Double-Word 1 ⇒ 2 ⇒ 3 10 Double-Word 2 ⇒ 3 ⇒ 0 ⇒ 1 Double-Word 2 ⇒ 3 11 Double-Word 3 ⇒ 0 ⇒ 1 ⇒ 2 Double-Word 3 POWER SUPPLY The M58BF008 places itself in one of three different modes depending on the status of the control signals which define decreasing levels of current consumption. This minimises the memory power consumption, allowing an overall decrease in the system power consumption without affecting performance. A different recovery time is, however, linked to the different modes - see the AC timing tables. Active Power mode. When Chip Enable E is at VIL and Reset/Power-Down RP is at VIH the memory is in Active Power mode. The DC characteristics tables show the current consumption figures. Standby mode. Refer to the Device Operating section Power-Down mode. Refer to the Device Operating section. 14/36 Data No-wrap Power Up. The VDD Supply Voltage, VDDQ Input/ Output Supply Voltage and the VPP Program/ Erase Supply Voltage can be applied in any order. The memory Command Interface is reset on power-up to Read Memory Array, but a negative transition on Chip Enable E or a change of the addresses is required to ensure valid data is output. Care must be taken to avoid writes to the memory when the VDD Supply Voltage is above VLKO and VPP Program/Erase Supply Voltage powers-up first. Writes can be inhibited by driving either Write Enable W or Write/Read WR to VIH. The memory is disabled until Reset/Power-Down RP is up to VIH. SUPPLY RAILS Normal precautions must be taken for supply rail decoupling. Each device in a system should have the VDD, VDDQ and VPP rails decoupled with a 0.1µF capacitor close to the package pins. PCB track widths should be sufficient to carry the required program and erase currents on the VPP supply. M58BF008 Table 13. AC Measurement Conditions Input Rise and Fall Times Figure 5. AC Testing Load Circuit ≤ 10ns VDDQ/2 0 to VDDQ Input Pulse Voltages Input and Output Timing Ref. Voltages VDDQ/2 1N914 3.3kΩ Figure 4. AC Testing Input Output Waveform DEVICE UNDER TEST VDDQ OUT CL = 80pF VDDQ/2 0V AI00610 CL includes JIG capacitance AI02657 Table 14. Capacitance (1) (TA = 25 °C, f = 1MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition Min Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF Note: 1. Sampled only, not 100% tested. 15/36 M58BF008 Table 15. DC Characteristics (TA = –40 to 125°C; VDD = 5V ± 10% and VDDQ = 3.3V ± 0.3V) Symbol Parameter Test Conditi on Min Max Unit ILI Input Leakage Current 0V≤ VIN ≤ VDDQ ±1 µA ILO Output Leakage Current 0V ≤ VOUT ≤VDDQ ±10 µA ILT1 Input Leakage Current pull-up 0V≤ VIN ≤ VDDQ –600 µA 0≤ V PP ≤ 12.6 200 µA ILIVPP Input Leakage Current pull-down –20 ICC Supply Current (Async. Read) E = VIL, G = VIL, f = 5MHz 25 mA ICCB Supply Current (Burst Read) E = VIL , G = V IL, f = 40MHz 25 mA ICC1 Supply Current (Standby) E = VIH, RP = VIH 10 µA ICC2 Supply Current (Power-down) RP = VIL 10 µA Supply Current (Program) Program in Progress V PP = VPP1 25 mA ICC3 VPP = VPPH 25 mA Supply Current (Erase) Erase in Progress V PP = VPP1 25 mA ICC4 VPP = VPPH 25 mA IPP Program Current (Read or Standby) VPP ≥ VPP1 200 µA IPP1 Program Current (Read or Standby) VPP ≤ VPP1 ±15 µA IPP2 Program Current (Power-down) RP = VIL 5 µA Program Current (Program) Program in Progress V PP = VPP1 15 mA IPP3 VPP = VPPH 25 mA V PP = VPP1 15 mA VPP = VPPH 25 mA IPP4 Program Current (Erase) Erase in Progress VIL Input Low Voltage –0.3 0.1V DDQ V VIH Input High Voltage 0.9V DDQ V DDQ +0.3 V VOL Output Low Voltage IOL = 100µA, VDD = VDD min, V DDQ = VDDQ min 0.2 V VOH Output High Voltage I OL = –100µA, VDD = VDD min, V DDQ = VDDQ min VPP1 Program Voltage (Program or Erase operations) 4.5 5.5 V V PPH Program Voltage (Program or Erase operations) 11.4 12.6 V VLKO VDD Supply Voltage Lock-out 1.5 V VPPLK Program Voltage Lock-out 1.5 V 16/36 VDDQ –0.2 V M58BF008 Table 16. Asynchronous Read AC Characteristics (1) (TA = –40 to 125°C; VDD = 5V ± 10% and VDDQ = 3.3V ± 0.3V) Symbol Alt tAVAV tRC Address Valid to Next Address Valid tAVQV tACC Address Valid to Output Valid tAXQX (2) tOH Address Transition to Output Transition 0 ns tEHQX (2) tOH Chip Enable High to Output Transition 0 ns tELQV (2, 3) tCE Chip Enable Low to Output Valid tELQX (2) tLZ Chip Enable Low to Output Transition (2) tHZ Chip Enable High to Output Hi-Z tGHQX (2) tOH Output Enable High to Output Transition tGHQZ (2) tDF Output Enable High to Output Hi-Z 25 ns tGLQV (2) tOE Output Enable Low to Output Valid 30 ns tGLQX tOLZ Output Enable Low to Output Transition tEXQZ Parameter Min Max Unit 100 ns 100 ns 100 ns 0 ns 25 ns 0 ns 0 ns Note: 1. See AC Testing Measurements Conditions for timing measurements. 2. Sampled only, not 100% tested. 3. G may be delayed up to tELQV-tGLQV after falling edge of E without increasing tELQV. Figure 6. Asynchronous Read AC Waveforms tAVAV VALID A12-A29 tAVQV E, LBA tELQV tELQX tEHQX tEHQZ G tGLQX tGLQV tGHQX tGHQZ VALID DQ0-DQ31 tPHQV RP AI03571 17/36 M58BF008 Table 17. Synchronous Read AC Characteristics (1) (TA = –40 to 125°C; VDD = 5V ± 10% and VDDQ = 3.3V ± 0.3V) Symbol Min Max Unit System Clock Duty Cycle 45 55 % Address Valid to System Clock High 10 ns Burst Address Advance Low to System Clock High 10 ns tBLCH (2) Load Burst Address Low to System Clock High 10 ns tCHAX (2) System Clock High to Address Transition 5 ns tCHBH (2) System Clock High to Load Burst Address High 5 ns DCCLK tAVCH (2) tBALCH tCHCL Parameter System Clock Fall Time 3 ns tCHGDH (2) System Clock High to Output Disable High 5 ns tCHGH (2) System Clock High to Output Enable High 5 ns tCHQV (2) System Clock High to Data Valid t CHQX1 (2) System Clock High to Data Transition 0 ns t CHQX2 (2) System Clock High to Data Transition 5 ns tCHQZ (2) System Clock High to Data Hi-Z 20 ns tCLCH System Clock Rise Time 3 ns tCLCL System Clock Period 25 ns tELCH Chip Enable Low to System Clock High 20 ns tGDLCH (2) Output Disable Low to System Clock High 10 ns tGLCH (2) Output Enable Low to System Clock High 10 ns Reset/Power-down High to Load Burst Address Low 20 ns Write/Read High to System Clock High 10 ns tPHBL tWRHCH Note: 1. See AC Testing Measurement Conditions for timing measurements. 2. Sampled only, not 100% tested. 18/36 20 ns M58BF008 Figure 7. Synchronous Single Read AC Waveforms CLK tAVCH A0-A17 tCHAX VALID LBA tBLCH tCHBH G tGLCH tCHGH E tELCH DQ0-DQ31 tCHQV tCHQZ tCHQX1 tCHQX2 VALID tPHBL RP tWRHCH WR AI02658 19/36 M58BF008 Figure 8. Synchronous Burst Read AC Waveforms CLK tAVCH A0-A17 tCHAX VALID LBA tBLCH tCHBH G tGLCH E tELCH tCHQV tCHQV tCHQX1 tCHQX2 DQ0-DQ31 VALID tCHQX2 VALID tPHBL RP tWRHCH WR tBALCH BAA AI03583 20/36 M58BF008 Table 18. Asynchronous Write AC Characteristics (1) (TA = –40 to 125°C; VDD = 5V ± 10% and VDDQ = 3.3V ± 0.3V) Symbol Alt tAVAV tWC Write Cycle Time 70 ns tAVWH tAS Address Valid to Write Enable High 70 ns tDVWH tDS Data Valid to Write Enable High 70 ns tELWL tCS Chip Enable Low to Write Enable Low 0 ns tPHWL tPS Reset/Power-down High to Write Enable Low 70 ns Output Valid to VPP out of the range VPP1 or V PPH 0 ns 200 ns tQVVPL (2) Parameter Min Max Unit tVPHWH (2) tVPS VPP High to Write Enable High tWHAX tAH Write Enable High to Address Transition 0 ns tWHDX tDH Write Enable High to Data Transition 0 ns tWHEH tCH Write Enable High to Chip Enable High 0 ns tWHQV1 (3) Write Enable High to Output Valid, Program 10 µs tWHQV2 (3) Write Enable High to Output Valid, Erase 2.1 sec tWHWL tWPH Write Enable High to Write Enable Low 30 ns tWLWH tWP Write Enable Low to Write Enable High 70 ns Note: 1. See AC Testing Measurement conditions for timing measurements. 2. Sampled only, not 100% tested. 3. Time is measured to Status Register Read giving bit b7 = ’1’. 21/36 M58BF008 Figure 9. Asynchronous Write AC Waveforms tAVAV A0-A17 00000h VALID tWHAX tAVWH G E tELWL tWHEH tWLWH tWHWL W tDVWH DQ0-DQ31 tWHQV1,2 tWHDX COMMAND or DATA COMMAND STATUS REGISTER tQVVPL tVPHWH VPP tPHWL RP WR WRITE WRITE READ AI02660 22/36 M58BF008 Table 19. Synchronous Write AC Characteristics (1) (TA = –40 to 125°C; VDD = 5V ± 10% and VDDQ = 3.3V ± 0.3V) Symbol Min Max Unit System Clock Duty Cycle 45 55 % tAVCH (2) Address Valid to System Clock High 10 ns tBLCH (2) Load Burst Address Low to System Clock High 10 ns tCHAX (2) System Clock High to Address Transition 5 ns tCHBH (2) System Clock High to Load Burst Address High 5 ns DCCLK tCHCL Parameter System Clock Fall Time 3 ns t CHQV1 (3) System Clock High to Output Valid, Program 10 µs t CHQV2 (3) System Clock High to Output Valid, Erase 2.1 sec tCHQX (2) System Clock High to Data Transition 5 ns tCHWH (2) System Clock High to Write/Read High 5 ns tCHWRH (2) System Clock High to Write Enable High 5 ns tCLCH System Clock Rise Time 3 ns tCLCL System Clock Period 25 ns tELCH Chip Enable Low to System Clock High tPHCH Reset/Power-down High to System Clock High (2) 20 ns 200 ns Data Valid to System Clock High 10 ns tQVVPL (2) Output Valid to VPP out of range VPP1 or VPPH 0 ns tVPHCH (2) V PP High to System Clock High 200 ns tWLCH (2) Write Enable Low to System Clock High 10 ns Write/Read Low to System Clock High 10 ns tQVCH tWRLCH (2) Note: 1. See AC Testing Measurement conditions for timing measurements. 2. Sampled only, not 100% tested. 3. Time is measured to Status Register Read giving bit b7 = ’1’. 23/36 M58BF008 Figure 10. Synchronous Write AC Waveforms CLK tAVCH A17-A0 tCHAX 00000h VALID LBA tBLCH tCHBH WR tWRLCH tCHWRH W tWLCH tCHWH tQVCH tCHQX DQ31-DQ0 COMMAND tWHQV1,2 COMMAND or DATA STATUS REGISTER tPHCB RP tVPHCH VPP tELCH E WRITE WRITE READ AI02659 24/36 M58BF008 Table 20. Reset/Power-down AC Characteristics (TA = –40 to 125°C; VDD = 5V ± 10% and VDDQ = 3.3V ± 0.3V) Mode Async Symbol Parameter Max Unit tPHEL Reset/Power-down High to Chip Enable Low tPHQV Reset/Power-down High to Output Valid tPHWL Reset/Power-down High to Write Enable Low 70 ns Reset/Power-down Pulse Width 100 ns tPLPH (1) Sync Min 70 ns 100 tPLRH Reset/Power-down Low to Program Erase Abort tPHBL1 Reset/Power-down High to Load Burst Address Low tPHBL2 Reset/Power-down High to Load Burst Address Low 22 20 ns µs ns 22 µs Note: 1. The device Reset is possible but not guaranteed if tPLPH < 100ns. A Reset will complete within 100ns if RP is Low while not in Program or Erase. Figure 11. Reset/Power-down AC Waveforms Reset during Read Mode tPLPH RP tPHQV tPHBL1 Reset during Program with tPLPH ≤ tPLRH Abort Complete tPLRH tPHWL tPHEL tPHBL1 tPLPH RP Reset during Program/Erase with tPLPH > tPLRH Abort Power Complete Down tPLRH tPHWL tPHEL tPHBL2 tPLPH RP AI00624 25/36 M58BF008 Table 21. Program, Erase Times and Program/Erase Endurance Cycles (TA = –40 to 125°C; VDD = 5V ± 10% and VDDQ = 3.3V ± 0.3V) Parameter Test Condition s Min Typ Max Unit VPP = VPPH 0.14 1.4 sec VPP = VPP1 0.18 1.8 sec VPP = VPPH 0.21 2.1 sec VPP = VPP1 0.33 3.3 sec Main/Overlay Block Program Time Main/Overlay Block Erase Time VPP = VPPH 1,000 cycles VPP = VPP1 10,000 cycles Program/Erase Cycles (per Block) Figure 12. Program Flowchart and Pseudo Code Start Write 40h/04h Command PG/OBPG instructions: – write 40h/04h command – write Address & Data (memory enters read status state after the PG instruction) Write Address & Data Read Status Register b7 = 1 do: – read status register (E or G must be toggled) NO while b7 = 1 YES b3 = 0 NO VPP Invalid Error (1) NO Program Error (1) If b3 = 1, VPP invalid error: – error handler YES b4 = 0 If b4 = 1, Program error: – error handler YES End AI02663 Note: 1. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations. 26/36 M58BF008 Figure 13. Program Suspend & Resume Flowchart and Pseudo Code Start Write B0h Command Write 70h Command PES instruction (note 1): – write B0h command (memory enters read register state after the PES instruction) do: – read status register (E or G must be toggled) Read Status Register b7 = 1 NO while b7 = 1 YES b6 = 1 NO YES b4 = 1 NO Program Complete If b4 = 0, Program completed (at this point the memory will accept only the RD or PER instruction) YES Write FFh Command RD instruction: – write FFh command – one or more data reads from another block Read data from another block Write D0h Command Write FFh Command Program Continues Read Data PER instruction: – write D0h command to resume erasure – if the program operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase suspend was not issued). AI02664 Note: 1. PES instruction is not allowed during OBPG operation. 27/36 M58BF008 Figure 14. Erase Flowchart and Pseudo Code Start Write 20h/02h Command EE/OBEE instructions: – write 20h/02h command – write Block Address (A12-A17) & command D0h/0Dh (memory enters read status state after the EE instruction) Write Block Address & D0h Command do: – read status register (E or G must be toggled) Read Status Register b7 = 1 NO while b7 = 1 YES b3 = 0 NO VPP Invalid Error (1) NO Command Sequence Error NO Erase Error (1) If b3 = 1, VPP invalid error: – error handler YES b4, b5 = 0 If b4, b5 = 1, Command Sequence error: – error handler YES b5 = 0 If b5 = 1, Erase error: – error handler YES End AI02680 Note: 1. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations. 28/36 M58BF008 Figure 15. Erase Suspend & Resume Flowchart and Pseudo Code Start Write B0h Command Write 70h Command PES instruction (note 1): – write B0h command (memory enters read register state after the PES instruction) do: – read status register (E or G must be toggled) Read Status Register b7 = 1 NO while b7 = 1 YES b6 = 1 NO YES b5 = 1 NO Erase Complete If b6 = 0, Erase completed (at this point the memory wich accept only the RD or PER instruction) YES Write FFh Command RD instruction: – write FFh command – one o more data reads from another block Read data from another block or Program PG instruction: – write 40h command – write Address & Data Write D0h Command Write FFh Command Program Continues Read Data PER instruction: – write D0h command to resume erasure – if the program operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase suspend was not issued). AI02681 Note: 1. PES instruction is not allowed during OBEE operation. 29/36 M58BF008 Figure 16. Command Interface and Program Erase Controller Flowchart (a) WAIT FOR COMMAND WRITE (1) NO 90h READ ARRAY YES READ SIGNATURE 06h NO YES OBEB TOGGLE 70h NO YES READ STATUS 30h NO YES WRAPPING TOGGLE NO 50h YES CLEAR STATUS 04h NO YES PROGRAM OB SET-UP 02h NO YES YES A ERASE OB SET-UP NO PROGRAM OB READY 0Dh READ STATUS NO YES READY ERASE OB NO ERASE COMMAND ERROR D B AI02682 Note: 1. If no command is written, the Command Interface remains in its previous valid state. Upon power-up, on exit from power-down or if VDD falls below V LKO, the Command Interface defaults to Read Array mode. 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7. 30/36 M58BF008 Figure 17. Command Interface and Program Erase Controller Flowchart (b) A B C 40h NO YES PROGRAM SET UP PROGRAM YES (READ STATUS) READY (2) NO B0h NO YES READ STATUS PROGRAM SUSPEND YES READY (2) NO NO PROGRAM SUSPENDED READ STATUS YES READ STATUS YES 70h NO READ SIGNATURE YES 90h NO READ ARRAY NO D0h YES READ STATUS (PROGRAM RESUME) AI02684 Note: 2. P/E. C. status (Ready or Busy) is read on Status Register bit 7. 31/36 M58BF008 Figure 18. Command Interface and Program Erase Controller Flowchart (c) C B D 20h D0h YES NO ERASE COMMAND ERROR YES ERASE YES NO FFh ERASE SET-UP (READ STATUS) READY (2) NO B0h NO YES READ STATUS ERASE SUSPEND NO ERASE SUSPENDED YES YES READ STATUS YES READY (2) NO READ STATUS 70h NO READ SIGNATURE YES 90h NO PROGRAM SET-UP YES c READ ARRAY 40h or 10h NO NO D0h YES READ STATUS (ERASE RESUME) AI02683 Note: 2. P/E. C. status (Ready or Busy) is read on Status Register bit 7. 32/36 M58BF008 Table 22. Ordering Information Scheme Example: M58BF008B 100 ZA 6 T Device Type M58 Architecture B = Burst Mode Operating Voltage F = VDD = 5V ± 10%; VDDQ = 3.0V or 3.6V Device Function 008 = 8 Mbit (256Kb x 32), Burst Configuration B = Synchronous Write, Burst Wrap, Critical Word Latency = 4 Burst Word Latency = 1 Speed 100 = 100ns Package D = PQFP80 ZA = LBGA80: 1.0 mm pitch Temperature Range 3 = –40 to 125 °C Optio n T = Tape & Reel Packing Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Configuration, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 33/36 M58BF008 Table 23. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Mechanical Data mm inches Symbol Typ Min A Max Typ Min Max 3.40 A1 0.1339 0.25 A2 2.80 0.0098 2.55 3.05 b 0.30 c 0.1102 0.1004 0.1201 0.45 0.0118 0.0177 0.11 0.23 0.0043 0.0091 D 23.90 – – 0.9409 – – D1 20.00 – – 0.7874 – – e 0.80 – – 0.0315 – – E 17.90 – – 0.7047 – – E1 14.00 – – 0.5512 – – L 0.88 0.73 1.03 0.0346 0.0287 0.0406 α 3.5 ° 0° 7° 3.5 ° 0° 7° N 80 80 Nd 24 24 Ne 16 16 CP 0.250 0.0098 Figure 19. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Outline D D1 D2 A2 e Ne E2 E1 E b N 1 Nd A CP c TQFP Drawing is not to scale. 34/36 A1 α L M58BF008 Table 24. LBGA80 - 10 x 8 balls, 1mm pitch, Package Mechanical Data mm inch Symbol Typ Min Max A Typ Min Max 1.700 A1 0.400 0.350 A2 1.100 b 0.500 – – D 12.000 – D1 9.000 – 0.0669 0.450 0.0157 0.0138 0.0177 0.0197 – – – 0.4724 – – – 0.3543 – – 0.0433 ddd 0.150 0.0059 e 1.000 – – 0.0394 – – E 10.000 – – 0.3937 – – E1 7.000 – – 0.2756 – – FD 1.500 – – 0.0591 – – FE 1.500 – – 0.0591 – – SD 0.500 – – 0.0197 – – SE 0.500 – – 0.0197 – – Figure 20. LBGA80 - 10 x 8 balls, 1mm pitch, Bottom View Package Outline E E1 FE FD SE SD D D1 ddd e e b A A2 A1 BGA-Z05 Drawing is not to scale. 35/36 M58BF008 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A . http://w ww.st.com 36/36