STMICROELECTRONICS M74HC165TTR

M74HC165
8 BIT PISO SHIFT REGISTER
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HIGH SPEED :
tPD = 15ns (TYP.) at VCC = 6V
LOW POWER DISSIPATION:
ICC =4µA(MAX.) at TA=25°C
HIGH NOISE IMMUNITY:
VNIH = V NIL = 28 % VCC (MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN)
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 165
DESCRIPTION
The M74HC165 is an high speed CMOS 8 BIT
PISO SHIFT REGISTER fabricated with silicon
gate C2MOS technology.
This device contains eight clocked master slave
RS flip-flops connected as a shift register, with
auxiliary
gating
to
provide
over-riding
asynchronous parallel entry. Parallel data enters
when the shift/load input is low. The parallel data
can change while shift/load is low, provided that
the recommended set-up and hold times are
observed. For clocked operation, shift/load must
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
TSSOP
M74HC165B1R
M74HC165M1R
T&R
M74HC165RM13TR
M74HC165TTR
be high. The two clock input perform identically;
one can be used as a clock inhibit by applying a
high signal; to permit this operation clocking is
accomplished through a 2 input nor gate.
To avoid double clocking, however, the inhibit
signal should only go high while the clock is high.
Otherwise the rising inhibit signal will cause the
same response as rising clock edge.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
1/12
M74HC165
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1
2
7
9
SYMBOL
NAME AND FUNCTION
SHIFT/LOAD Data Inputs
Complementary Output
QH
QH
Serial Output
Clock Input (LOW to
CLOCK
HIGH, Edge Triggered
SI
Serial Data Inputs
10
11, 12, 13,
A to H
14, 3, 4, 5, 6
15
CLOCK INH
8
GND
16
Vcc
Parallel Data Inputs
Clock Inhibit
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUTS
INTERNAL OUTPUTS
OUTPUTS
SHIFT /
LOAD
CLOCK INH
CLOCK
SI
A..........H
QA
QB
QH
L
X
X
X
a..........h
a
b
h
H
L
H
X
H
QAn
QGn
H
L
L
X
L
QAn
QGn
H
L
H
X
H
QAn
QGn
H
L
L
X
L
QAn
QGn
H
X
X
X
X
X
H
H
X
H
a........h : The level of steady input voltage at inputs a through respectively
QAn - QGn : The level of QA - QG, respectively. before the most-recent transition of the clock
LOGIC DIAGRAM
2/12
NO CHANGE
NO CHANGE
M74HC165
TIMING CHART
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Supply Voltage
Value
Unit
-0.5 to +7
V
VI
DC Input Voltage
-0.5 to VCC + 0.5
V
VO
DC Output Voltage
IIK
DC Input Diode Current
-0.5 to VCC + 0.5
± 20
mA
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Current
± 25
mA
ICC or IGND DC VCC or Ground Current
PD
Power Dissipation
Tstg
Storage Temperature
TL
Lead Temperature (10 sec)
V
± 50
mA
500(*)
mW
-65 to +150
°C
300
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
3/12
M74HC165
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Value
Supply Voltage
VI
Input Voltage
VO
Output Voltage
Top
Operating Temperature
Input Rise and Fall Time
tr, tf
Unit
2 to 6
V
0 to VCC
V
0 to VCC
V
-55 to 125
°C
VCC = 2.0V
0 to 1000
ns
VCC = 4.5V
0 to 500
ns
VCC = 6.0V
0 to 400
ns
DC SPECIFICATIONS
Test Condition
Symbol
VIH
VIL
VOH
VOL
II
ICC
4/12
Parameter
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
Low Level Output
Voltage
Input Leakage
Current
Quiescent Supply
Current
Value
TA = 25°C
VCC
(V)
Min.
2.0
4.5
6.0
2.0
4.5
6.0
Typ.
Max.
1.5
3.15
4.2
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
1.5
3.15
4.2
0.5
1.35
1.8
Max.
1.5
3.15
4.2
0.5
1.35
1.8
V
0.5
1.35
1.8
2.0
IO=-20 µA
1.9
2.0
1.9
1.9
4.5
IO=-20 µA
4.4
4.5
4.4
4.4
6.0
IO=-20 µA
5.9
6.0
5.9
5.9
4.5
IO=-4.0 mA
4.18
4.31
4.13
4.10
5.68
Unit
V
V
6.0
IO=-5.2 mA
2.0
IO=20 µA
0.0
0.1
0.1
0.1
4.5
IO=20 µA
0.0
0.1
0.1
0.1
6.0
IO=20 µA
0.0
0.1
0.1
0.1
4.5
IO=4.0 mA
0.17
0.26
0.33
0.40
6.0
IO=5.2 mA
0.18
0.26
0.33
0.40
6.0
VI = VCC or GND
± 0.1
±1
±1
µA
6.0
VI = VCC or GND
4
40
80
µA
5.8
5.63
5.60
V
M74HC165
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
Test Condition
Symbol
Parameter
tTLH tTHL Output Transition
Time
tPLH tPHL Propagation Delay
Time
(CLOCK - QH, QH)
tPLH tPHL Propagation Delay
Time
(SHIFT/LOAD QH, QH)
tPLH tPHL Propagation Delay
Time
(H - QH, QH)
fMAX
Maximum Clock
Frequency
tW(H)
tW(L)
Minimum Pulse
Width
(CLOCK)
tW(L)
Minimum Pulse
Width
(SHIFT/LOAD)
ts
th
tREM
Minimum Set-up
Time
(PI - SHIFT/LOAD)
(SI - CLOCK)
(SHIFT/LOAD - CK)
Minimum Hold
Time
(PI - SHIFT/LOAD)
(SI - CLOCK)
(SHIFT/LOAD - CK)
Minimum Removal
Time
(CLOCK - CK INH)
Value
TA = 25°C
VCC
(V)
Min.
-40 to 85°C
-55 to 125°C
Min.
Min.
Typ.
Max.
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
30
8
7
55
18
15
65
21
75
15
13
150
30
26
165
33
95
19
16
190
38
33
205
41
6.0
18
28
35
43
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
52
17
14
15
60
71
24
6
5
32
8
7
24
6
135
27
23
170
34
29
205
41
35
75
15
13
75
15
13
75
15
95
19
16
95
19
16
95
19
110
22
19
110
22
19
110
22
5
13
16
19
2.0
4.5
0
0
0
0
0
0
6.0
0
0
0
75
15
13
95
19
16
110
22
19
7.4
37
44
6.0
2.0
4.5
6.0
Max.
6.0
30
35
20
5
4
Unit
Max.
110
22
19
225
45
38
ns
ns
250
50
4.8
24
28
ns
ns
MHz
ns
ns
ns
ns
ns
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
VCC
(V)
Value
TA = 25°C
Min.
Typ.
Max.
10
CIN
Input Capacitance
5.0
5
CPD
Power Dissipation
Capacitance (note
1)
5.0
55
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
10
Unit
Max.
10
pF
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
5/12
M74HC165
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: SERIAL MODE PROPAGATION DELAY (f=1MHz; 50% duty cycle)
6/12
M74HC165
WAVEFORM 2: PARALLEL MODE PROPAGATION DELAY (f=1MHz; 50% duty cycle)
WAVEFORM 3: MINIMUM PULSE WIDTH (S/L), PROPAGATION DELAY TIMES
(f=1MHz; 50% duty cycle)
7/12
M74HC165
WAVEFORM 4: SETUP AND HOLD TIME (PI TO S/L) (f=1MHz; 50% duty cycle)
WAVEFORM 5: MINIMUM REMOVAL TIME (CK INH TO CK) (f=1MHz; 50% duty cycle)
8/12
M74HC165
Plastic DIP-16 (0.25) MECHANICAL DATA
mm.
inch
DIM.
MIN.
a1
0.51
B
0.77
TYP
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
Z
3.3
0.130
1.27
0.050
P001C
9/12
M74HC165
SO-16 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.068
0.2
a2
MAX.
0.003
0.007
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45° (typ.)
D
9.8
10
0.385
0.393
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
8.89
0.350
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
S
0.62
0.024
8° (max.)
PO13H
10/12
M74HC165
TSSOP16 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
A
MAX.
MIN.
TYP.
MAX.
1.2
A1
0.05
A2
0.8
b
0.047
0.15
0.002
0.004
0.006
1.05
0.031
0.039
0.041
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0089
D
4.9
5
5.1
0.193
0.197
0.201
E
6.2
6.4
6.6
0.244
0.252
0.260
E1
4.3
4.4
4.48
0.169
0.173
0.176
1
e
0.65 BSC
K
0°
L
0.45
A
0.60
0.0256 BSC
8°
0°
0.75
0.018
8°
0.024
0.030
A2
A1
b
e
K
c
L
E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
11/12
M74HC165
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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12/12