MK5027 SS7 SIGNALLING LINK CONTROLLER CMOS FULLY COMPATIBLE WITH BOTH 8 OR 16 BIT SYSTEMS SYSTEM CLOCK RATE TO 10MHz. DATA RATE UP TO 2.5Mbps FOR SS7 PROTOCOL PROCESSING,7Mbps FOR TRANSPARENT HDLC MODE COMPLETE LEVEL 2 IMPLEMENTATION COMPATIBLE WITH 1988 CCITT, AT&T, ANSI, AND BELLCORE SIGNALLING SYSTEM NUMBER 7 LINK LEVEL PROTOCOLS 52 PIN PLCC AND 48-PIN DIP PIN-FOR-PIN COMPATIBLE WITH THE SGS-THOMSON X.25 CHIP (MK5025) AND NEARLY PIN-FORPIN COMPATIBLE WITH THE SGS-THOMSON VLANCE CHIP (MK5032) BUFFER MANAGEMENT INCLUDES: - Initialization Block - Separate Receive and Transmit Rings - Variable Descriptor Ring and Window Sizes. ON CHIP DMA CONTROL WITH PROGRAMMABLE BURST LENGTH SELECTABLE BEC OR PCR RETRANSMISSION METHODS, INCLUDING FORCED RETRANSMISSION FOR PCR HANDLES ALL 7 SS7 TIMERS HANDLES ALL SS7 FRAME FORMATTING: - Zero bit insert and delete - FCS generation and detection - Frame delimiting with flags PROGRAMMABLE MINIMUM SIGNAL UNIT SPACING (number of flags between SU’s) HANDLES ALL SEQUENCING AND LINK CONTROL SELECTABLE FCS OF 16 OR 32 BITS. TESTING FACILITIES: - Internal Loopback - Silent Loopback - Optional Internal Data Clock Generation - Self Test ALL INPUTS AND OUTPUTS ARE TTL COMPATIBLE PROGRAMMABLE FOR FULL OR HALF DUPLEX OPERATION DESCRIPTION The SGS-THOMSON Signalling System #7 Signalling Link Controller (MK5027) is a VLSI semiAugust 1989 DIP48 PLCC52 conductor device which provides a complete link control function conforming to the 1988 CCITT version of SS7. This includes frame formatting, transparency (so called ”bit-stufling”), error recovery by two types of retransmission, error monitoring, sequence number control, link status control, and FISU generation. One of the outstanding features of the MK5027 is its buffer management which includes on-chip DMA. This feature allows users to handlq multiple packets of receive and transmit data at a time. (A conventional data linkcontrol chip plus a separate DMA chip would handle data for only a single block at a time.) The MK5027 may be used with any of several popular 16 and 8 bit microprocessors, such as 68000, 6800, Z8000, Z80, LSI-11, 8086, 8088, 8080, etc. Figure 1: Pin Connection. 1 48 VCC (+5V) DAL07 2 47 DAL08 DAL06 3 46 DAL09 DAL05 4 45 DAL10 DAL04 5 44 DAL11 DAL03 6 43 DAL12 DAL02 7 42 DAL13 DAL01 8 41 DAL14 DAL00 9 M 40 DAL15 READ 10 K 39 A16 INTR 11 38 A17 DALI 12 37 A18 DALO 13 36 A19 DAS 14 35 A20 34 A21 33 A22 32 A23 VSS-GND BMO, BYTE, BUSREL 15 BMI, BUSAKO 16 HOLD, BUSRQ 17 5 0 H 2 5 ALE, AS 18 31 RD HLDA 19 30 DSR, CTS CS 20 29 TD ADR 21 28 SYSCLK READY 22 27 RCLK RESET 23 26 DTR, RTS 24 25 TCLK VSS-GND 1/19 MK5027 Table 1: Pin Description. LEGEND: I Input only O Output only IO Input/Output 3S 3-State OD Open Drain (no internal pull-up) Signal Name Pin(s) Type DAL<15:00> 2-9 40-47 IO/3S The time multiplexed Data Address bus. During the address portion of a memory transfer, DALe15:00 contains the lower 16 bits of the memory address. During the data portion of a memory transfer, DAL<15:00> contains the read or write data, depending on the type of transfer. READ 10 IO/3S READ indicates the type of operation that the bus controller is performing during a bus transaction. READ is driven by the MK5027 only while it is the BUS MASTER. READ is valid during the entire bus transaction and is tristated at all other times. MK5027 as a Bus Slave: READ = HIGH - Data is placed on the DAL lines by the chip. READ = LOW - Data is taken off the DAL lines by the chip. MK5027 as a Bus Master: READ = HIGH - Data is taken off the DAL lines by the chip. READ = LOW - Data is placed on the DAL lines by the chip. INTR 11 O/OD INTERRUPT is an attention interrupt line that indicates that one or more of the following CSR0 status flags is set: MISS, MERR, RINT, TINT or PINT. INTERRUPT is enabled by CSR0<0.9>, INEA = 1. DALI 12 O/3S DAL IN is an external bus transceiver control line. DALI is driven by the MK5027 only while it is the BUS MASTER. DALI is asserted by the MK5027 when | ads from the DAL lines during the data portion of a READ transfer. DALI is not asserted during a WRITE transfer. DALO 13 O/3S DAL OUT is an external bus transceiver control line. DALO is driven by the MK5027 only while it is the BUS MASTER. DALO is asserted by the MK5027 when it drives the DAL lines during the address portion of a READ transfer or for the duration of a WRITE transfer. DAS 14 IO/3S DATA STROBE defines the data portio,n of a transaction. By definition, data is stable and valid at the low to high transition of DAS. This signal is driven by the MK5027 while it is the BUS MASTER. During the BUS SLAVE operation, this pin is used as an input. At all other times the signal is tristated. BMO BYTE BUSREL 15 IO/3S I/O pins 15 and 16 are programmable through CSR4. If bit 06 of CSR4 is set to a one, pin 15 becomes input BUSREL and is used by the host to signal the MK5027 to terminate a DMA burst after the current bus transfer has completed. If bit 06 is clear the pin 15 is an output and behaves as described below for pin 16. Note: Pin out shown is for 48 pin dip. 2/19 Descriplion MK5027 Table 1: Pin Description (continued) Signal Name BM1 BUSAKO Pin(s) 16 Type O/3S Descriplion Pins 15 and 16 are programmable though bit 00 of CSR4 (BCON). If CSR4<00> BCON = 0, I/O PIN 15 = BMO (O/3S) I/O PIN 16 = BM1 (O/3S) BYTE MASK<1:0> indicates the byte(s) on the DAL to be read or written during this bus transaction. MK5027 drives these lines only as a Bus Master. MK5027 ignores the BM lines when it is a Bus Slave. Byte selection is done as outlined in the following table. BM1 BM0 TYPE OF TRANSFER LOW LOW ENTIRE WORD LOW HIGH UPPER BYTE (DAL<15:08>) HIGH LOW LOWER BYTE (DAL<07:00>) HIGH HIGH NONE If CSR4<00>BCON = 1, I/O PIN 15 = BYTE (O/3S) I/O PIN 16 = BUSAKO(O) Byte selection is done using the BYTE line and DAL<00> latched during the address portion of the bus transaction. MK5027 drives BYTE only a Bus Master and ignores it when a Bus Slave. Byte selection is done as outlined in the following table. HOLD BUSRQ 17 IO/OD ALE AS 18 O/3S HLDA 19 I BYTE DAL<00> TYPE OF TRANSFER LOW LOW HIGH HIGH LOW HIGH LOW HIGH ENTIRE WORD ILLEGAL CONDITION LOWER BYTE UPPER BYTE BUSAKO is a bus request daisy chain output. If MK5027 is not requesting the bus and it receives HLDA, BUSAKO will be driven low. If MK5027 is requesting the bus when it receives HLDA, BUSAKO will remain high. Note: All transfers are entire word unless the MK5027 is configured for 8 bit operation. Pins 17 is configured through bit 0 of CSR4. If CSR4<00> BCON = 0, I/O PIN 17 = HOLD HOLD request is asserted by MK5027 when it requires a DMA cycle, if HLDA is inactive, regardless of the previous state of the HOLD pin. HOLD is held low for the entire ensuing bus transaction. If CSR4<00> BCON = 1, I/O PIN 17 = BUSRQ BUSRQ is asserted by MK5027 when it requires a DMA cycle if the prior state of the BUSRQ pin was high and HLDA is inactive. BUSRQ is held low for the entire ensuing bus transaction. The active level of ADDRESS STROBE is programmable through CSR4. The address portion of a bus transfer occurs while this signal is at its asserted level. This signal is driven by MK5027 while it is the BUS MASTER. At all other times, the signal is tristated. If CSR4<01> ACON = 0, I/O PIN 18 = ALE ADDRESS LATCH ENABLE is used to demultiplex the DAL lines and define the address portion of the transfer and remains low during the data portion. If CSR4<01> ACON = 1, I/O PIN 18 = AS As AS, the signal pulses low during the address portion of the bus transfer. The low to high transition of AS can be used by a slave device to strobe the address into a register. AS is effectively the inversion of ALE. HOLD AKNOWLEDGE is the response to HOLD. When HLDA is low in response to MK5027’s assertion of HOLD, the MK5027 is the Bus Master. HLDA should be desasserted ONLY after HOLD has been released by the MK5027. 3/19 MK5027 Table 1: Pin Description (continued) Signal Name Pin(s) Type Descriplion CS 20 I CHIP SELECT indicates, when low, that the MK5027 is the slave device for the data transfer.CS must be valid througout the enture transaction. ADR 21 I ADDRESS selects the Register Address Port or the Register Data Port. It must be valid throughout the data portion of the transfer and is only used by the chip when CS is low. ADR LOW HIGH READY 22 IO/OD When the MK5027 is a Bus Master, READY is an asynchronous acknowledgement from the bus memory that memory will accept data in a WRITE cycle or that memory has put data on the DAL lines in a READ cycle. As a bus Slave, the MK5027 asserts READY when it has put data on the DAL lines during a READ cycle or is about to take data from the DAL lines during WRITE cycle. READY is a response to DAS and it will be released after DAS or CS is negated. RESET 23 I RESET is the Bus signal that will cause MK5027 to cease operation, clear its internal logic and enter an idle state with the Power Off bit of CSR0 set. TCLK 25 I TRANSMIT CLOCK. A 1x clock input for transmitter timing. TD changes on the falling edge of TCLK. The frequency of TCLK may not be greater than the frequency of SYSCLK. DTR RTS 26 IO DATA TERMINAL READY, REQUEST TO SEND. Modem control pin. Pin 26 is configurable through CSR5. This pin can be programmed to behave as output RTS or as programmable IO pin DTR. If configured as RTS, the MK5027 will assert this pin if it has data to send and throughout the transmission of a signal unit. RCLK 27 I RECEIVE CLOCK. A 1x clock input for receiver timing. RD is sampled on the rising edge of RCLK. The frequency of RCLK may not be greater than the frequency of SYSCLK. SYSCLK 28 I SYSTEM CLOCK. System clock used for internal timing of the MK5027. SYSCLK should be a square wave, of frequency up to 10MHz. TD 29 O TRANSMIT DATA. Transmit serial data output. DSR CTS 30 IO DATA SET READY, CLEAR TO SEND. Modem Control Pin. Pin 30 is configurable through CSR5. This pin can be programmed to behave as input CTS or as programmable IO pin DSR. If configured as CTS, the MK5027 will transmit all ones while CTS is high. RD 31 I A<23:16> 32-39 O/3S VSS-GND 1, 24 VCC 48 4/19 PORT REGISTER DATA PORT REGISTER ADDRESS PORT RECEIVE DATA. Received serial data input. Address bits <23:16> used in conjunction with DAL <15:00> to produce a 24 bit address. MK5027 drives these lines only as a Bus Master. A23-A20 may be driven continuously as described in the CSR4<7> BAEN bit. Ground Pins Power Supply Pin +5.0 VDC ± 5% MK5027 Figure 2: Possible System Configuration for the MK5027. 5/19 MK5027 INTR DSR, CTS ADR DTR, RTS CS BM0 BM1 ALE, AS HOLD HLDA DALO DALI A <23:16> DAL <15:00> Figure 3: MK5027 Simplified Block Diagram. READY READ DAS FIRMWARE ROM CONTROL / STATUS REGISTERS 0 - 5 DMA CONTROLLER MICRO CONTROLLER TIMERS SYSCLK INTERNAL BUS RECEIVER TRANSMITTER FIFO FIFO VCC VSS - GND RESET RCLK RECEIVER TRANSMITTER RD TCLK TD LOOPBACK TEST OPERATIONAL DECRIPTION The SGS-THOMSON Signalling System #7 Signalling Link Controller (MK5027) device is a VLSI product intended for data communication applications requiring SS7 link level control. The MK5027 will perform all frame formatting, such as: frame delimiting with flags, FCS generation and detection. It will also perform all error recovery and link control. The MK5027 also includes a buffer management mechanism that allow the user to transmit and/or receive multiple MSU’s. Contained in the buffer management is an on-chip dual chan6/19 nel DMA: one channel for receive and one channel for transmit. The MK5027 handles error recovery and link status signalling. The MK5027 is intended to be used with any popular 16 or 8 bit microprocessor. Possible system configuration for the MK5027 is shown in Figure 2. The MK5027 will move multiple blocks of receive and transmit data directly into and out of memory through the host’s bus. An I/O acceleration processor in Figure 2 is recommended, but not required. MK5027 All signal pins on the MK5027 are TTL compatible. This has the advantage of making the MK5027 in- dependent of the physical interface. As shown in Figure 2. Iine drivers and receivers are used for electrical- connection to the physical layer. SERIAL INTERFACE The MK5027 provides two separate serial channels: one for received data and one for transmitted data. These serial channels are completely separate and may be run at different clock frequencies The receiver is responsible for recognizing frame boundries. removal of inserted zeroes (for transparency) and checking the incoming FCS. Signal units with in correct FCS values are discarded. The receiver also parallelizes the incoming data which is placed into the receive data buffers within the receive descriptor ring The transmitter is responsible for framing and serializing the data frames placed in the transmit descriptor ring. The transmitter calculates the FCS of the outgoing data and appends it to the data The transmitter generates flag sequences for inter-signal unit fill, at least two flags are transmitted between adjacent signal units. The FCS calculations for both directions of serial data optionally follow either the 16 bit CRC CCITT or the 32-bit CRC 32 algorithms FCS generation and checking can also be optionally disabled if necessary. MICROPROCESSOR INTERFACE The MK5027 contains a dual channel DMA on chip to handle data transfers to and from the host mem- ory. All access to the initialization block and descriptor rings is handled in this way The address bus is 24 bits wide and does not use any segmentation or paging methods. Data transfers can optionally be 8 and 16 bit operations. this allows easy interfacing with both 8 and 16 bit processors DMA transfers can be up to 1. 8 or an unlimited number of words per transfer under program control During bus slave operation the MK5027 allows access to its 6 control/status registers which are used to monitor and control the chip. These registers are used to control link procedures, configure interface options, control and monitor interrupt status. and more. Bus slave mode also allows both 8 and 16 bit accesses. BUFFER MANAGEMENT The basic organization of the buffer management is a circular queue of tasks in memory called descriptor rings. There are separate rings to describe the transmit and receive operations. Up to 128 buffers may be queued-up on a descriptor ring awaiting execution by the MK5027 The descriptor ring has a segment assigned to each buffer. Each segment holds a pointer for the starting address of the buffer. and holds a value for the length of the buffer in bytes. Each segment also contains two control bits called OWNA and OWNB, which denote whether the MK5027. the HOST. or the l/O ACCELERATION PROCESSOR (if present) ”owns” the buffer. For transmit. when the MK5027 owns the buffer. the MK5027 is allowed and commanded to transmit the buffer When the MK5027 does not own the buffer, it will not transmit that buffer. For receive. when the MK5027 owns a buffer. it may place received data into that buffer. Conversely. when the MK5027 does not own a receive buffer, it will not place received data in that buffer. The MK5027 buffer management mechanism will handly signal units which are longer than the length of an individual buffer. This is done by a chaining method which utilizes multiple buffers. The MK5027 tests the next segment in the descriptor ring in a ”look ahead” manner. If the packet is too long for one buffer, the next bufferwill be used after filling the first buffer: that is, ”chained”. The MK5027 will then ”look ahead” to the next buffer, and chain that buffer if necessary, and so on The operational parameters for the buffer management are defined by the user in the initialization block The parameters defined include the basic mode of operation. the number of entries for the transmitter and receiver descriptor rings. etc. 7/19 MK5027 Figure 4: MK5027 Buffer Management. RECEIVE BUFFER CSR 2, CSR3 POINTER TO INITIALIZATI ON BLOCK RECEI VER DESCRIPTOR RINGS BUFFER 0 DESCRIPTOR 0 BUFFER STATUS BUFFE R ADDRESS BUFFER SIZE BUFFER 1 BUFFER MSG COUNT DESCRIPTOR 1 INITIALIZATI ON BLOCK BUFFER M MODE FRAME ADDRESS FIELDS DESCRIPTOR M TIMER VALUES RX DESCRIPTOR POINTER TX DESCRIPTOR POINTER TRANS MIT DESCRIPTOR RINGS DESCRIPTOR 0 BUFFER STAT US TRANSMIT BUFFER BUFFER 0 XID/TEST TRANSMIT DESCRIPTOR POINTER XID/TES T RECEIVE BUFFER ADDRESS BUFFER SIZE DESCRI PTOR POINTER STAT US BUFFER ADDRESS BUFFER MSG COUNT BUFFER 1 DESCRIPTOR 1 ERROR COUNTERS STATUS BUFFER BUFFER N XID/TEST RECEIVE BUFFER XID/T EST TRANSMIT BUFFER 8/19 DESCRIPTOR N MK5027 SIGNALLING UNIT REPERTOIRE The signal unit repertoire of the MK5027 is shown in Table 1. This set conforms to the 1988 CCITT specification for level 2 of Signalling System #7. The definitions for the symbols for the frame types are: Name F FSN BSN FIB BIB LI X SIO SIF SF FCS Definition Flag Sequence Forward Sequence Number Backward Sequences Number Forward Indicator Bit Backward Indicator Bit Lenght Indicator Programmed As Zeroes Signalling Information Octet Service Information Field Satus Field Frame Check Sequence Table 1: MK5027 Signal Unit Repertoire. 9/19 MK5027 MK5027 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Temperature under Bias –25°C to +100°C Storage Temperature –65°C to +150°C Voltage on Any Pin with Respect to Ground –0.5V to VCC +0.5V Power Dissipation 0.50W Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the above device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affectdevice reliability. DC CHARACTERISTICS TA=0 °C to 70 °C, VCC = +5V ±5 percent unless otherwise specified. Symbol Parameter Min. VIL VIH VOL @ IOL = 3.2 mA VOH @ IOH= -0.4 mA IIL @ VIN = 0.4 to VCC ICC @ TSCT = 100 ns Max. Units -0.5 Typ. +0.8 V +2.0 VCC +0.5 V +0.5 V +10 mA +2.4 V µA 50 CAPACITANCE f = 1MHz Symbol CIN COUT C IO Max. Units Capacitance on Input pins Parameter Min. Typ. 10 pF Capacitance on Output Pins 10 pF Capacitance on I/O pins 20 pF AC TIMING SPECIFICATIONS TA = 0 °C to 70 °C, VCC = +5V ±5 percent, unless otherwise specified. Signal Symbol 1 SYSCLK TSCT SYSCLK period 100 2 SYSCLK TSCL SYSCLK low time 45 3 SYSCLK TSCH SYSCLK high time 45 4 SYSCLK TSCR Rise time of SYSCLK 0 8 ns 5 SYSCLK TSCF Fall time of SYSCLK 0 8 ns 6 TCLK TTCT TCLK period 140 ns 7 TCLK TTCL TCLK low time 63 ns 8 TCLK TTCH TCLK high time 63 9 TCLK TTCR Rise time of TCLK 10 TCLK TTCF Fall time of TCLK 11 TD TTDP TD data propagation delay after the falling edge of TCLK 12 TD TTDH TD data hold time after the falling edge of TCLK 10/19 Parameter Test Condition No CL = 50 pF Min. 0 0 CL = 50 pF 5 Typ. Max. Units 20000 ns ns ns ns 8 ns 8 ns 40 ns ns MK5027 AC TIMING SPECIFICATIONS (Continued) TA = 0 °C to 70 °C, VCC = +5V ±5 percent, unless otherwise specified. No Signal Symbol Parameter Test Conditions Min. Typ. Max. Units 13 RCLK TRCT RCLK period 140 14 RCLK TRCH RCLK high time 63 ns 15 RCLK TRCL RCLK low time 63 ns 16 RCLK TRCR Rise time of RCLK 0 8 17 RCLK TRCF Fall time of RCLK 0 8 ns 18 RD TRDR RD data rise time 0 8 ns 19 RD TRDF RD data fall time 0 8 20 RD TRDH RD hold time after rising edge of RCLK 5 ns 21 RD TRDS RD setup time prior to rising edge of RCLK 30 ns 22 A/DAL TDOFF Bus Master driver disable after rising edge of HOLD 0 50 ns 23 A/DAL TDON Bus Master driver enable after falling edge of HLDA 0 200 ns 24 HLDA THHA Delay to falling edge of HLDA from falling edge of HOLD (Bus Master) RESET pulse width 25 RESET TRW 26 A/DAL TCYCLE 27 A TXAS 28 A 29 TSCT = 100ns ns ns ns 0 ns 30 ns 600 ns Address setup time to falling edge of ALE 100 ns TXAH Address hold time after the rising edge of DAS 50 ns DAL TAS Address setup time to falling edge of ALE 75 ns 30 DAL TAH Address hold time after the falling edge of ALE 20 ns 31 DAL TRDAS Data setup time to the falling edge of DAS (Bus Master read) 55 ns 32 DAL TRDAH Data hold time after the rising edge of DAS (bus master read) 0 ns 33 DAL TDDAS Data setup time to the falling edge of DAS (bus master write) 0 ns 34 DAL TWDS Data setup time to the rising edge of DAS (bus master write) 250 ns 35 DAL TWDH Data hold time to the rising edge of DAS (bus slave write) 35 ns 36 DAL TSRDH Data hold time after the rising edge of DAS (bus slave read) 37 DAL TSWDH Data hold time after the rising edge of DAS (bus slave write) 0 ns 38 DAL TSWDS Data setup time to the falling edge of DAS (bus slave write) 0 ns Read/write, address/data Cycle Time TSCT = 100ns TSCT = 100ns 0 35 ns 39 ALE TALEW ALE width high 110 ns 40 ALE TDSW Delay from rising edge od DAS to the rising edge of ALE 70 ns 41 DAS TDSW DAS width low 200 ns 11/19 MK5027 AC TIMING SPECIFICATIONS (Continued) TA = 0 °C to 70 °C, VCC = +5V ±5 percent, unless otherwise specified. Test Conditions No Signal Symbol Parameter 42 DAS TADAS Delay from the falling edge of ALE to the falling edge of DAS 80 ns 43 DAS TRIDF Delay from the rising edge of DALO to the falling edge of DAS (bus master read) 35 ns 44 DAS TRDYS Delay from the falling edge of READY to the falling edge of DAS 45 DALI TROIF Delay from the rising edge of DALO to the falling edge of DALI (bus master read) 70 ns 46 DALI TRIS DALI setup time to the rising edge of DAS (bus master read) 150 ns 47 DALI TRIH DALI hold time after the rising edge of DAS (bus master read) 0 ns 48 DALI TRIOF Delay from the rising edge of DALI to the falling edge of DALO (bus master read) 70 ns 49 DALO TOS DALO setup time to the falling edge of ALE (bus master read) 110 ns 50 DALO TROH DALO hold time after the falling edge of ALE (bus master read) 35 ns 51 DALO TWDSI Delay from the rising edge of DAS to the rising edge of DALO (bus master write) 50 ns 52 CS TCSH CS hold time after the rising edge of DAS (bus slave) 0 ns 53 CS TCSS CS setup time to the falling edge of DAS (bus slave) 0 ns 54 ADR TSAH ADR hold time after the rising edge of DAS (bus slave) 0 ns 55 ADR TSAS ADR setup time to the falling edge of DAS (bus slave) 0 ns 56 READY TARYD Delay from the falling edge of ALE to the falling edge of READY to Insure a Minimum Bus Cycle Time (600ns) 57 READY TSRDS Data setup time to the falling edge of READY (bus slave read) 75 ns 58 READY TRDYH READY hold time after the rising edge of DAS (bus master) 0 ns 59 READY TSRYH READY hold time after the rising edge of DAS (bus slave) 60 READY TRSH READ hold time after rhe rising edge of DAS (bus slave) 0 ns 61 READ TSRS READ setup time after rhe rising edge of DAS (bus slave) 0 ns 62 READY TRDYD Delay from falling edge of DAS to falling edge of READY (bus slave) 12/19 TARYD = 300ns TSCT = 100ns Min. Typ. 120 200 TSCT = 100ns TSCT = 100ns TSCT = 100ns Max. 150 0 35 200 Units ns ns ns ns MK5027 Figure 5A: TTL Output Load Diagram. Figure 5B: Open Drain Output Load Diagram. TEST POINT Vcc Vcc R1 = 1.2K FROM OUTPUT UNDER TEST R1 = 1.4K FROM OUTPUT UNDER TEST CR1 - CR4 = 1N914 or EQUIV CR 1 C CR 0.4 mA 2 L C CR 3 L C L = 50pF min @ 1 MHz CR 4 NOTE: This load is used on open NOTE: This load is used on all outputs except INTR, HOLD, READY. drain outputs INTR, HOLD, READY. Figure 6: MK5027 Serial Link Timing Diagram 13 14 15 RCLK 16 21 19 17 20 RD 18 6 8 7 TCLK 10 9 11 12 TD TIMING MEASUREMENTS ARE MADE AT THE FOLLOWING VOLTAGES, UNLESS OTHERWISE SPECIFIED: ”1” ”0” OUTPUT 2.0 V O.8 V INPUT 2.0 V O.8 V FLOAT 10 % 90 % 13/19 MK5027 Figure 7: MK5027 Bus Master Timing Diagram (read). Note: The Bus Master cycle time will increase from a minimum of 600ns in 100ns steps until the slave device return READY. 14/19 MK5027 Figure 8: MK5027 Bus Master Timing Diagram (write). Note: The Bus Master cycle time will increase from a minimum of 600ns in 100ns steps until the slave device return READY. 15/19 MK5027 Figure 9: MK5027 Bus Slave Timing Diagram (read) Figure 10: MK5027 Bus Slave Timing Diagram (write) 16/19 MK5027 DIP48 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. a1 0.63 0.025 b 0.45 0.018 b1 0.23 b2 0.31 1.27 D E 0.009 0.012 0.050 62.74 15.2 16.68 2.470 0.598 0.657 e 2.54 0.100 e3 58.42 2.300 F MAX. 14.1 0.555 I 4.445 0.175 L 3.3 0.130 17/19 MK5027 PLCC52 PACKAGE MECHANICAL DATA mm TYP. MAX. A 4.20 5.08 A1 0.51 A3 2.29 3.30 0.090 0.13 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 DIM. C MIN. inch TYP. MAX. 0.165 0.20 0.020 0.25 0.01 D 19.94 20.19 0.785 0.795 D1 19.05 19.20 0.750 0.756 D2 17.53 18.54 0.690 0.730 D3 18/19 MIN. 15.24 0.60 E 19.94 20.19 0.785 0.795 E1 19.05 19.20 0.750 0.756 E2 17.53 18.54 0.690 0.730 E3 15.24 0.60 e 1.27 0.05 L 0.64 0.025 L1 1.53 0.060 M 1.07 1.22 0.042 0.048 M1 1.07 1.42 0.042 0.056 MK5027 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1996 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Swit zerland - Taiwan - Thailand - United Kingdom - U.S.A. 19/19