M2201 2-Wires 1 Kbit (x8) Serial EEPROM TWO WIRE SERIAL INTERFACE 100.000 ERASE/WRITE CYCLES with 100 YEARS DATA RETENTION at 55°C SINGLE SUPPLY VOLTAGE: – 4.5V to 5.5V for M2201 version – 2.7V to 5.5V for M2201V version HARDWARE WRITE CONTROL 100 KBIT TRANSFER RATE BYTE WRITE PAGE WRITE (up to 4 BYTES) SELF TIMED PROGRAMMING CYCLE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD/LATCH UP 8 8 1 1 PSDIP8 (B) 0.25mm Frame SO8 (M) 150mil Width 8 DESCRIPTION The M2201 is a simplified 2-wire bus 1 Kbit electrically erasable programmable memory (EEPROM), organized as 128 x8 bits. It is manufactured in STMicroelectronics’s Hi-Endurance Advanced CMOS technology which guarantees a data retention of 100 years at 55°C. The M2201 is available in Plastic Dual-in-Line, Plastic Small Outline and Thin Shrink Small Outline packages. The memory is compatible with a two wire serial interface which uses a bi-directional data bus and serial clock. Read and write operations are initiated by a START condition generated by the bus master and ended by a STOP condition. Address bits and RW bit are defined in one single byte, instead of two (or three) bytes for the standard I2C protocol. 1 TSSOP8 (DW) 169 mil width Figure 1. Logic Diagram VCC SCL WC SDA M2201 Table 1. Signal Names SDA Serial Data Input/Output SCL Serial Clock WC Write Control VCC Supply Voltage VSS Ground July 1999 VSS AI01321 1/15 M2201 Figure 2A. DIP Pin Connections Figure 2B. SO and TSSOP Pin Connections M2201 NC NC NC VSS M2201 8 7 6 5 1 2 3 4 VCC WC SCL SDA NC NC NC VSS AI01322 8 7 6 5 1 2 3 4 VCC WC SCL SDA AI01323 Warning: NC = Not Connected. Warning: NC = Not Connected. Table 2. Absolute Maximum Ratings (1) Symbol Parameter Value Unit Ambient Operating Temperature –40 to 85 °C TSTG Storage Temperature –65 to 150 °C TLEAD Lead Temperature, Soldering 215 260 t.b.c. °C TA (SO8 package) (PSDIP8 package) (TSSOP8 package) 40 sec 10 sec t.b.c. VO Output Voltage –0.6 to 6.5 V VI Input Voltage –0.6 to 6.5 V –0.3 to 6.5 V VCC VESD Supply Voltage Electrostatic Discharge Voltage (Human Body model) Electrostatic Discharge Voltage (Machine model) (3) (2) 4000 V 500 V Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω). 3. EIAJ IC-121 (Condition C) (200pF, 0 Ω). DESCRIPTION (cont’d) When writing data to the memory, it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condition. Power On Reset: VCC lock out write protect. In order to prevent data corruption and inadvertent 2/15 write operations during power up, a Power On Reset (POR) circuit is implemented. Until the VCC voltage has reached the POR threshold value, the internal reset is active, all operations are disabled and the device will not respond to any command. In the same way, when VCC drops down from the operating voltage to below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable VCC must be applied before applying any logic signal. M2201 SIGNAL DESCRIPTIONS Serial Clock (SCL). The SCL input pin is used to synchronize all data in and out of the memory. A resistor can be connected from the SCL line to VCC to act as a pull up (see Figure 3). Serial Data (SDA). The SDA pin is bi-directional and is used to transfer data in or out of the memory. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A resistor must be connected from the SDA bus line to VCC to act as pull up (see Figure 3). Write Control (WC). An hardware Write Control feature (WC) is offered on pin 7. This feature is usefull to protect the contents of the memory from any erroneous erase/write cycle. The Write Control signal is used to enable (WC = VIH) or disable (WC = VIL) the internal write protection. When unconnected, the WC input is internally read as VIL (WC is disabled). DEVICE OPERATION The device that controls the data transfer is known as the master. The master will always initiate a data transfer and will provide the serial clock for synchronisation. The M2201 is always a slave device in all communications. Start Condition. START is identified by a high to low transition of the SDA line while the clock SCL is stable in the high state. A START condition must precede any command for data transfer. Except during a programming cycle, the M2201 continuously monitor the SDA and SCL signals for a START condition and will not respond unless one is given. Stop Condition. STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the M2201 and the bus master. A STOP condition at the end of a Read command forces the standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle. Acknowledge Bit (ACK). An acknowledge signal is used to indicate a successfull data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse period the receiver pulls the SDA bus low to acknowledge the receipt of the 8 bits of data. Data Input. During data input the M2201 sample the SDA bus signal on the rising edge of the clock SCL. Note that for correct device operation the SDA signal must be stable during the clock low to high transition and the data must change ONLY when the SCL line is low. Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) 20 VCC 16 RL max (kΩ) RL 12 RL SDA MASTER CBUS SCL 8 CBUS 4 VCC = 5V 0 100 200 CBUS (pF) 300 400 AI01100 3/15 M2201 Table 3. Input Parameters (TA = 25 °C, f = 100 kHz ) Symbol Parameter Test Condition Min Max Unit CIN Input Capacitance (SDA) 8 pF CIN Input Capacitance (other pins) 6 pF 20 kΩ ZWCL (1) WC Input Impedance VIN ≤ 0.3 VCC 5 ZWCH (1) WC Input Impedance VIN ≥ 0.7 VCC 500 tLP (1) Low-pass filter input time constant (SDA and SCL) kΩ 100 ns Max Unit Note: 1. The results come from simulation, actual results may vary. These figures are not guaranteed. Table 4. DC Characteristics (TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.7V to 5.5V) Symbol Parameter Test Condition ILI Input Leakage Current (SCL, SDA) 0V ≤ VIN ≤ VCC ±2 µA ILO Output Leakage Current 0V ≤ VOUT ≤ VCC SDA in Hi-Z ±2 µA Supply Current (M2201) VCC = 5V; fC = 100kHz (Rise/Fall time < 30ns) 2 mA VCC = 2.7V; fC = 100kHz 1 mA VIN = VSS or VCC, VCC = 5V 100 µA VIN = VSS or VCC, VCC = 5V, fC = 100kHz 300 µA VIN = VSS or VCC, VCC = 2.7V 5 µA VIN = VSS or VCC, VCC = 2.7V; fC = 100kHz 50 µA ICC Supply Current (M2201V) ICC1 ICC2 Supply Current (Standby) (M2201) Supply Current (Standby) (M2201V) VIL Input Low Voltage (SCL, SDA) –0.3 0.3 VCC V VIH Input High Voltage (SCL, SDA) 0.7 VCC VCC + 1 V VIL Input Low Voltage (WC) –0.3 0.5 V VIH Input High Voltage (WC) VCC – 0.5 VCC + 1 V IOL = 3mA, VCC = 5V 0.4 V IOL = 2mA, VCC = 2.7V 0.4 V VOL Output Low Voltage (M2201) Output Low Voltage (M2201V) 4/15 Min M2201 Table 5. AC Characteristics (TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.7V to 5.5V) Symbol Alt tCH1CH2 tR tCL1CL2 Parameter Min Max Unit Clock Rise Time 1 µs tF Clock Fall Time 300 ns tDH1DH2 tR Input Rise Time 1 µs tDL1DL1 tF Input Fall Time 300 ns tCHDX (1) tSU:STA tCHCL tHIGH tDLCL 4.7 µs Clock Pulse Width High 4 µs tHD:STA Input Low to Clock Low (START) 4 µs tCLDX tHD:DAT Clock Low to Input Transition 0 µs tCLCH tLOW Clock Pulse Width Low 4.7 µs tDXCX tSU:DAT Input Transition to Clock Transition 250 ns tCHDH tSU:STO Clock High to Input High (STOP) 4.7 µs tDHDL tBUF Input High to Input Low (Bus Free) 4.7 µs tAA Clock Low to Next Data Out Valid 0.3 tCLQX tDH Data Out Hold Time 300 fC fSCL Clock Frequency 100 kHz tW tWR Write Time 10 ms tCLQV (2) Clock High to Input Transition 3.5 µs ns Notes: 1. For a reSTART condition, or following a write cycle. 2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP conditions. Table 6. AC Measurement Conditions Input Rise and Fall Times ≤ 50ns Input Pulse Voltages 0.2VCC to 0.8VCC Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC Figure 4. AC Testing Input Output Waveforms 0.8VCC 0.2VCC 0.7VCC 0.3VCC AI00825 Memory Addressing. To start communication between the bus master and the slave M2201, the master must initiate a START condition. Following this, the master sends onto the SDA bus line 8 bits (MSB first) corresponding to the 7th bit byte-address and a READ or WRITE bit. This 8th bit is set to ’1’ for read and ’0’ for write operations. If a match is found, the corresponding memory will acknowledge the identification on the SDA bus during the 9th bit time. Write Operations Following a START condition the master sends the byte address with the RW bit reset to ’0’. The memory acknowledges this and waits for a data byte. Any write command with WC = 1 (during a period of time from the START condition until the end of the Byte Address) will not modify data and will NOT be acknowledged on data bytes, as in Figure 8. 5/15 M2201 Figure 5. AC Waveforms tCHCL tCLCH SCL tDLCL tDXCX tCHDH SDA IN tCHDX START CONDITION tCLDX tDHDL SDA INPUT SDA CHANGE STOP & BUS FREE SCL tCLQV tCLQX DATA VALID SDA OUT DATA OUTPUT SCL tW SDA IN tCHDH STOP CONDITION tCHDX WRITE CYCLE START CONDITION AI00795B 6/15 M2201 Byte Write. In the Byte Write mode the master sends one data byte, which is acknowledged by the memory. The master then terminates the transfer by generating a STOP condition. Page Write. The Page Write mode allows up to 4 bytes to be written in a single write cycle, provided that they are all located in the same ’row’ in the memory: that is the 5 most significant memory address bits (A6-A2) are the same. The master sends from one up to four bytes of data, which are each acknowledged by the memory. After each byte is transfered, the internal byte address counter (2 least significant bits only) is incremented. The transfer is terminated by the master generating a STOP condition. Care must be taken to avoid ad- dress counter ’roll-over’ which could result in data being overwritten. It must be noticed that, for any write mode, the generation by the master of the STOP condition starts the internal memory program cycle. All inputs are disabled until the completion of this cycle and the memory will not respond to any request. Minimizing System Delays by Polling On ACK. During the internal write cycle, the memory disconnects itself from the bus in order to copy the data from the internal latches to the memory cells. The maximum value of the write time (tW) is given in the AC Characteristics table, since the typical time is shorter, the time seen by the system may be re- Figure 6. I2C Bus Protocol SCL SDA START CONDITION SCL 1 SDA MSB SDA INPUT 2 SDA CHANGE STOP CONDITION 3 7 8 9 ACK START CONDITION SCL 1 SDA MSB 2 3 7 8 9 ACK STOP CONDITION AI00792 7/15 M2201 DEVICE OPERATION (cont’d) duced by an ACK polling sequence issued by the master. The sequence is as follows: – Initial condition: a Write is in progress (see Figure 7). – Step 1: the Master issues a START condition followed by a Device Select byte (1st byte of the new instruction). – Step 2: if the memory is busy with the internal write cycle, no ACK will be returned and the master goes back to Step 1. If the memory has terminated the internal write cycle, it will respond with an ACK, indicating that the memory is ready to receive the second part of the next instruction (the first byte of this instruction was already sent during Step 1). Figure 7. Write Cycle Polling using ACK WRITE Cycle in Progress START Condition Byte Address with RW = 0 NO ACK Returned YES NO Next Operation is WRITE YES ReSTART Send DATA BYTE STOP STOP AI01049 8/15 M2201 Read Operation Byte Read. The master sends a START condition followed by seven bits of address and the RW bit (set to ’1’). The M2201 acknowledges it and outputs the corresponding data byte. The read operation is terminated by a STOP condition issued by the master (instead of the ACK bit). Sequential Read. The master sends a START condition followed by seven bits of address and the RW bit (set to ’1’). The M2201 acknowledges it and outputs the corresponding data byte. The master does acknowledge this byte and reads the next data byte (at address + 1). The read operation is terminated by a STOP condition issued by the master (instead of the ACK bit). The output data is from consecutive byte addresses, with the internal byte address counter automatically incremented after each byte output. After a count of the last memory address, the address counter will ’rollover to address ’00’ and the memory will continue to output data. Acknowledge in Read Mode. In all read modes the M2201 waits for an acknowledge during the 9th bit time. If the master does not pull the SDA line low during this time, the M2201 terminates the data transfer and switches to a standby state. Figure 8. Write Modes Sequences with Write Control = 1 (M2201 and M2201V) WC ACK DATA IN STOP BYTE ADDR START BYTE WRITE NO ACK R/W = 0 WC BYTE ADDR START PAGE WRITE R/W = 0 NO ACK DATA IN 1 NO ACK NO ACK DATA IN 4 STOP ACK AI01324 9/15 M2201 Figure 9. Write Modes Sequences (M2201 and M2201V) ACK Data-In STOP Byte-Address START BYTE WRITE ACK R/W=0 ACK ACK Byte-Address START PAGE WRITE Data-In1 ACK Data-In 2 Data-In 3 R/W=0 ACK ACK STOP Data-In N AI03128 Figure 10. Read Modes Sequences ACK DATA OUT START BYTE ADDR ACK DATA OUT 1 R/W = 1 ACK NO ACK DATA OUT N STOP R/W = 1 ACK SEQUENTIAL READ STOP BYTE ADDR START BYTE READ NO ACK AI01325 10/15 M2201 ORDERING INFORMATION SCHEME Example: M2201 Operating Voltage blank 4.5V to 5.5V V V M Package B PSDIP8 0.25mm Frame M SO8 150mil Width 2.7V to 5.5V DW 1 TR Temperature Range 1 0 to 70 °C 6 –40 to 85 °C Option TR Tape & Reel Packing TSSOP8 169mil width Devices are shipped from the factory with the memory content set at all "1’s" (FFh). For a list of available options (Operating Voltage, Package, etc...) or for further information please contact the STMicroelectronics Sales Office nearest to you. 11/15 M2201 PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame mm Symb Typ inches Min Max A 3.90 A1 Min Max 5.90 0.154 0.232 0.49 – 0.019 – A2 3.30 5.30 0.130 0.209 B 0.36 0.56 0.014 0.022 B1 1.15 1.65 0.045 0.065 C 0.20 0.36 0.008 0.014 D 9.20 9.90 0.362 0.390 – – – – 6.00 6.70 0.236 0.264 – – – – 7.80 – 0.307 – E 7.62 E1 e1 2.54 eA eB Typ 0.300 0.100 10.00 L 3.00 N 8 3.80 0.118 8 A2 A1 B 0.394 A L e1 eA eB B1 D C N E1 E 1 PSDIP-a Drawing is not to scale. 12/15 0.150 M2201 SO8 - 8 lead Plastic Small Outline, 150 mils body width mm Symb Typ inches Min Max A 1.35 A1 Min Max 1.75 0.053 0.069 0.10 0.25 0.004 0.010 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.00 0.150 0.157 – – – – H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 0.90 0.016 0.035 α 0° 8° 0° 8° N 8 e 1.27 Typ 0.050 8 CP 0.10 0.004 h x 45˚ A C B CP e D N E H 1 A1 α L SO-a Drawing is not to scale. 13/15 M2201 TSSOP8 - 8 lead Plastic Thin Shrink Small Outline, 169 mils body width mm Symb Typ inches Min Max A Typ Min Max 1.10 0.043 A1 0.05 0.15 0.002 0.006 A2 0.85 0.95 0.033 0.037 B 0.19 0.30 0.007 0.012 C 0.09 0.20 0.004 0.008 D 2.90 3.10 0.114 0.122 E 6.25 6.50 0.246 0.256 E1 4.30 4.50 0.169 0.177 – – – – L 0.50 0.70 0.020 0.028 α 0° 8° 0° 8° N 8 e 0.65 0.026 8 CP 0.08 0.003 D DIE N C E1 E N/2 1 α A1 A CP A2 B L e TSSOP Drawing is not to scale. 14/15 M2201 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 1999 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 15/15