ST24C16, ST25C16 ST24W16, ST25W16 16 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection 1 MILLION ERASE/WRITE CYCLES, with 40 YEARS DATA RETENTION SINGLE SUPPLY VOLTAGE: – 4.5V to 5.5V for ST24x16 versions – 2.5V to 5.5V for ST25x16 versions HARDWARE WRITE CONTROL VERSIONS: ST24W16 and ST25W16 TWO WIRE SERIAL INTERFACE, FULLY I2C BUS COMPATIBLE BYTE and MULTIBYTE WRITE (up to 8 BYTES) for the ST24C16 PAGE WRITE (up to 16 BYTES) BYTE, RANDOM and SEQUENTIAL READ MODES SELF TIMED PROGRAMING CYCLE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD/LATCH UP PERFORMANCES DESCRIPTION This specification covers a range of 16 Kbit I2C bus EEPROM products, the ST24/25C16 and the ST24/25W16. In the text, products are referred to as ST24/25x16 where "x" is: "C" for Standard version and "W" for hardware Write Control version. The ST24/25x16 are 16 Kbit electrically erasable programmable memories (EEPROM), organized as 8 blocks of 256 x8 bits. These are manufactured in STMicroelectronics’s Hi-Endurance Advanced CMOS technology which guarantees an endurTable 1. Signal Names PRE Write Protect Enable PB0, PB1 Protect Block Select SDA Serial Data Address Input/Output SCL Serial Clock MODE Multybyte/Page Write Mode (C version) WC Write Control (W version) VCC Supply Voltage VSS Ground February 1999 8 8 1 1 PSDIP8 (B) 0.25mm Frame SO8 (M) 150mil Width Figure 1. Logic Diagram VCC 2 PB0-PB1 PRE SCL SDA ST24x16 ST25x16 MODE/WC* VSS AI00866B Note: WC signal is only available for ST24/25W16 products. 1/17 ST24/25C16, ST24/25W16 Figure 2A. DIP Pin Connections Figure 2B. SO8 Pin Connections ST24x16 ST25x16 PRE PB0 PB1 VSS 1 2 3 4 8 7 6 5 ST24x16 ST25x16 VCC MODE/WC SCL SDA PRE PB0 PB1 VSS AI00867B 1 2 3 4 8 7 6 5 VCC MODE/WC SCL SDA AI00500B Table 2. Absolute Maximum Ratings (1) Symbol Value Unit Ambient Operating Temperature –40 to 125 °C TSTG Storage Temperature –65 to 150 °C TLEAD Lead Temperature, Soldering 215 260 °C TA Parameter (SO8) (PSDIP8) 40 sec 10 sec VIO Input or Output Voltages –0.6 to 6.5 V VCC Supply Voltage –0.3 to 6.5 V VESD Electrostatic Discharge Voltage (Human Body model) (2) 4000 V Electrostatic Discharge Voltage (Machine model) (3) 500 V Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. 100pF through 1500Ω; MIL-STD-883C, 3015.7 3. 200pF through 0Ω; EIAJ IC-121 (condition C) DESCRIPTION (cont’d) ance of one million erase/write cycles with a data retention of 40 years. The ST25x16 operates with a power supply value as low as 2.5V. Both Plastic Dual-in-Line and Plastic Small Outline packages are available. The memories are compatible with the I2C standard, two wire serial interface which uses a bi-directional data bus and serial clock. The memories 2/17 carry a built-in 4 bit, unique device identification code (1010) corresponding to the I2C bus definition. The memories behave as slave devices in the I2C protocol with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition generated by the bus master. The START condition is followed by a stream of 4 bits (identification code 1010), 3 block select bits, plus one read/write bit and terminated by an acknowledge bit. When writing data to the ST24/25C16, ST24/25W16 Table 3. Device Select Code Device Code Memory MSB Addresses RW Bit b7 b6 b5 b4 b3 b2 b1 b0 Device Select 1 0 1 0 A10 A9 A8 RW Note: The MSB b7 is sent first. Table 4. Operating Modes Mode Current Address Read Random Address Read RW bit MODE pin Bytes ’1’ X 1 X 1 ’0’ ’1’ Initial Sequence START, Device Select, RW = ’1’ START, Device Select, RW = ’0’, Address, reSTART, Device Select, RW = ’1’ Sequential Read ’1’ X 1 to 2048 As CURRENT or RANDOM Mode Byte Write ’0’ X 1 START, Device Select, RW = ’0’ Multibyte Write ’0’ VIH 8 START, Device Select, RW = ’0’ Page Write ’0’ VIL 16 START, Device Select, RW = ’0’ Note: X = VIH or VIL. memory it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condition. Data in the 4 upper blocks of the memory may be write protected. The protected area is programmable to start on any 16 byte boundary. The block in which the protection starts is selected by the input pins PB0, PB1. Protection is enabled by setting a Protect Flag bit when the PRE input pin is driven High. Power On Reset: VCC lock out write protect. In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is implemented. Untill the VCC voltage has reached the POR threshold value, the internal reset is active: all operations are disabled and the device will not respond to any command. In the same way, when VCC drops down from the operating voltage to below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable VCC must be applied before applying any logic signal. 3/17 ST24/25C16, ST24/25W16 SIGNALS DESCRIPTION Serial Clock (SCL). The SCL input signal is used to synchronise all data in and out of the memory. A resistor can be connected from the SCL line to VCC to act as a pull up (see Figure 3). Serial Data (SDA). The SDA signal is bi-directional and is used to transfer data in or out of the memory. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A resistor must be connected from the SDA bus line to VCC to act as pull up (see Figure 3). Protected Block Select (PB0, PB1). PB0 and PB1 input signals select the block in the upper part of the memory where write protection starts. These inputs have a CMOS compatible input level. Protect Enable (PRE). The PRE input signal, in addition to the status of the Block Address Pointer bit (b2, location 7FFh as in Figure 7), sets the PRE write protection active. Mode (MODE). The MODE input is available on pin 7 (see also WC feature) and may be driven dynamically. It must be at VIL or VIH for the Byte Write mode, VIH for Multibyte Write mode or VIL for Page Write mode. When unconnected, the MODE input is internally read as VIH (Multibyte Write mode). Write Control (WC). An hardware Write Control feature is offered only for ST24W16 and ST25W16 versions on pin 7. This feature is usefull to protect the contents of the memory from any erroneous erase/write cycle. The Write Control signal is used to enable (WC at VIH) or disable (WC at VIL) the internal write protection. When unconnected, the WC input is internally read as VIL. The devices with this Write Control feature no longer supports the Multibyte Write mode of operation, however all other write modes are fully supported. Refer to the AN404 Application Note for more detailed information about Write Control feature. Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus 20 VCC 16 RL max (kΩ) RL 12 RL SDA MASTER CBUS SCL 8 CBUS 4 VCC = 5V 0 100 200 CBUS (pF) 4/17 300 400 AI01100 ST24/25C16, ST24/25W16 Table 5. Input Parameters (1) (TA = 25 °C, f = 100 kHz ) Symbol Parameter Test Condition Min Max Unit CIN Input Capacitance (SDA) 8 pF CIN Input Capacitance (other pins) 6 pF 20 kΩ ZWCL WC Input Impedance (ST24/25W16) VIN ≤ 0.3 VCC 5 ZWCH WC Input Impedance (ST24/25W16) VIN ≥ 0.7 VCC 500 tLP Low-pass filter input time constant (SDA and SCL) kΩ 100 ns Max Unit Note: 1. Sampled only, not 100% tested. Table 6. DC Characteristics (TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V) Symbol Parameter Test Condition ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2 µA ILO Output Leakage Current 0V ≤ VOUT ≤ VCC SDA in Hi-Z ±2 µA Supply Current (ST24 series) VCC = 5V, fC = 100kHz (Rise/Fall time < 10ns) 2 mA Supply Current (ST25 series) VCC = 2.5V, fC = 100kHz 1 mA VIN = VSS or VCC, VCC = 5V 100 µA VIN = VSS or VCC, VCC = 5V, fC = 100kHz 300 µA VIN = VSS or VCC, VCC = 2.5V 5 µA VIN = VSS or VCC, VCC = 2.5V, fC = 100kHz 50 µA ICC ICC1 ICC2 Supply Current (Standby) (ST24 series) Supply Current (Standby) (ST25 series) Min VIL Input Low Voltage (SCL, SDA) –0.3 0.3 VCC V VIH Input High Voltage (SCL, SDA) 0.7 VCC VCC + 1 V VIL Input Low Voltage (PB0 - PB1, PRE, MODE, WC) –0.3 0.5 V VIH Input High Voltage (PB0 - PB1, PRE, MODE, WC) VCC – 0.5 VCC + 1 V VOL Output Low Voltage (ST24 series) IOL = 3mA, VCC = 5V 0.4 V Output Low Voltage (ST25 series) IOL = 2.1mA, VCC = 2.5V 0.4 V 5/17 ST24/25C16, ST24/25W16 Table 7. AC Characteristics (TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V) Symbol Alt tCH1CH2 tR tCL1CL2 Max Unit Clock Rise Time 1 µs tF Clock Fall Time 300 ns tDH1DH2 tR Input Rise Time 1 µs tDL1DL1 tF Input Fall Time 300 ns tCHDX (1) tSU:STA Parameter Min 4.7 µs Clock Pulse Width High 4 µs Clock High to Input Transition tCHCL tHIGH tDLCL tHD:STA Input Low to Clock Low (START) 4 µs tCLDX tHD:DAT Clock Low to Input Transition 0 µs tCLCH tLOW Clock Pulse Width Low 4.7 µs tDXCX tSU:DAT Input Transition to Clock Transition 250 ns tCHDH tSU:STO Clock High to Input High (STOP) 4.7 µs tDHDL tBUF Input High to Input Low (Bus Free) 4.7 µs tAA Clock Low to Next Data Out Valid 0.3 tCLQX tDH Data Out Hold Time 300 fC fSCL Clock Frequency 100 kHz tWR Write Time 10 ms tCLQV tW (2) (3) 3.5 µs ns Notes: 1. For a reSTART condition, or following a write cycle. 2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP conditions. 3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (5 address MSB are not constant) the maximum programming time is doubled to 20ms. Table 8. AC Measurement Conditions Input Rise and Fall Times ≤ 50ns Input Pulse Voltages 0.2VCC to 0.8VCC Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC Figure 4. AC Testing Input Output Waveforms 0.8VCC 0.2VCC 0.7VCC 0.3VCC AI00825 6/17 DEVICE OPERATION I2C Bus Background The ST24/25x16 support the I2C protocol. This protocol defines any device that sends data onto the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master will always initiate a data transfer and will provide the serial clock for synchronisation. The ST24/25x16 are always slave devices in all communications. Start Condition. START is identified by a high to low transition of the SDA line while the clock SCL is stable in the high state. A START condition must precede any command for data transfer. Except during a programming cycle, the ST24/25x16 continuously monitor the SDA and SCL signals for a START condition and will not respond unless one is given. ST24/25C16, ST24/25W16 Figure 5. AC Waveforms tCHCL tCLCH SCL tDLCL tDXCX tCHDH SDA IN tCHDX START CONDITION tCLDX tDHDL SDA INPUT SDA CHANGE STOP & BUS FREE SCL tCLQV tCLQX DATA VALID SDA OUT DATA OUTPUT SCL tW SDA IN tCHDH STOP CONDITION tCHDX WRITE CYCLE START CONDITION AI00795B 7/17 ST24/25C16, ST24/25W16 Figure 6. I2C Bus Protocol SCL SDA START CONDITION SCL 1 SDA MSB SDA INPUT 2 SDA CHANGE STOP CONDITION 3 7 8 9 ACK START CONDITION SCL 1 SDA MSB 2 3 7 8 9 ACK STOP CONDITION AI00792 Stop Condition. STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the ST24/25x16 and the bus master. A STOP condition at the end of a Read command forces the standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle. Acknowledge Bit (ACK). An acknowledge signal is used to indicate a successful data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse period the receiver pulls the SDA bus low to acknowledge the receipt of the 8 bits of data. 8/17 Data Input. During data input the ST24/25x16 samples the SDA bus signal on the rising edge of the clock SCL. Note that for correct device operation the SDA signal must be stable during the clock low to high transition and the data must change ONLY when the SCL line is low. Memory Addressing. To start communication between the bus master and the slave ST24/25x16, the master must initiate a START condition. The 8 bits sent after a START condition are made up of a device select of 4 bits that identifie the device type (1010), 3 Block select bits and one bit for a READ (RW = 1) or WRITE (RW = 0) operation. There are three modes both for read and write. They are summarised in Table 4 and described hereafter. A communication between the master and the slave is ended with a STOP condition. ST24/25C16, ST24/25W16 Figure 7. Memory Protection PB1 Block Select PB0 1 Protect Location 16 byte boundary address b7 7FFh Protect Flag Enable = 0 Disable = 1 b4 PB1 PB0 b2 0 X X Block 7 1 1 Block 6 1 0 Block 5 0 1 Block 4 0 0 700h 600h 500h 400h AI00870B Write Operations The Multibyte Write mode (only available on the ST24/25C16 versions) is selected when the MODE pin is at VIH and the Page Write mode when MODE pin is at VIL. The MODE pin may be driven dynamically with CMOS input levels. Following a START condition the master sends a device select code with the RW bit reset to ’0’. The memory acknowledges this and waits for a byte address. The byte address of 8 bits provides access to any of the 256 bytes of one memory block. After receipt of the byte address the device again responds with an acknowledge. For the ST24/25W16 versions, any write command with WC = ’1’ (during a period of time from the START condition untill the end of the Byte Address) will not modify data and will NOT be acknowledged on data bytes, as in Figure 10. Byte Write. In the Byte Write mode the master sends one data byte, which is acknowledged by the memory. The master then terminates the transfer by generating a STOP condition. The Write mode is independant of the state of the MODE pin which could be left floating if only this mode was to be used. However it is not a recommended operating mode, as this pin has to be connected to either VIH or VIL, to minimize the stand-by current. Multibyte Write (ST24/25C16 only). For the Multibyte Write mode, the MODE pin must be at VIH. The Multibyte Write mode can be started from any address in the memory. The master sends from one up to 8 bytes of data, which are each acknowledged by the memory. The transfer is terminated by the master generating a STOP condition. The duration of the write cycle is tW = 10ms maximum except when bytes are accessed on 2 contiguous rows (one row is 16 bytes), the programming time is then doubled to a maximum of 20ms. Writing more than 8 bytes in the Multibyte Write mode may modify data bytes in an adjacent row (one row is 16 bytes long). However, the Multibyte Write can properly write up to 16 consecutive bytes only if the first address of these 16 bytes is the first address of the row, the 15 following bytes being written in the 15 following bytes of this same row. 9/17 ST24/25C16, ST24/25W16 Page Write. For the Page Write mode, the MODE pin must be at VIL. The Page Write mode allows up to 16 bytes to be written in a single write cycle, provided that they are all located in the same ’row’ in the memory: that is the same Block Address bits (b3, b2, b1 of Device Select code in Table 3) and the same 4 MSBs in the Byte Address. The master sends one up to 16 bytes of data, which are each acknowledged by the memory. After each byte is transfered, the internal byte address counter (4 Least Significant Bits only) is incremented. The transfer is terminated by the master generating a STOP condition. Care must be taken to avoid address counter ’roll-over’ which could result in data being overwritten. Note that for any write mode, the generation by the master of the STOP condition starts the internal memory program cycle. All inputs are disabled until the completion of this cycle and the memory will not respond to any request. Minimizing System Delay by Polling On ACK. During the internal Write cycle, the memory disconnects itself from the bus in order to copy the data from the internal latches to the memory cells. The maximum value of the Write time (tW) is given in the AC Characteristics table, this timing value may be reduced by an ACK polling sequence issued by the master. The sequence is: – Initial condition: a Write is in progress (see Figure 8). – Step 1: the Master issues a START condition followed by a Device Select byte (1st byte of the new instruction). – Step 2: if the memory is internally writing, no ACK will be returned. The Master goes back to Step1. If the memory has terminated the internal writing, it will issue an ACK indicating that the memory is ready to receive the second part of the instruction (the first byte of this instruction was already sent during Step 1). Figure 8. Write Cycle Polling using ACK WRITE Cycle in Progress START Condition DEVICE SELECT with RW = 0 NO First byte of instruction with RW = 0 already decoded by ST24xxx ACK Returned YES NO Next Operation is Addressing the Memory YES Send Byte Address ReSTART STOP Proceed WRITE Operation Proceed Random Address READ Operation AI01099B 10/17 ST24/25C16, ST24/25W16 Write Protection. Data in the upper four blocks of 256 bytes of the memory may be write protected. The memory is write protected between a boundary address and the top of memory (address 7FFh).The boundary address is user defined by writing it in the Block Address Pointer (location 7FFh). The Block Address Pointer is an 8 bit EEPROM register located at the address 7FFh. It is composed by 4 MSBs Address Pointer, which defines the bottom boundary address, and 4 LSBs which must be programmed at ’0’. This Address Pointer can therefore address a boundary by page of 16 bytes. The block in which the Block Address Pointer defines the boundary of the write protected memory is defined by the logic level applied on the PB1 and PB0 input pins: – PB1 =’0’and PB0 =’0’ select block 4 – PB1 =’0’and PB0 =’1’ select block 5 – PB1 =’1’and PB0 =’0’ select block 6 – PB1 =’1’and PB0 =’1’ select block 7 The following sequence should be used to set the Write Protection: – write the data to be protected into the top of the memory, up to, but not including, location 7FFh; – select the block by hardwiring the signals PB0 & PB1; – set the protection by writing the correct bottom boundary address in the Address Pointer (4 MSBs of location 7FFh) with bit b2 (Protect Flag) set to ’0’. Note that for a correct fonctionality of the memory, all the 4 LSBs of the Block Address Pointer must also be programmed at ’0’. The area will be protected when the PRE input is taken High. Remark: The Write Protection is active if and only if the PRE input pin is driven High and the bit 2 of location 7FFh is set to ’0’. In all the other cases, the memory Block will not be protected. While the PRE input pin is read at ’0’ by the memory, the location 7FFh can be used as a normal EEPROM byte. Caution: Special attention must be used when using the protect mode together with the Multibyte Write mode (MODE input pin High). If the Multibyte Write starts at the location right below the first byte of the Write Protected area, then the instruction will write over the first 7 bytes of the Write Protected area. The area protected is therefore smaller than the content defined in the location 7FFh, by 7 bytes. This does not apply to the Page Write mode as the address counter ’roll-over’ and thus cannot go above the 16 bytes lower boundary of the protected area. Figure 9. Write Modes Sequence (ST24/25C16) ACK BYTE ADDR DATA IN R/W ACK START DEV SEL ACK BYTE ADDR ACK DATA IN 1 DATA IN 2 R/W ACK ACK DATA IN N STOP MULTIBYTE AND PAGE WRITE ACK STOP DEV SEL START BYTE WRITE ACK AI00793 11/17 ST24/25C16, ST24/25W16 Figure 10. Write Modes Sequence with Write Control = 1 (ST24/25W16) WC ACK BYTE ADDR NO ACK DATA IN STOP DEV SEL START BYTE WRITE ACK R/W WC ACK DEV SEL START PAGE WRITE ACK BYTE ADDR NO ACK DATA IN 1 DATA IN 2 R/W WC (cont'd) NO ACK DATA IN N STOP PAGE WRITE (cont'd) NO ACK AI01161B Read Operation Read operations are independent of the state of the MODE signal. On delivery, the memory content is set at all "1’s" (or FFh). Current Address Read. The memory has an internal byte address counter. Each time a byte is read, this counter is incremented. For the Current Address Read mode, following a START condition, the master sends a memory address with the RW bit set to ’1’. The memory acknowledges this and outputs the byte addressed by the internal byte address counter. This counter is then incremented. The master does NOT acknowledge the byte output, but terminates the transfer with a STOP condition. 12/17 Random Address Read. A dummy write is performed to load the address into the address counter (see Figure 11). This is followed by another START condition from the master and the byte address repeated with the RW bit set to ’1’. The memory acknowledges this and outputs the byte addressed. The master does NOT acknowledge the byte output, but terminates the transfer with a STOP condition. Sequential Read. This mode can be initiated with either a Current Address Read or a Random Address Read. However, in this case the master DOES acknowledge the data byte output and the memory continues to output the next byte in sequence. To terminate the stream of bytes, the master must NOT acknowledge the last byte out- ST24/25C16, ST24/25W16 Figure 11. Read Modes Sequence ACK DATA OUT STOP START DEV SEL R/W ACK RANDOM ADDRESS READ BYTE ADDR R/W ACK START DEV SEL DATA OUT R/W ACK ACK DATA OUT 1 NO ACK DATA OUT N R/W ACK START DEV SEL * ACK BYTE ADDR R/W ACK ACK DEV SEL * START SEQUENTIAL RANDOM READ NO ACK STOP SEQUENTIAL CURRENT READ ACK DEV SEL * START START DEV SEL * ACK STOP CURRENT ADDRESS READ NO ACK ACK DATA OUT 1 R/W NO ACK STOP DATA OUT N AI00794C Note: * The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical. put, but MUST generate a STOP condition. The output data is from consecutive byte addresses, with the internal byte address counter automatically incremented after each byte output. After a count of the last memory address, the address counter will ’roll- over’ and the memory will continue to output data. Acknowledge in Read Mode. In all read modes the ST24/25x16 wait for an acknowledge during the 9th bit time. If the master does not pull the SDA line low during this time, the ST24/25x16 terminate the data transfer and switches to a standby state. 13/17 ST24/25C16, ST24/25W16 ORDERING INFORMATION SCHEME Example: Operating Voltage ST24C16 Range 24 4.5V to 5.5V C Standard 25 2.5V to 5.5V W Hardware Write Control M 1 TR Package B PSDIP8 0.25mm Frame M SO8 150mil Width Temperature Range 1 0 to 70 °C 6 –40 to 85 °C Option TR Tape & Reel Packing 3 (1) –40 to 125 °C Note: 1. Temperature range on special request only. Devices are shipped from the factory with the memory content set at all "1’s" (FFh). For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 14/17 ST24/25C16, ST24/25W16 PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame mm Symb Typ inches Min Max A 3.90 A1 Min Max 5.90 0.154 0.232 0.49 – 0.019 – A2 3.30 5.30 0.130 0.209 B 0.36 0.56 0.014 0.022 B1 1.15 1.65 0.045 0.065 C 0.20 0.36 0.008 0.014 D 9.20 9.90 0.362 0.390 E 7.62 – – 6.00 6.70 – – eA 7.80 eB Typ – – 0.236 0.264 – – – 0.307 – – 10.00 – 0.394 L 3.00 3.80 0.118 0.150 N 8 E1 e1 2.54 0.100 8 A2 A1 B 0.300 A L e1 eA eB B1 D C N E1 E 1 PSDIP-a Drawing is not to scale. 15/17 ST24/25C16, ST24/25W16 SO8 - 8 lead Plastic Small Outline, 150 mils body width mm Symb Typ inches Min Max A 1.35 A1 Min Max 1.75 0.053 0.069 0.10 0.25 0.004 0.010 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.00 0.150 0.157 – – – – H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 0.90 0.016 0.035 α 0° 8° 0° 8° N 8 e 1.27 Typ 0.050 8 CP 0.10 0.004 h x 45˚ A C B CP e D N E H 1 A1 SO-a Drawing is not to scale. 16/17 α L ST24/25C16, ST24/25W16 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 1999 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners Purchase of I2C Components by STMicroelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com 17/17