STMICROELECTRONICS ST63140

ST63140, ST63146
ST63126, ST63156
DATA SHEET
1st Edition
OCTOBER 1993
USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED.
SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics.
As used herein :
1. Life support devices or systems are those which (a) are
intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided with the product, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can reasonably be expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
ST631xx DATASHEET INDEX
Pages
ST63140, ST63142
ST63126, ST63156
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ST631xx CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STACK SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WAIT & STOP MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ON-CHIP CLOCK OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INPUT/OUTPUT PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION . . . . . . . . . . . . . . . . . . .
SERIAL PERIPHERAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14-BIT VOLTAGE SYNTHESIS TUNING
PERIPHERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-BIT PWM D/A CONVERTER AND 62.5 kHz OUTPUT FUNCTION . . . . . . . . . . . . . . . .
AFC A/D INPUT, KEYBOARD INPUTS
AND BANDSWITH OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INFRARED INPUT (IRIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ON-SCREEN DISPLAY (OSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOFTWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ORDERING INFORMATION TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ST63E140/T140, E142/T142
ST63E126/T126, E156/T156
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . .
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . .
EPROM/OTP DESCRIPTION. . . . . . . . . . . . . . . . . . . .
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . .
EEPROM INFORMATION . . . . . . . . . . . . . . . . . . . . .
PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . .
ORDERING INFORMATION TABLE . . . . . . . . . . . . . . . .
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1
3
5
7
10
16
16
20
22
23
24
27
30
31
40
41
43
44
45
54
59
60
63
65
67
69
71
74
75
76
79
82

ST63140, ST63142
ST63126, ST63156

8-BIT HCMOS MCUs FOR
TV FREQUENCY & VOLTAGE SYNTHESIS WITH OSD
PRELIMINARY DATA
4.5 to 6V operating Range
8MHz Maximum Clock Frequency
User Program ROM: 7948 bytes
Reserved Test ROM: 244 bytes
Data ROM:
user selectable size
Data RAM:
256 bytes
Data EEPROM:
128 bytes
40-Pin Dual in Line Plastic Package for the
ST63126, 156
28-Pin Dual in Line Plastic Package for the
ST63140, 142
Up to 18 software programmable general purpose Inputs/Outputs, including 8 direct LED
driving Outputs
3 Inputs for keyboard scan (KBY0-2)
Up to 4 high voltage outputs (BSW0-3)
Two Timers each including an 8-bit counter with
a 7-bit programmable prescaler
Digital Watchdog Function
Serial Peripheral Interface (SPI) supporting
S-BUS/ I2C BUS and standard serial protocols
Up to Four 6-bit PWM D/A Converters
62.5kHz Output pin
14 bit counter for voltage synthesis tuning
(ST63156, ST63140)
AFC A/D converter with 0.5V resolution
Four interrupt vectors (IRIN/NMI, Timer 1 & 2,
VSYNC.)
On-chip clock oscillator
5 Lines by 15 Characters On-Screen Display
Generator with 128 Characters (2 banks)
All ROM types are supported by pin-to-pin
EPROM and OTP versions.
The development tool of the ST631xx microcontrollers consists of the ST63TVS-EMUemulation
and development system to be connected via a
standard RS232 serial line to an MS-DOS Personal Computer.
1
PDIP40
1
PDIP28
(Ordering Information at the end of the datasheet)
DEVICE SUMMARY
ROM
(Bytes)
TUN.
I/O Pins
Package
ST63126
8K
FS
12
PDIP40
ST63156
8K
VS
11
PDIP40
ST63140
8K
VS
6
PDIP28
ST63142
8K
FS
6
PDIP28
DEVICE
October 1993
This is Preliminary information from SGS-THOMSON. Details are subject to change without notice.
1/82
ST63140,142,126,156
Figure 1. ST63126, 156 Pin Configuration
BSW0
BSW1
BSW2
BSW3
KBY0
KBY 1
KBY2
OSDOSCout
OSDOSCin
(SEN) PB7
(SDA) PB6
(SCL) PB5
(HSYNC) PB3
(VSYNC) PB2
AFC
(1)
TEST
PA6
PA5
PA4
V SS
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VDD
DA3
DA2
DA1
DA0
OUT1
IRIN
PC7 (B)
PC6 (G)
PC5 (R)
PC3 (BLANK)
PC2 (ON/OFF)
PC1
PC0
OSCout
OSCin
RESET
PA1
PA2
PA3
BSW0
BSW
BSW2
BSW3
KBY0
KBY 1
KBY2
OSDOSCout
OSDOSCin
(SEN) PB7
(SDA) PB6
(SCL) PB5
(HSYNC) PB3
(VSYNC) PB2
AFC
(1)
TEST
PA6
PA5
PA4
V SS
VA00282
ST63126
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VDD
DA3
DA2
DA1
DA0
OUT1
IRIN
VS
PC7 (B)
PC6 (G)
PC5 (R)
PC3 (BLANK)
PC2 (ON/OFF)
PC1
OSCout
OSCin
RESET
PA1
PA2
PA3
VA00288
ST63156
Note 1. This pin is also the V PP input for EPROM based devices
Figure 2. ST63140, 142 Pin Configuration
BSW0
1
28
V DD
BSW0
1
28
VDD
BSW1
BSW2
KBY0
2
3
4
27
26
25
DA0
OUT1
VS
BSW1
BSW2
KBY0
2
3
4
27
26
25
DA0
OUT1
IRIN
KBY1
KBY2
OSDOSCout
5
6
7
24
23
22
PC6 (G)
PC4
PC3 (BLANK)
KBY1
KBY2
OSDOSCout
5
6
7
24
23
22
PC6 (G)
PC5 (R)
PC4
OSDOSCin
PB3 (HSYNC)
PB2 (VSYNC)
8
9
10
21
20
19
PC2
OSCout
OSCin
OSDOSCin
PB3 (HSYNC)
PB2 (VSYNC)
8
9
10
21
20
19
PC2
OSCout
OSCin
AFC
(1)
TEST
PA4
V SS
11
12
13
18
17
16
RESET
PA0
PA1
AFC
(1)
TEST
PA4
11
12
13
18
17
16
RESET
PA0
PA1
14
15
PA2
VSS
14
15
PA2
VR001390
VR001389
ST63142
ST63140
Note 1. This pin is also the V PP input for EPROM based devices
2/82

ST63140,142,126,156
GENERAL DESCRIPTION
The ST63140, 142, 126, 156 microcontrollers are
members of the 8-bit HCMOS ST631xx family, a
series of devices specially oriented to TV applications. Different ROM size and peripheral configurations are available to give the maximum application
and cost flexibility. All ST631xx members are
based on a building block approach: a common
core is surrounded by a combination of on-chip peripherals (macrocells) available from a standard library. These peripherals are designed with the
same Core technology providing full compatibility
and short design time. Many of these macrocells
are specially dedicated to TV applications. The
macrocells of the ST631xx family are: two Timer
peripherals each including an 8-bit counter with a
7-bit software programmable prescaler (Timer), a
digital hardware activated watchdog function
(DHWD), a 14-bit voltage synthesis tuning peripheral, a Serial Peripheral Interface (SPI), up to four
6-bit PWM D/A converters, an AFC A/D converter
with 0.5V resolution, an on-screen display (OSD)
with 15 characters per line and 128 characters (in
two banks each of 64 characters). In addition the
following memory resources are available: program ROM (7K), data RAM (256 bytes), EEPROM
(128 bytes).
Refer to pin configuration figures and to ST631xx
device summary (Table 1) for the definition of
ST631xx family members and a summary of differences among the different types.
3/82

ST63140,142,126,156
Figure 3. ST631xx Block Diagram
* Refer To Pin Configuration For Additional Information
TEST
IRIN/NMI
TEST
PORT A
PA0 - PA7
IR INTERRUPT
Input
PORT B
PB2 - PB7 *
PORT C
PC0 - PC7 *
DATA ROM
USER SELECTABLE
USER PROGRAM
ROM
8 KBytes
SERIAL PERIPHERAL
INTERFACE
DATA RAM
256 Bytes
TIMER 1
DATA EEPROM
128 Bytes
TIMER 2
DIGITAL
WATCHDOG/TIMER
PC
STACK
STACK
STACK
STACK
STACK
STACK
LEVEL 1
LEVEL 2
LEVEL 3
LEVEL 4
LEVEL 5
LEVEL 6
POWER SUPPLY
VDD
*
VSS
D / A Outputs
DA0 - DA3
VS output &
AFC Input
AFC & VS *
8-BIT CORE
OSCILLATOR
OSCin
ON-SCREEN
DISPLAY
RESET
OSCout
RESET
OSDOSCin
R, G, B, BLANK
HSYNC (PB3)
VSYNC (PB2)
VR 01 753E
OSDOSCout
Table 1. Device Summary
DEVICE
ROM RAM
(Bytes) (Bytes)
EEPROM
(Bytes)
I/O
KBY
I/O
BSW
OUT
AFC
VS
D/A
PACK.
EMUL.
DEVICES
ST63126
8K
256
128
12
3
4
YES
NO
4
PDIP40
ST63E126
ST63156
8K
256
128
11
3
4
YES
YES
4
PDIP40
ST63E156
ST63140
8K
256
128
6
3
3
YES
YES
1
PDIP28
ST6E140
ST63142
8K
256
128
6
3
3
YES
NO
1
PDIP28
ST63E142
4/82

ST63140,142,126,156
PIN DESCRIPTION
VDD and VSS. Power is supplied to the MCU using
these two pins. VDD is power and VSS is the ground
connection.
OSCin, OSCout. These pins are internally connected to the on-chip oscillator circuit. A quartz
crystal or a ceramic resonator can be connected
between these two pins in order to allow the correct operation of the MCU with various stability/cost trade-offs. The OSCin pin is the input pin,
the OSCout pin is the output pin.
RESET. The active low RESET pin is used to start
the microcontroller to the beginning of its program.
TEST. The TEST pin must be held at VSS for normal operation.
PA0-PA7. These 8 lines are organized as one I/O
port (A). Each line may be configured as either an
input or as an output under software control of the
data direction register. Port A has an open-drain
(12V drive) output configuration with direct LED
driving capability (30mA, 1V).
PB2-PB3, PB5-PB7. These lines are organized as
one I/O port (B). Each line may be configured as
either an input with or without internal pull-up resistor or as an output under software control of the
data direction register. PB2-PB3 have a push-pull
configuration in output mode while PB5-PB7 are
open-drain (5V drive).
PB2 and PB3 lines are connected to the VSYNC
and HSYNC control signals of the OSD cell; to provide the right signals to the OSD these I/O lines
should be programmed in input mode and the user
can read “on the fly” the state of VSYNC and
HSYNC signals. PB2 is also connected with the
VSYNC Interrupt. The active polarity of VSYNC Interrupt signal is software controlled. The active polarity of these synchronization input pins to the
OSD macrocell can be selected by the user as
ROM mask option. If the device is specified to have
negative logic inputs, then when these signals are
low the OSD oscillator stops. If the device is specified to have positive logic inputs, then when these
signals are high the OSD oscillator stops.
PB5, PB6 and PB7 lines, when in output modes,
are “ANDed” with the SPI control signals. PB5 is
connected with the SPI clock signal (SCL), PB6
with the SPI data signal (SDA) while PB7 is connected with SPI enable signal (SEN).
PC0-PC7. These 8 lines are organized as one I/O
port (C). Each line may be configured as either an
input with or without internal pull-up resistor or as
an output under software control of the data direction register. PC0-PC2, PC4 have a push-pull configuration in output mode while PC3, PC5-PC7
(OSD signals) are open-drain (5V drive). PC3, PC5 ,
PC6 and PC7 lines when in output mode are
“ANDed” with the character and blank signals of
the OSD cell. PC3 is connected with the OSD
BLANK signal, PC5, PC6 and PC7 with the OSD R,
G and B signals. The active polarity of these signals can be selected by the user as ROM mask option. PC2 is also used as TV set ON-OFF switch
(5V drive).
DA0-DA3. These pins are the four PWM D/A outputs (with 32kHz repetition) of the 6-bit on-chip D/A
converters. The PWM function can be disabled by
software and these lines can be used as general
purpose open-drain outputs (12V drive).
IRIN. This pin is the external NMI of the MCU.
OUT1. This pin is the 62.5kHz output specially
suited to drive multi-standard chroma processors.
This function can be disabled by software and the
pin can be used as general purpose open-drain
output (12V drive).
BSW0-BSW3. These output pins can be used to
select up to 4 tuning bands. These lines are configured as open-drain outputs (12V drive).
KBY0-KBY2. These pins are input only and can be
used for keyboard scan. They have CMOS threshold levels with Schmitt Trigger and on-chip 100kΩ
pull-up resistors.
AFC. This is the input of the on-chip 10 level comparator that can be used to implement the AFC
function. This pin is an high impedance input able
to withstand signals with a peak amplitude up to
12V.
OSDOSCin, OSDOSCout. These are the On
Screen Display oscillator terminals. An oscillation
capacitor and coil network have to be connected to
provide the right signal to the OSD.
VS. This is the output pin of the on-chip 14-bit voltage synthesis tuning cell (VS). The tuning signal
present at this pin gives an approximate resolution
of 40kHz per step over the UHF band. This line is a
push-pull output with standard drive (ST63140,
ST63156 only).
5/82

ST63140,142,126,156
Table 2. Pin Summary
Pin Function
Description
DA0 to DA3
Output, Open-Drain, 12V
BSW0 to BSW3
Output, Open-Drain, 12V
IRIN
Input, Resistive Bias, Schmitt Trigger
AFC
Input, High Impedance, 12V
OUT1
Output, Open-Drain, 12V
KBY0 to KBY2
Input, Pull-up, Schmitt Trigger
R,G,B, BLANK
Output, Open-Drain, 5V
HSYNC, VSYNC
Input, Pull-up, Schmitt Trigger
OSDOSCin
Input, High Impedance
OSDOSCout
Output, Push-Pull
TEST
Input, Pull-Down
OSCin
Input, Resistive Bias, Schmitt Trigger to Reset Logic Only
OSCout
Output, Push-Pull
RESET
Input, Pull-up, Schmitt Trigger Input
VS
Output, Push-Pull
PA0-PA6
I/O, Open-Drain, 12V, No Input Pull-up, Schmitt Trigger, High Drive
PB2-PB3, PB5-PB7
I/O, Push-Pull, 5V, Input Pull-up, Schmitt Trigger
PB5-PB7
I/O, Open-Drain, 5V, Input Pull-up, Schmitt Trigger
PC0-PC2, PC4
I/O, Push-Pull, 5V, Input Pull-up, Schmitt Trigger
PC3, PC5-PC7
I/O, Open-Drain, 5V, Input Pull-up, Schmitt Trigger
VDD, VSS
Power Supply Pins
6/82

ST63140,142,126,156
ST631xx CORE
Figure 5. ST631xx Core Programming Model
The Core of the ST631xx Family is implemented
independently from the I/O or memory configuration. Consequently, it can be treated as an independent central processor communicating with I/O
and memory via internal addresses, data, and control busses. The in-core communication is arranged as shown in the following block diagram
figure; the controller being externally linked to both
the reset and the oscillator, while the core is linked
to the dedicated on-chip macrocells peripherals via
the serial data bus and indirectly for interrupt purposes through the control registers.
Registers
The ST631xx Family Core has six registers and
three pairs of flags available to the programmer.
They are shown in Figure 5 and are explained in
the following paragraphs together with the program and data memory page registers.
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic calculations, logical operations, and data manipulations. The accumulator is addressed in the data
space as RAM location at address FFh .
Accordingly, the ST631xx instruction set can use
the accumulator as any other register of the data
space.
INDEX
REGISTER
b11
b7
X REG. POINTER
b0
b7
Y REG. POINTER
b0
SHORT
DIRECT
ADDRESSING
MODE
b0
b7
V REGISTER
b7
W REGISTER
b0
b7
ACCUMULATOR
b0
b0
PROGRAM COUNTER
SIX LEVELS
STACK REGISTER
NORMAL FLAGS
C
Z
INTERRUPT FLAGS
C
Z
NMI FLAGS
C
Z
VA000423
Figure 4. ST631xx Core Block Diagram
0,0 1 TO 8MHz
OS Cin
RESET
OSCout
CONTROLLER
INTERRUPTS
DATA SPACE
OPCODE
FLAG
VALUES
CONTROL
SIGNALS
2
ADDRESS / READ LINE
DATA
RAM / EEPROM
PROGRAM
ROM/EPROM
ADDRESS
DECODER
DATA
256
ROM / EPROM
B-DATA
A-DATA
DEDICATIONS
12
Progr am Counter
a nd
6 LAYER STACK
ACCUMULATOR
FLAGS
ALU
RESULTS TO DATA SPACE ( WRITE LINE )
VR001811
7/82

ST63140,142,126,156
ST631xx CORE (Continued)
Indirect Registers (X, Y). These two indirect registers are used as pointers to the memory locations
in the data space. They are used in the register-indirect addressing mode.These registers can be
addressed in the data space as RAM locations at
the 80h (X) and 81h (Y) addresses. They can also
be accessed with the direct, short direct, or bit direct addressing modes. Accordingly, the ST631xx
instruction set can use the indirect registers as any
other register of the data space.
Short Direct Registers (V, W). These two registers are used to save one byte in short direct addressing mode. These registers can be addressed
in the data space as RAM locations at the 82h (V)
and 83H (W) addresses. They can also be accessed with the direct and bit direct addressing
modes. Accordingly, the ST631xx instruction set
can use the short direct registers as any other register of the data space.
Program Counter (PC)
The program counter is a 12-bit register that contains the address of the next ROM location to be
processed by the core. This ROM location may be
an opcode, an operand, or an address of operand.
The 12-bit length allows the direct addressing of
4096 bytes in the program space. Nevertheless, if
the program space contains more than 4096 locations, the further program space can be addressed
by using the Program ROM Page Register. The PC
value is incremented, after it is read for the address
of the current instruction, by sending it through the
ALU, so giving the address of the next byte in the
program. To execute relative jumps the PC and the
offset values are shifted through the ALU, where
they will be added, and the result is shifted back
into the PC. The program counter can be changed
in the following ways:
JP (Jump) instruction.... PC = Jump address
CALL instruction ........... PC= Call address
Relative Branch
instructions ................... PC= PC+offset
Interrupt........................ PC= Interrupt vector
Reset............................ PC= Reset vector
RET & RETI instructions............PC=Pop (stack)
Normal instruction ........ PC = PC+1
8/82

Flags (C, Z)
The ST631xx Core includes three pairs of flags
that correspond to 3 different modes: normal
mode, interrupt mode and Non-Maskable-Interrupt-Mode. Each pair consists of a CARRY flag
and a ZERO flag. One pair (CN, ZN) is used during
normal operation, one pair is used during the interrupt mode (CI,ZI) and one is used during the notmaskable interrupt mode (CNMI, ZNMI).
The ST631xx Core uses the pair of flags that corresponds to the actual mode: as soon as an interrupt
(resp. a Non-Maskable-Interrupt) is generated, the
ST631xx Core uses the interrupt flags (resp. the
NMI flags) instead of the normal flags. When the
RETI instruction is executed, the normal flags
(resp. the interrupt flags) are restored if the MCU
was in the normal mode (resp. in the interrupt
mode) before the interrupt. Should be observed
that each flag set can only be addressed in its own
routine (Not-maskable interrupt, normal interrupt
or main routine). The interrupt flags are not cleared
during the context switching and so, they remain in
the state they were at the exit of the last routine
switching.
The Carry flag is set when a carry or a borrow occurs during arithmetic operations, otherwise it is
cleared. The Carry flag is also set to the value of
the bit tested in a bit test instruction, and participates in the rotate left instruction.
The Zero flag is set if the result of the last arithmetic
or logical operation was equal to zero, otherwise it
is cleared.
The switching between these three sets is automatically performed when an NMI, an interrupt and
a RETI instructions occur. As the NMI mode is
automatically selected after the reset of the MCU,
the ST631xx Core uses at first the NMI flags.
ST63140,142,126,156
ST631xxx CORE (Continued)
Stack
The ST631xx Core includes true LIFO hardware
stack that eliminates the need for a stack pointer.
The stack consists of six separate 12-bit RAM locations that do not belong to the data space RAM
area. When a subroutine call (or interrupt request)
occurs, the contents of each level is shifted into the
next level while the content of the PC is shifted into
the first level (the value of the sixth level will be
lost). When subroutine or interrupt return occurs
(RET or RETI instructions), the first level register is
shifted back into the PC and the value of each level
is shifted back into the previous level. These two
operating modes are described in Figure 6. Since
the accumulator, as all other data space registers,
is not stored in this stack the handling of this registers shall be performed inside the subroutine. The
stack pointer will remain in its deepest position, if
more than 6 calls or interrupts are executed, so
that the last return address will be lost. It will also
remain in its highest position if the stack is empty
and a RET or RETI is executed. In this case the
next instruction will be executed.
Figure 6. Stack Operation
PROGRAM COUNTER
STACK LEVEL 1
RET OR RETI
WHEN
OCCURS
STACK LEVEL 1
STACK LEVEL 1
WHEN CALL
OR
INTERRUPT REQUEST
OCCURS
STACK LEVEL 1
STACK LEVEL 1
STACK LEVEL 1
VA000424
9/82

ST63140,142,126,156
MEMORY SPACES
The MCUs operate in three different memory
spaces: Program Space, Data Space, and Stack
Space. A description of these spaces is shown in
the following Figures.
Program Space
The program space is physically implemented in
the ROM and includes all the instructions that are
to be executed, as well as the data required for the
immediate addressing mode instructions, the reserved test area and user vectors. It is addressed
thanks to the 12-bit Program Counter register (PC
register) and so, the ST631xx Core can directly address up to 4K bytes of Program Space. Nevertheless, the Program Space can be extended by the
addition of 2-Kbyte ROM banks as it is shown in
Figure 8 in which the 8K bytes memory is described.
These banks are addressed by pointing to the
000h-7FFh locations of the Program Space thanks
to the Program Counter, and by writing the appropriate code in the Program ROM Page Register
(PRPR) located at address CAh of the Data
Space. Because interrupts and common subroutines should be available all the time only the lower
2K bytes of the 4K program space are bank
switched while the upper 2K bytes can be seen as
static space. Table 3 gives the codes that allow the
selection of the corresponding banks.
Note that, from the memory point of view, the Page
1 and the Static Page represent the same physical
memory: it is only a different way of addressing the
same location. On the ST631xx a total of 8192
bytes of ROM have been implemented; 7948 are
available as user ROM while 244 are reserved for
testing.
Figure 8. ST631xx 8K Bytes Program Space
Addressing Description
Program
counter
space
0000h
1FFFh
0FFFh
Static Page
Page 1
0800h
07FFh
Page 0
Page 1
Static Page
Page 2
Page 3
0000h
Figure 7. ST631xx Memory Addressing Description Diagram
STACK SPAC E
PROGRAM SPACE
DATA SPACE
000h
0000h
RAM / EEPROM
PROGRAM COUNTER
BANKING AR EA
0-63
STACK LEVEL 1
ROM
STACK LEVEL 2
STACK LEVEL 3
03Fh
040h
DATA ROM
STACK LEVEL 4
WINDOW
STACK LEVEL 5
070h
080h
081h
082h
083h
084h
STACK LEVEL 6
07FFh
0800h
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
RA M
ROM
0C 0h
DATA ROM
WIND OW SELECT
DATA RAM
BANK S ELECT
0FF0h
INTERRUPT &
0FFFh
RESET VEC TOR S
0FFh
AC CUMUL ATOR
VR001568
10/82

ST63140,142,126,156
MEMORY SPACES (Continued)
Figure 11. Program ROM Page Register
PRPR
Program ROM Page Register
(CAh, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
PRPR0 = PROG.ROM Select 0
PRPR1 = PROG.ROM Select 1
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
D7-D2. These bits are not used.
PRPR1-PRPR0. These are the program ROM
banking bits and the value loaded selects the corresponding page to be addressed in the lower part
of 4K program address space as specified in Table 3.
This register is undefined on reset.
Note:
Only the lower part of address space has been
bankswitched because interrupt vectors and common subroutines should be available all the time.
The reason of this structure is due to the fact that it
is not possible to jump from a dynamic page to another, unless jumping back to the static page,
changing contents of PRPR, and, then, jumping to
a different dynamic page.
Care is required when handling the PRPR as it is
write only. For this reason, it is not allowed to
change the PRPR contents while executing interrupts drivers, as the driver cannot save and than
restore its previous content. Anyway, this operation may be necessary if the sum of common routines and interrupt drivers will take more than 2K
bytes; in this case could be necessary to divide the
interrupt driver in a (minor) part in the static page
(start and end), and in the second (major) part in
one dynamic page. If it is impossible to avoid the
writing of this register in interrupts drivers, an image of this register must be saved in a RAM location, and each time the program writes the PRPR it
writes also the image register. The image register
must be written first, so if an interrupt occurs between the two instructions the PRPR is not affected.
Table 3. Program ROM Page Register Coding
PRPR1
PRPR0
PC11
Memory Page
X
X
1
Static Page (Page1)
0
0
0
Page 0
0
1
0
Page 1 (Static Page)
1
0
0
Page 2
1
1
0
Page 3
This register is undefined on reset. Neither
read nor single bit instructions may be used to
address this register.
Table 4. ST631xx Program ROM Map
Device Address
Device Address (1)
PAGE 0
0000h-007Fh
0080h-07FFh
0000h-007Fh
0080h-07FFh
Reserved
User ROM
PAGE 1
“STATIC”
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Vector
Reset Vector
PAGE 2
0000h-000Fh
0010h-07FFh
1000h-100Fh
1010h-17FFh
Reserved
User ROM
PAGE 3
0000h-000Fh
0010h-07FFh
1800h-180Fh
1810h-1FFFh
Reserved
User ROM
ROM Page
Description
Note 1. EPROM addresses relate to the use of ST63E1xx EPROM Emulation device.
11/82

ST63140,142,126,156
MEMORY SPACES (Continued)
Data Space
The instruction set of the ST631xx Core operates
on a specific space, named Data Space that contains all the data necessary for the processing of
the program. The Data Space allows the address-
ing of RAM (256 bytes for the ST631xx family),
EEPROM (128 bytes), ST631xx Core/peripheral
registers, and read-only data such as constants
and the look-up tables.
Figure 12. ST631xx Data Space
Figure 13. ST631xx Data Space (Continued)
b7
b7
b0
RESERVED
TIMER 2 PRESCALER REGISTER
TIMER 2 COUNTER REGISTER
TIMER 2 STATUS CONTROL REG.
b0
000h
DATA RAM/EEPROM/OSD
BANK AREA
03Fh
040h
DATA ROM
WINDOW AREA
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
RESERVED
07Fh
080h
081h
082h
083h
084h
DA0 DATA/CONTROL REGISTER
DA1 DATA/CONTROL REGISTER
DA2 DATA/CONTROL REGISTER
DA3 DATA/CONTROL REGISTER
AFC RESULT REGISTER
KEYBOARD INPUT REGISTER
RESERVED
RESERVED
DATA RAM BANK REGISTER
BSW CONTROL REGISTER
EEPROM CONTROL REGISTER
SPI CONTROL REGISTER 1
SPI CONTROL REGISTER 2
VS DATA REGISTER 1
VS DATA REGISTER 2
OSD CHARAC. BANK SELECT REG.
DATA RAM
PORT A DATA REGISTER
PORT B DATA REGISTER
PORT C DATA REGISTER
RESERVED
PORT A DIRECTION REGISTER
PORT B DIRECTION REGISTER
PORT C DIRECTION REGISTER
RESERVED
INTERR UPT OPTION REGISTER
DATA ROM WINDOW REGISTER
PROGRAM ROM PAGE REGISTER
RESERVED
SPI DATA REGISTER
0D9h
0DAh
0DBh
0DCh
0DDh
0BFh
0C0h
0C1h
0C2h
0C3h
0C4h
0C5h
0C6h
0C7h
0C8h
0C9h
0CAh
0CBh
0CCh
0CDh
0DFh
0E0h
0E1h
0E2h
0E3h
0E4h
0E5h
0E6h
0E7h
0E8h
0E9h
0EAh
0EBh
0ECh
0EDh
0EEh
0EFh
0F0h
RESERVED
ACCUMULATOR
0FEh
0FFh
RESERVED
TIMER 1 PRESCALER REGISTER
TIMER 1 COUNTER REGISTER
TIMER 1 STATUS/CONTROL REG.
0D1h
0D2h
0D3h
0D4h
0D5h
OSD CONTROL REGISTERS LOCATED
IN PAGE6 OF BANKED DATA RAM
VERTICAL START ADDRESS REG.
HORIZONTALSTART ADDRESS REG.
VERTICAL SPACE REGISTER
HORIZONTAL SPACE REGISTER
BACKGROUND COLOUR REGISTER
GLOBAL ENABLE REGISTER
RESERVED
WATCHD OG REGISTER
0D7h
0D8h
12/82

010h
011h
012h
013h
014h
017h
ST63140,142,126,156
MEMORY SPACES (Continued)
Figure 14. Data ROM Window Register
Data ROM Addressing. All the read-only data are
physically implemented in the ROM in which the
Program Space is also implemented. The ROM
therefore contains the program to be executed and
also the constants and the look-up tables needed
for the program. The locations of Data Space in
which the different constants and look-up tables
are addressed by the ST631xx Core can be considered as being a 64-byte window through which
it is possible to access to the read-only data stored
in the ROM. This window is located from address
40H to address 7Fh in the Data space and allows
the direct reading of the bytes from the address
000h to address 03Fh in the ROM. All the bytes of
the ROM can be used to store either instructions or
read-only data. Indeed, the window can be moved
by step of 64 bytes along the ROM in writing the
appropriate code in the Write-only Data ROM Window register (DRWR, location C9h). The effective
address of the byte to be read as a data in the ROM
is obtained by the concatenation of the 6 less significant bits of the address in the Data Space (as
less significant bits) and the content of the DRWR
(as most significant bits). So when addressing location 40h of data space, and 0 is loaded in the
DRWR, the physical addressed location in ROM is
00h.
DWR
Data ROM Window Register
(C9h, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
DWR0 = Data
DWR1 = Data
DWR2 = Data
DWR3 = Data
DWR4 = Data
DWR5 = Data
DWR6 = Data
UNUSED
ROM Window 0
ROM Window 1
ROM Window 2
ROM Window 3
ROM Window 4
ROM Window 5
ROM Window 6
D7. This bit is not used.
DWR6-DWR0. These are the Data Rom Window bits
thatcorrespondto theupperbits of data ROMprogram
space. This register is undefined after reset.
This register is undefined on reset. Neither
read nor single bit instructions may be used to
address this register.
Note. Care is required when handling the DRWR
as it is write only. For this reason, it is not allowed
to change the DRWR contents while executing interrupts drivers, as the driver cannot save and than
restore its previous content. If it is impossible to
avoid the writing of this register in interrupts drivers, an image of this register must be saved in a
RAM location, and each time the program writes
the DRWR it writes also the image register. The image register must be written first, so if an interrupt
occurs between the two instructions the DRWR
register is not affected.
Figure 15. Data ROM Window Memory Addressing
DATA ROM
13
WINDOW REGISTER 7
CONTENTS
12
11
10
9
8
7
6
6
5
4
3
2
1
0
(DWR)
5
4
3
2
1
0 PROGRAM SPACE ADDRESS
READ
5
4
3
2
1
0
0
1
0
0
0
1
0
1
1
0
0
1
0
0
0
1
1
0
0
1
DATA SPACE ADDRESS
40h-7Fh
IN INSTRUCTION
Example:
DWR=28h
ROM
ADDRESS:A19h
0
0
0
0
1
1
0
0
1
1
0
0
DATA SPACE ADDRESS
59h
VR01573B
13/82

ST63140,142,126,156
MEMORY SPACES (Continued)
Data RAM/EEPROM/OSD RAM Addressing
In all members of the ST631xx family 64 bytes of
data RAM are directly addressable in the data
space from 80h to BFh addresses. The additional
192 bytes of RAM, the 128 bytes of EEPROM , and
the OSD RAM can be addressed using the banks
of 64 bytes located between addresses 00h and
3Fh. The selection of the bank is done by programming the Data RAM Bank Register (DRBR) located
at the E8h address of the Data Space. In this way
each bank of RAM, EEPROM or OSD RAM can select 64 bytes at a time. No more than one bank
should be set at a time.
Figure 16. Data RAM Bank Register
DRBR
Data RAM
Bank Register
(E8h, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
DRBR0 = Data RAM Bank 0
DRBR1= Data RAM Bank 0
DRBR2= Data RAM Bank 0
DRBR3= Data RAM Bank 0
DRBR4= Data RAM Bank 0
DRBR5= Data RAM Bank 0
DRBR6= Data RAM Bank 0
UNUSED
D7. This bit is not used.
DRBR6, DRBR5. Each of these bits, when set, will
select one OSD RAM register page.
DRBR4,DRBR3,DRBR2. Each of these bits, when
set, will select one RAM page.
DRBR1,DRBR0. These bits select the EEPROM
pages.
This register is undefined after reset. Neither
read nor single bit instructions may be used to
address this register.
Table 5 summarizes how to set the Data RAM
Bank Register in order to select the various banks
or pages.
Note :
Care is required when handling the DRBR as it is
write only. For this reason, it is not allowed to
change the DRBR contents while executing interrupts drivers, as the driver cannot save and than
restore its previous content. If it is impossible to
avoid the writing of this register in interrupts drivers, an image of this register must be saved in a
RAM location, and each time the program writes
the DRBR it writes also the image register.
The image register must be written first, so if an interrupt occurs between the two instructions the
DRBR is not affected.
Table 5. Data RAM Bank Register Set-up
DRBR Value
Selection
Hex.
Binary
01h
0000 0001
EEPROM Page 0
02h
0000 0010
EEPROM Page 1
04h
0000 0100
RAM Page 2
08h
000 1000
10h
0001 0000
RAM Page 4
20h
0010 0000
OSD Page 5
40h
0100 0000
OSD Page 6
RAM Page 3
14/82

ST63140,142,126,156
MEMORY SPACES (Continued)
EEPROM Description
The data space of ST631xx family from 00h to 3Fh
is paged as described in Table 5. 128 bytes of
EEPROM located in 2 pages of 64 bytes (pages 0,
and 1, see Table 5).
Through the programming of the Data RAM Bank
Register (DRBR=E8h) the user can select the
bank or page leaving unaffected the way to address the static registers. The way to address the
“dynamic” page is to set the DRBR as described in
Table 5 (e.g. to select EEPROM page 0, the DRBR
has to be loaded with content 01h, see Data
RAM/EEPROM/OSD RAM addressing for additional information). Bits 0 and 1 of the DRBR are
dedicated to the EEPROM.
The EEPROM pages do not require dedicated instructions to be accessed in reading or writing. The
EEPROM is controlled by the EEPROM Control
Register (EECR=EAh). Any EEPROM location can
be read just like any other data location, also in
terms of access time.
To write an EEPROM location takes an average
time of 5 ms (10ms max) and during this time the
EEPROM is not accessible by the Core. A busy
flag can be read by the Core to know the EEPROM
status before trying any access. In writing the
EEPROM can work in two modes: Byte Mode
(BMODE) and Parallel Mode (PMODE). The
BMODE is the normal way to use the EEPROM
and consists in accessing one byte at a time. The
PMODE consists in accessing 8 bytes per time.
Figure 17. EEPROM Control Register
EECR
EEPROM Control Register
(EAh, Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
EN = EEPROM Enable Bit
BS = EEPROM Busy Bit
PE = Parallel Mode Enable Bit
PS = Parallel Start Bit
Reserved (Must be set Low)
Reserved (Must be set Low)
SB = Stand-by Enable Bit
Unused
D7. Not used
SB. WRITE ONLY. If this bit is set the EEPROM is
disabled (any access will be meaningless) and the
power consumption of the EEPROM is reduced to
the leakage values.
D5, D4. Reserved, they must be set to zero.
PS. SET ONLY. Once in Parallel Mode, as soon as
the user software sets the PS bit the parallel writing
of the 8 adjacent registers will start. PS is internally
reset at the end of the programming procedure.
Note that less than 8 bytes can be written; after
parallel programming the remaining undefined
bytes will have no particular content.
PE. WRITE ONLY. This bit must be set by the user
program in order to perform parallel programming
(more bytes per time). If PE is set and the “parallel
start bit” (PS) is low, up to 8 adjacent bytes can be
written at the maximum speed, the content being
stored in volatile registers. These 8 adjacent bytes
can be considered as row, whose A7, A6, A5, A4,
A3 are fixed while A2, A1 and A0 are the changing
bytes. PE is automatically reset at the end of any
parallel programming procedure. PE can be reset
by the user software before starting the programming procedure, leaving unchanged the EEPROM
registers.
BS. READ ONLY. This bit will be automatically set
by the CORE when the user program modifies an
EEPROM register. The user program has to test it
before any read or write EEPROM operation; any
attempt to access the EEPROM while “busy bit” is
set will be aborted and the writing procedure in progress completed.
EN. WRITE ONLY. This bit MUST be set to one in
order to write any EEPROM register. If the user
program will attempt to write the EEPROM when
EN= “0” the involved registers will be unaffected
and the “busy bit” will not be set.
AfterRESET the contentof EECR register will be 00h.
Notes :
When the EEPROM is busy (BS=“1”) the EECR
can not be accessed in write mode, it is only possible to read BS status. This implies that as long as
the EEPROM is busy it is not possible to change
the status of the EEPROM control register. EECR
bits 4 and 5 are reserved for test purposes, and
must never be set to “1”.
15/82

ST63140,142,126,156
MEMORY SPACES (Continued)
Additional Notes on Parallel Mode. If the user
wants to perform a parallel programming the first
action should be the set to one the PE bit; from this
moment the first time the EEPROM will be addressed in writing, the ROW address will be
latched and it will be possible to change it only at
the end of the programming procedure or by resetting PE without programming the EEPROM. After
the ROW address latching the Core can “see” just
one EEPROM row (the selected one) and any attempt to write or read other rows will produce errors. Do not read the EEPROM while PE is set.
As soon as PE bit is set, the 8 volatile ROW latches
are cleared. From this moment the user can load
data in the whole ROW or just in a subset. PS setting will modify the EEPROM registers corresponding to the ROW latches accessed after PE. For
example, if the software sets PE and accesses
EEPROM in writing at addresses 18h,1Ah,1Bh
and then sets PS, these three registers will be
modified at the same time; the remaining bytes will
have no particular content. Note that PE is internally reset at the end of the programming procedure. This implies that the user must set PE bit
between two parallel programming procedures.
Anyway the user can set and then reset PE without
performing any EEPROM programming. PS is a
set only bit and is internally reset at the end of the
programming procedure. Note that if the user tries
to set PS while PE is not set there will not be any
programming procedure and the PS bit will be unaffected. Consequently PS bit can not be set if EN
is low. PS can be affected by the user set if, and
only if, EN and PE bits are also set to one.
STACK SPACE
The stack space consists of six 12 bit registers that
are used for stacking subroutine and interrupt return addresses plus the current program counter
register.
16/82

INTERRUPT
The ST631xx Core can manage 4 different maskable interrupt sources, plus one non-maskable interrupt source (top priority level interrupt). Each
source is associated with a particular interrupt vector that contains a Jump instruction to the related
interrupt service routine. Each vector is located in
the Program Space at a particular address (see
Table 6). When a source provides an interrupt request, and the request processing is also enabled
by the ST631xx Core, then the PC register is
loaded with the address of the interrupt vector (i.e.
of the Jump instruction). Finally, the PC is loaded
with the address of the Jump instruction and the interrupt routine is processed.
The relationship between vector and source and
the associated priority is hardware fixed for the different ST631xx devices. For some interrupt
sources it is also possible to select by software the
kind of event that will generate the interrupt.
All interrupts can be disabled by writing to the GEN
bit (global interrupt enable) of the interrupt option
register (address C8h). After a reset, ST631xx is in
non maskable interrupt mode, so no interrupts will
be accepted and NMI flags will be used, until a
RETI instruction is executed. If an interrupt is executed, one special cycle is made by the core, during that the PC is set to the related interrupt vector
address. A jump instruction at this address has to
redirect program execution to the beginning of the
related interrupt routine. The interrupt detecting cycle, also resets the related interrupt flag (not available to the user), so that another interrupt can be
stored for this current vector, while its driver is under execution.
If additional interrupts arrive from the same source,
they will be lost. NMI can interrupt other interrupt
routines at any time, while other interrupts cannot
interrupt each other. If more than one interrupt is
waiting for service, they are executed according to
their priority. The lower the number, the higher the
priority. Priority is, therefore, fixed. Interrupts are
checked during the last cycle of an instruction
(RETI included). Level sensitive interrupts have to
be valid during this period.
ST63140,142,126,156
INTERRUPT (Continued)
Table 6. Interrupt Vectors/Sources Relationships
Interrupt
Source
Associated
Vector
Vector Address
IRIN/NMI
(1)
Pin
Interrupt
Vector # 0 (NMI)
0FFCh-0FFDh
Interrupt
Vector # 1
0FF6h-0FF7h
Vsync
Interrupt
Vector # 2
0FF4h-0FF5h
Timer 1
Interrupt
Vector # 3
0FF2h-0FF3h
Timer 2
Interrupt
Vector # 4
0FF0h-0FF1h
None
(2)
Interrupt Option Register
The Interrupt Option Register (IOR register, location C8h) is used to enable/disable the individual
interrupt sources and to select the operating mode
of the external interrupt inputs. This register can be
addressed in the Data Space as RAM location at
the C8h address, nevertheless it is write-only register that can not be accessed with single-bit operations. The operating modes of the external
interrupt inputs associated to interrupt vectors #1
and #2 are selected through bits 5 and 6 of the IOR
register.
Figure 18. Interrupt Option Register
IOR
Notes:
1. This pin is associated with the NMI Interrupt Vector
2. This vector is not used in ST631xx.
Interr upt Option Register
(C8h, Write Only)
Interrupt Vectors/Sources
The ST631xx Core includes 5 different interrupt
vectors in order to branch to 5 different interrupt
routines. The interrupt vectors are located in the
fixed (or static) page of the Program Space.
The interrupt vector associated with the non-maskable interrupt source is named interrupt vector #0.
It is located at addresses FFCh,FFDh in the Program Space. This vector is associated with the
PC6/IRIN pin.
The interrupt vectors located at addresses
(FF6h,FF7h),
(FF4h,FF5h),
(FF2h,FF3h),
(FF0h,FF1h) are named interrupt vectors #1, #2,
#3 and #4 respectively. These vectors are associated with TIMER 2 (#4), VSYNC (#2), and TIMER
1 (#3). Interrupt vector (#1) is not used on
ST631xx.
Interrupt Priority
The non-maskable interrupt request has the highest priority and can interrupt any other interrupt
routines at any time, nevertheless the other interrupts cannot interrupt each other. If more than one
interrupt request is pending, they are processed by
the ST631xx Core according to their priority level:
vector #1 has the higher priority while vector #4 the
lower. The priority of each interrupt source is hardware fixed.
D7 D6 D5 D4 D3 D2 D1 D0
Unuse d
GEN = Global Enab le Bit
ES2 = Edge Selection Bit
EL1 = Edge Level Selection Bit
Unuse d
D7. Not used.
EL1. This is the Edge/Level selection bit of interrupt #1. When set to one, the interrupt is generated
on low level of the related signal; when cleared to
zero, the interrupt is generated on falling edge. The
bit is cleared to zero after reset and as no interrupt
source is associated to vector #1 on ST631xx, the
user must keep this bit at zero to avoid ghost interrupts from this source.
ES2. This is the edge selection bit on interrupt #2.
This bit is used on the ST631xx devices with onchip OSD generator for VSYNC detection.
GEN. This is the global enable bit. When set to one
all interrupts are globally enabled; when this bit is
cleared to zero all interrupts are disabled (EXcluding NMI).
D3 - D0. These bits are not used.
17/82

ST63140,142,126,156
INTERRUPT (Continued)
Interrupt Procedure. The interrupt procedure is
very similar to a call procedure, indeed the user
can consider the interrupt as an asynchronous call
procedure. As this is an asynchronous event the
user does not know about the context and the time
at which it occurred. As a result the user should
save all the data space registers which will be used
inside the interrupt routines. There are separate
sets of processor flags for normal, interrupt and
non-maskable interrupt modes which are automatically switched and so these do not need to be
saved.
The following list summarizes the interrupt procedure:
ST631xx actions
- Interrupt detection
- The flags C and Z of the main routine are exchanged with the flags C and Z of the interrupt
routine (or the NMI flags)
value of the PC is stored in the first level of
- The
the stack
- The normal interrupt lines are inhibited (NMI
still active)
- First internal latch is cleared
- The related interrupt vector is loaded in the PC.
User actions
selected registers are saved inside the in- User
terrupt service routine (normally on a software
stack)
source of the interrupt is found by polling
- The
(if more than one source is associated to the
same vector) the interrupt flag of the source.
- Interrupt servicing
- Return from interrupt (RETI)
ST631xx actions
the ST631xx core switches back
- Automatically
to the normal flags (or the interrupt flags) and
pops the previous PC value from the stack
The interrupt routine begins usually by the identification of the device that has generated the interrupt request (by polling). The user should save the
registers which are used inside the interrupt routine (that holds relevant data) into a software stack.
After the RETI instruction execution, the core carries out the previous actions and the main routine
can continue.
18/82

Figure 19. Interrupt Processing Flow-Chart
INSTRUCTION
FE TCH
INST RUCTION
EX ECUTE
INST RUCTION
WA S
THE INST RUCTION
A RETI
NO
LOAD PC FROM
INTERRUPT VECTOR
( FF C / FFD )
YE S
YES
IS THE CORE
ALREADY IN
NORMAL MODE ?
?
SET
INTE RRUPT MAS K
NO
CLEA R
INTERRUPT MAS K
PUSH THE
PC INTO THE STAC K
SELECT
PROGRAM FLA GS
SEL ECT
INTERNAL MODE FLAG
” POP ”
THE STACK ED PC
NO
CHECK IF THERE IS
AN INTERRUPT REQUES T
AND INTE RRUPT MASK
?
YES
VA000014
ST631xx Interrupt Details
IR Interrupt (#0). The IRIN Interrupt is connected
to the first interrupt #0 (NMI, 0FFCh). If enabled,
then an interrupt will be generated on a rising edge
at the pin.
Interrupt (#1). On ST631xx no sources are associated to vector (#1). To avoid any ghost interrupt
due to interrupt (#1) the user must keep the EL1
bit of IOR register to zero.
ST63140,142,126,156
INTERRUPT (Continued)
VSYNC Interrupt (#2). The VSYNC Interrupt is
connected to the interrupt #2. When disabled the
VSYNC INT signal is low. Bit 5 of the interrupt option register C8h is used to select the negative
edge (ES2=0) or the positive edge (ES2=1); the
edge willdepend on the application. Note that once
an edge has been latched, then the only way to remove the latched signal is to service the interrupt.
Care must be taken not to generate spurious interrupts. This interrupt may be used for synchronize
to the VSYNC signal in order to change characters
in the OSD only when the screen is on vertical
blanking (if desired). This method may also be
used to blink characters.
TIMER 1 Interrupt (#3). The TIMER 1 Interrupt is
connected to the fourth interrupt #3 (0FF2h) which
detects a low level (latched in the timer).
TIMER 2 Interrupt (#4). The TIMER 2 Interrupt is
connected to the fifth interrupt #4 (0FF0h) which
detects a high to low level (latched in the timer).
Notes: Global disable does not reset edge sensitive interrupt flags. These edge sensitive interrupts
become pending again when global disabling is released. Moreover, edge sensitive interrupts are
stored in the related flags also when interrupts are
globally disabled, unless each edge sensitive interrupt is also individually disabled before the interrupting event happens. Global disable is done by
clearing the GEN bit of Interrupt option register,
while any individual disable is done in the control
register of the peripheral. The on-chip Timer peripherals have an interrupt request flag bit (TMZ),
this bit is set to one when the device wants to generate an interrupt request and a mask bit (ETI) that
must be set to one to allow the transfer of the flag
bit to the Core.
19/82

ST63140,142,126,156
RESET
The ST631xx device can be reset in two ways: by
the external reset input (RESET ) tied low, by
power-on reset and by the digital Watchdog peripheral.
RESET Input
The external active low RESET pin is used to reset
the ST631xx devices and provide an orderly software startup procedure. The activation of the RESET pin may occur in the RUN or WAIT mode.
Even short pulses at the reset pin will be accepted
since the reset signal is latched internally and is
only cleared after 2048 clocks at the oscillator pin.
The clocks from the oscillator pin to the reset circuitry are buffered by a Schmitt Trigger so that an
oscillator in start-up conditions will not give spurious clocks. The MCU is configured in the Reset
mode as long as the signal of the RESET pin is low.
The processing of the program is stopped and the
standard Input/Outputports (port A, port B and port
C) are in the input state (except PC2). As soon as
the level on the RESET pin becomes high, the initialization sequence is executed.
Figure 20. Internal Reset Circuit
20/82

Watchdog Reset
The ST631xx devices are provided with an onchip hardware activated digital watchdog function
in order to provide a graceful recovery from a software upset. If the watchdog register is not refreshed and the end-of-count is reached, then the
reset state will be latched into the MCU and an internal circuit pulls down the RESET pin. This also
resets the watchdog which subsequently turns off
the pull-down and activates the pull-up device at
the RESET pin. This causes the positive transition
at the RESET pin. The MCU will then exit the reset
state after 2048 clocks on the oscillator pin.
Application Notes
An external resistor between VDD and reset pin is
not required because an internal pull-up device is
provided. The user may prefer to add an external
pull-up resistor.
An internal Power-on device does not guarantee
that the MCU will exit the reset state when VDD is
above 4.5V and therefore the RESET pin should
be externally controlled.
ST63140,142,126,156
RESET (Continued)
Figure 21. Reset & Interrupt Processing
Flow-Chart
Figure 22. Restart Initialization Program
Flow-Chart
RESET
RESET
JP
JP: 2 BYTES/4 CYCLES
RESET VECTOR
NMI MASK SET
INT LATCH CLEARED
( IF PRESENT )
INITIALIZATION
ROUTINE
RETI
SELECT
NMI MODE FLAGS
PUT FFEh
ON ADDRESS BUS
YES
RETI: 1BYTES/2 CYCLES
VA 000181
MCU Initialization Sequence
When a reset occurs the stack is reset to the program counter, the PC is loaded with the address of
the reset vector (located in the program ROM at
addresses FFEh & FFFh). A jump instruction to the
beginning of the program has to be written into
these locations. After a reset a NMI is automatically activated so that the core is in non-maskable
interrupt mode to prevent false or ghost interrupts
during the restart phase. Therefore the restart routine should be terminated by a RETI instruction to
switch to normal mode and enable interrupts. If no
pending interrupt is present at the end of the reset
routine the ST631xx will continue with the instruction after the RETI; otherwise the pending interrupt
will be serviced.
IS RESET
STILL PRESENT ?
NO
LOAD PC
FROM RESET LOCATIONS
FFE / FFF
FETCH INSTRUCTION
VA000427
21/82

ST63140,142,126,156
WAIT & STOP MODES
The STOP and WAIT modes have been implemented in the ST631xx Core in order to reduce the
consumption of the device when the latter has no
instruction to execute. These two modes are described in the following paragraphs. On ST631xx
as the hardware activated digital watchdog function is present the STOP instruction is de-activated
and any attempt to execute it will cause the automatic execution of a WAIT instruction.
WAIT Mode
The configuration of the MCU in the WAIT mode
occurs as soon as the WAIT instruction is executed. The microcontroller can also be considered
as being in a “software frozen” state where the
Core stops processing the instructions of the routine, the contents of the RAM locations and peripheral registers are saved as long as the power
supply voltage is higher than the RAM retention
voltage but where the peripherals are still working.
The WAIT mode is used when the user wants to reduce the consumption of the MCU when it is in idle,
while not losing count of time or monitoring of external events. The oscillator is not stopped in order
to provide clock signal to the peripherals. The timers counting may be enabled (writing the PSI bit in
TSCR register) and the timer interrupt may be also
enabled before entering the WAIT mode; this allows the WAIT mode to be left when timer interrupt
occurs. If the exit from the WAIT mode is performed with a general RESET (either from the activation of the external pin or by watchdog reset) the
MCU will enter a normal reset procedure as described in the RESET chapter. If an interrupt is
generated during WAIT mode the MCU behaviour
depends on the state of the ST631xx Core before
the initialization of the WAIT sequence, but also of
the kind of the interrupt request that is generated.
This case will be described in the following paragraphs. In any case, the ST631xx Core does not
generate any delay after the occurrence of the interrupt because the oscillator clock is still available.
STOP Mode
On ST631xx the hardware watchdog is present
and the STOP instruction has been de-activated.
Any attempt to execute a STOP will cause the
automatic execution of a WAIT instruction.
Exit from WAIT Mode
The following paragraphs describe the output procedure of the ST631xx Core from WAIT mode
when an interrupt occurs. It must be noted that the
restart sequence depends on the original state of
22/82

the MCU (normal, interrupt or non-maskable interrupt mode) before the start of the WAIT sequence,
but also of the type of the interrupt request that is
generated. In all cases the GEN bit of IOR has to
be set to 1 in order to restart from WAIT Mode.
Contrary to the operation of NMI in the RUN Mode,
the NMI is masked in WAIT Mode if GEN=0.
Normal Mode. If the ST631xx Core was in the
main routine when the WAIT instruction has been
executed, the ST631xx Core outputs from the wait
mode as soon as any interrupt occurs; the related
interrupt routine is executed and at the end of the
interrupt service routine the instruction that follows
the WAIT instruction is executed if no other interrupts are pending.
Non-maskable Interrupt Mode. If the WAIT instruction has been executed during the execution
of the non-maskable interrupt routine, the ST631xx
Core outputs from the wait mode as soon as any
interrupt occurs: the instruction that follows the
WAIT instruction is executed and the ST631xx
Core is still in the non-maskable interrupt mode
even if another interrupt has been generated.
Normal Interrupt Mode. If the ST631xx Core was
in the interrupt mode before the initialization of the
WAIT sequence, it outputs from the wait mode as
soon as any interrupt occurs. Nevertheless, two
cases have to be considered:
the interrupt is a normal interrupt, the inter- Ifrupt
routine in which the WAIT was entered will
be completed with the execution of the instruction that follows the WAIT and the ST631xx
Core is still in the interrupt mode. At the end of
this routine pending interrupts will be serviced
in accordance to their priority.
- If the interrupt is a non-maskable interrupt, the
non-maskable routine is processed at first.
Then, the routine in which the WAIT was entered will be completed with the execution of
the instruction that follows the WAIT and the
ST631xx Core is still in the normal interrupt
mode.
Notes :
If all the interrupt sources are disabled, the restart
of the MCU can only be done by a Reset activation.
The Wait instruction is not executed if an enabled
interrupt request is pending. In the ST631xx the
hardware activated digital watchdog function is
present. As the watchdog is always activated the
STOP instruction is de-activated and any attempt
to execute the STOP instruction will cause an execution of a WAIT instruction.
ST63140,142,126,156
ON-CHIP CLOCK OSCILLATOR
The internal oscillator circuit is designed to require
a minimum of external components. A crystal
quartz, a ceramic resonator, or an external signal
(provided to the OSCin pin) may be used to generate a system clock with various stability/cost tradeoffs. The typical clock frequency is 8MHz. Please
note that different frequencies will affect the operation of those peripherals (D/As, SPI, 62.5 kHz
OUT) whose reference frequencies are derived
from the system clock.
The different clock generator options connection
methods are shown in Figures 24 and 25. One machine cycle takes 13 oscillator pulses; 12 clock
pulses are needed to increment the PC while and
additional 13th pulse is needed to stabilize the internal latches during memory addressing. This
means that with a clock frequency of 8MHz the machine cycle is 1.625µSec.
The crystal oscillator start-up time is a function of
many variables: crystal parameters (especially
RS), oscillator load capacitance (CL), IC parameters, ambient temperature, and supply voltage.It
must be observed that the crystal or ceramic leads
and circuit connections must be as short as possible. Typical values for CL1 and CL2 are in the
range of 15pF to 22pF but these should be chosen
based on the crystal manufacturers specification.
Typical input capacitance for OSCin and OSCout
pins is 5pF.
The oscillator output frequency is internallydivided
by 13 to produce the machine cycle and by 12 to
produce the Timer and the Watchdog clock. A byte
cycle is the smallest unit needed to execute any
operation (i.e., increment the program counter). An
instruction may need two, four, or five byte cycles
to be executed (See Table 7).
Figure 23. Clock Generator Option (1)
Figure 24. Clock Generator Option (2)
Figure 25. OSCin, OSCout Diagram
Table 7. Intructions Timing with 8MHz Clock
Cycles
Execution
Time
Branch if set/reset
5 Cycles
8.125µs
Branch & Subroutine Branch
4 Cycles
6.50µs
Bit Manipulation
4 Cycles
6.50µs
Load Instruction
4 Cycles
6.50µs
Arithmetic & Logic
4 Cycles
6.50µs
Conditional Branch
2 Cycles
3.25µs
Program Control
2 Cycles
3.25µs
Instruction Type
23/82

ST63140,142,126,156
INPUT/OUTPUT PORTS
The ST631xx microcontrollers use three standard
I/O ports (A,B,C) with up to eight pins on each port;
refer to the device pin configurations to see which
pins are available.
Each line can be individually programmed either in
the input mode or the output mode as follows by
software.
- Output
with on-chip pull-up resistor (selected by
- Input
software)
without on-chip pull-up resistor (selected
- Input
by software)
Note: pins with 12V open-drain capability do not
have pull-up resistors.
In output mode the following hardware configurations are available:
- Open-drain output 12V (PA0-PA7)
output 5V (PB5-PB7, PC3, PC5- Open-drain
PC7)
- Push-pull output (PB0-PB4, PC0-PC2, PC4)
The lines are organized in three ports (port A,B,C).
The ports occupy 6 registers in the data space.
Each bit of these registers is associated with a particular line (for instance, the bits 0 of the Port A
Data and Direction registers are associated with
the PA0 line of Port A).
There are three Data registers (DRA, DRB, DRC),
that are used to read the voltage level values of the
lines programmed in the input mode, or to write the
logic value of the signal to be output on the lines
configured in the output mode. The port Data Registers can be read to get the effective logic levels of
the pins, but they can be also written by the user
software, in conjunction with the related Data Direction Register, to select the different input mode
options. Single-bit operations on I/O registers (bit
set/reset instructions) are possible but care is necessary because reading in input mode is made
from I/O pins and therefore might be influenced by
the external load, while writing will directly affect
the Port data register causing an undesired
changes of the input configuration. The three Data
Direction registers (DDRA, DDRB, DDRC) allow
the selection of the direction of each pin (input or
output).
All the I/O registers can be read or written as any
other RAM location of the data space. During the
initialization of the MCU, all the I/O registers are
cleared and the input mode with pull-up is selected
on all the pins thus avoiding pin conflicts (with the
exception of PC2 which is set in output mode and
is set low).
24/82

Details of I/O Ports
When programmed as an input a pull-up resistor (if
available) can be switched active under program
control. When programmed as an output the I/O
port will operate either in the push-pull mode or the
open-drain mode according to the hardware fixed
configuration as specified below.
Port A. PA0-PA7 are available as an open-drain
only (no push-pull programmability and no resistive pull-up in input mode) capable of withstanding
12V while the normal open drain has standard ratings of VDD + 0.3V. This I/O port has been specially
designed for direct LED driving and is able to sink
up to 30mA with a maximum VOL of 1V.
Some Port B and C lines are also used as I/O buffers for signals coming from the on-chip SPI and
OSD.
In this case the final signal on the output pin is
equivalent to a wired AND with the programmed
data output.
If the user needs to use the SPI or the OSD, then
the I/O line should be set in output mode while the
open-drain configuration is fixed in hardware ; the
corresponding data bit must be set to one.
PB2 and PB3 must be programmed in input mode
to provide the HSYNC and VSYNC input signals to
the OSD.
On ST631xx the I/O pins with double or special
functions are:
(connected to the OSD VSYNC
- PB2/VSYNC
signal)
(connected to the OSD HSYNC
- PB3/HSYNC
signal)
- PB5/SCL (connected to the SPI clock signal)
- PB6/SDA (connected to the SPI data signal)
- PB7/SEN (connected to the SPI enable signal)
this I/O is specially suited to TV
- PC2-ON-OFF,
SET ON-OFF and for this reason at reset the
related Data Direction bit will be automatically
set to one (I/O line is in output mode), while the
rest of the port is in input mode
(connected to the OSD Blank sig- PC3/BLANK
nal)
- PC5/R, PC6/G, PC7/B (connected to the OSD
R-G-B signals)
All the Port A,B and C I/O lines have Schmitt-trigger input configuration with a typical hysteresis of
1V.
ST63140,142,126,156
INPUT/OUTPUT PORTS (Continued)
I/O Pin Programming
Each pin can be individually programmed as input or
output with different input and output configurations.
This is achieved by writing to the relevant bit in the
data (DR) and data direction register (DDR). Table
8 shows all the port configurations that can be selected by the user software.
Figure 24. Port A, B, C Data Register
Figure 25. Port A, B, C Data Direction Register
DDRPA, DDRPB,DDRPC
Port A, B, C Data Direction Register
( C4h PA, C5h PB, C6h PC Read/ Write )
D7 D6 D5 D4 D3 D2 D1 D0
PA0 - PA7 = Data Direction Bits
PB0 - PB7 = Data Direction Bits
PC0 - PC7 = Data Direction Bits
“0” Defines bit as Inpu t
”1” Defines bit as Outpu t
DRA, DRB, DRC
Port A, B, C Data Register
( C0h PA, C1h PB, C2h PC Read/ Write )
D7 D6 D5 D4 D3 D2 D1 D0
PA0 - PA7 = Data Bits
PB0 - PB7 = Data Bits
PC0 - PC7 = Data Bits
PA7-PA0.These are the I/O port A data bits. Reset
at power-on.
PB7-PB0.These are the I/O port B data bits. Reset
at power-on.
PC7-PC0. These are the I/O port C data bits. Reset
at power-on.
PA7-PA0. These are the I/O port A data direction
bits. When a bit is cleared to zero the related I/O
line is in input mode, if bit is set to one the related
I/O line is in output mode. Reset at power-on.
PB7-PB0. These are the I/O port B data direction
bits. When a bit is cleared to zero the related I/O
line is in input mode, if bit is set to one the related
I/O line is in output mode. Reset at power-on.
PC7-PC0. These are the I/O port C data direction
bits. When a bit is cleared to zero the related I/O
line is in input mode, if bit is set to one the related
I/O line is in output mode. Set to 04h at power-on.
Bit 2 (PC2 pin) is set to one (output mode selected)
as this line is intended for TV ON-OFF switching.
Table 8. I/O Port Options Selection
DDR
DR
Mode
Option
0
0
Input
With on-chip pull-up
resistor
0
1
Input
Without on-chip pull-up
resistor
1
X
Output
Open-drain or Push-Pull
Note: X: Means don’t care.
25/82

ST63140,142,126,156
INPUT/OUTPUT PORTS (Continued)
Input/Output Configurations
The following schematics show the I/O lines hardware configuration for the different options. Figure
30 shows the I/O configuration for an I/O pin with
open-drain 12V capability (standard drive and high
drive). Figure 31 shows the I/O configuration for an
I/O pin with push-pull and with open drain 5V capability.
Figure 26. I/O Configuration Diagram
(Open Drain 12V)
Notes :
The WAIT instruction allows the ST631xx to be
used in situations where low power consumption is
needed. This can only be achieved however if the
I/O pins either are programmed as inputs with well
defined logic levels or have no power consuming
resistive loads in output mode. As the same die is
used for the different ST631xx versions the unavailable I/O lines of ST631xx should be programmed in output mode.
Single-bit operations on I/O registers are possible
but care is necessary because reading in input
mode is made from I/O pins while writing will directly affect the Port data register causing an undesired changes of the input configuration.
Figure 27. I/O Configuration Diagram (Open Drain 5V, Push-pull)
26/82

ST63140,142,126,156
TIMERS
The ST631xx devices offer two on-chip Timer peripherals consisting of an 8-bit counter with a 7-bit
programmable prescaler, thus giving a maximum
count of 215, and a control logic that allows configuring the peripheral operating mode. Figure 30
shows the timer block diagram. The content of the
8-bit counters can be read/written in the
Timer/Counter registers TCR that can be addressed in the data space as RAM location at addresses D3h (Timer 1) and DBh (Timer 2). The
state of the 7-bit prescaler can be read in the PSC
register at addresses D2h (Timer 1) and DAh
(Timer 2). The control logic is managed by TSCR
registers at D4h (Timer 1) and DCh (Timer 2) addresses as described in the following paragraphs.
The following description applies to both Timer 1
and Timer 2. The 8-bit counter is decrement by the
output (rising edge) coming from the 7-bit prescaler and can be loaded and read under program
control. When it decrements to zero then the TMZ
(timer zero) bit in the TSCR is set to one. If the ETI
(enable timer interrupt) bit in the TSCR is also set
to one an interrupt request, associated to interrupt
vector #3 (for Timer 1) and #1 for Timer 2, is generated. The interrupt of the timer can be used to exit
the MCU from the WAIT mode.
The prescaler decrements on rising edge. The
prescaler input is the oscillator frequency divided
by 12 or an external clock at TIMER pin (this is not
available in ST631xx).
Depending on the division factor programmed by
PS2/PS1/PS0 (see table 9) bits in the TSCR, the
clock input of the timer/counter register is multiplexed to different sources.
On division factor 1, the clock input of the prescaler is
also that of timer/counter; on factor2, bit 0 of prescaler
register is connectedto the clock input of TCR.
This bit changes its state with the half frequency of
prescaler clock input. On factor 4, bit 1 of PSC is
connected to clock input of TCR, and so on. On division factor 128, the MSB bit 6 of PSC is connected to clock input of TCR. The prescaler
initialize bit (PSI) in the TSCR register must be set
to one to allow the prescaler (and hence the
counter) to start. If it is cleared to zero then all of
the prescaler bits are set to one and the counter is
inhibited from counting.
The prescaler can be given any value between 0
and 7Fh by writing to the related register address,
if bit PSI in the TSCR register is set to one. The tap
of the prescaler is selected using the
PS2/PS1/PS0bits in the control register. Figure 33
shows the timer working principle.
Figure 28. Timer Peripheral Block Diagram
27/82

ST63140,142,126,156
TIMERS (Continued)
Figure 29. Timer Working Principle
Timer Operating Modes
As the external TIMER pin is not available on
ST631xx devices, the only allowed operating mode
is the output mode that have to be selected by setting to 1 bit 4 and by clearing to 0 bit 5 in the TSCR1
register. This procedure will enable both Timer 1 and
Timer 2.
Output Mode (TSCR1 D4 = 1, TSCR1 D5 = 0). On
this mode the timer prescaler is clocked by the
prescaler clock input (OSC/12). The user can select the desired prescaler division ratio through the
PS2/PS1/PS0 bits. When TCR count reaches 0, it
sets the TMZ bit in the TSCR.
The TMZ bit can be tested under program control
to perform timer functions whenever it goes high.
Bit D4 and D5 on TSCR2 (Timer 2) register are not
implemented.
Timer Interrupt
When the counter register decrements to zero and
the software controlled ETI (enable timer interrupt)
bit is set to one then an interrupt request associated to interrupt vector #3 (for Timer 1) and to interrupt vector #4 (for Timer 2) is generated. When the
counter decrements to zero also the TMZ bit in the
TSCR register is set to one.
28/82

Notes :
TMZ is set when the counter reaches 00h ; however, it may be set by writing 00h in the TCR register or setting the bit 7 of the TSCR register. TMZ
bit must be cleared by user software when servicing the timer interrupt to avoid undesired interrupts
when leaving the interrupt service routine. After reset, the 8-bit counter register is loaded to FFh while
the 7-bit prescaler is loaded to 7Fh , and the TSCR
register is cleared which means that timer is
stopped (PSI=0) and timer interrupt disabled.
A write to the TCR register will predominate over
the 8-bit counter decrement to 00h function, i.e. if a
write and a TCR register decrement to 00h occur
simultaneously, the write will take precedence, and
the TMZ bit is not set until the 8-bit counter reaches
00h again. The values of the TCR and the PSC
registers can be read accurately at any time.
ST63140,142,126,156
TIMERS (Continued)
The TSCR1 and TSCR2 registers are cleared on
reset. The correct D4-D5 combination must be
written in TSCR1 by user’s software to enable the
operation of Timer 1 and Timer 2.
Figure 30. Timer Status Control Registers
TSCR
Timer 1&2 Status Control
Register s
D4h Timer 1, DCh Timer 2,
Read/ Write
Table 9. Prescaler Division Factors
D7 D6 D5 D4 D3 D2 D1 D0
PS0 = Prescaler Mux. Select
PS1 = Prescaler Mux. Select
PS2 = Prescaler Mux. Select
PSI = Prescaler Initialize Bit
D4 = Timers Enable Bit*
D5 = Timers Enable Bit*
ETI = Enable Timer Inte rrupt
TMZ = Timer Zero Bit
*
PS2
PS1
PS0
Divided By
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
Only Available in TSCR1
TMZ. Low-to-high transition indicates that the timer
count register has decrement to zero. This bit must
be cleared by user software before to start with a
new count.
ETI. This bit, when set, enables the timer interrupt
(vector #3 for Timer 1, vector #4 for Timer 2) request.
If ETI=0 the timer interrupt is disabled. If ETI= 1 and
TMZ= 1 an interrupt request is generated.
D5. This is the timers enable bit D5. It must be
cleared to 0 together with a set to 1 of bit D4 to enable both Timer 1 and Timer 2 functions. It is not
implemented on TSCR2 register.
D4. This is the timers enable bit D4. This bit must
be set to 1 together with a clear to 0 of bit D5 to enable both Timer 1 and Timer 2 functions. It is not
implemented on TSCR2 register.
D5
D4
Timers
0
0
Disabled
0
1
Enabled
1
X
Reserved
Figure 31. Timer Counter Registers
TCR
Timer Counter 1&2 Register
D3h Timer 1, DBh Timer 2, Read/ Write
D7 D6 D5 D4 D3 D2 D1 D0
D7 - D0 = Counter bits
Figure 32. Timer Counter Registers
PSC
PSI. Used to initialize the prescaler and inhibit its
countingwhile PSI = 0 the prescaler is set to 7Fh and
the counter is inhibited. When PSI = 1 the prescaler
is enabled to count downwards. As long as PSI= 0
both counter and prescaler are not running.
PS2-PS0. These bits select the division ratio of the
prescaler register (see Table 9)
TimerPrescaler 1&2 Register
D2h Timer 1, DAh Timer 2, Read/ Write
D7 D6 D5 D4 D3 D2 D1 D0
D6 - D0 = Prescaler bits
Always read as “0”
29/82

ST63140,142,126,156
HARDWARE ACTIVATED DIGITAL WATCHDOG
FUNCTION
The hardware activated digital watchdog function
consists of a down counter that is automatically initialized after reset so that this function does not
need to be activated by the user program. As the
watchdog function is always activated this down
counter can not be used as a timer. The watchdog
is using one data space register (HWDR location
D8h). The watchdog register is set to FEh on reset
and immediately starts to count down, requiring no
software start. Similarly the hardware activated
watchdog can not be stopped or delayed by software.
The watchdog time can be programmed using the 6
MSbits in the watchdog register, this gives the possibility to generate a reset in a time between 3072 to
196608 oscillator cycles in 64 possible steps (With a
clock frequency of 8MHz this means from 384µs to
24.576ms). The reset is prevented if the register is
reloaded with the desired value before bits 2-7
decrement from all zeros to all ones.
The presence of the hardware watchdog deactivates
the STOP instruction and a WAIT instruction is automatically executed instead of a STOP. Bit 1 of the
watchdog register (set to one at reset) can be used
to generate a software reset if cleared to zero).
Figure 34. Hardware Activated Watchdog
Working Principle
Figure 33. Hardware Activated Watchdog Block Diagram
30/82

ST63140,142,126,156
HARDWARE ACTIVATED DIGITAL WATCHDOG
FUNCTION (Continued)
Figure 35. Watchdog Register
HWDR
Hardware Activated Watchdog Register
(D8h, Read/ Write)
D7 D6 D5 D4 D3 D2 D1 D0
C = Watchdog Activation Bit
SR = Software Reset Bit
T1-T6 = Counter Bits
T1-T6. These are the watchdog counter bits. It
should be noted that D7 (T1) is the LSB of the
counter and D2 (T6) is the MSB of the counter,
these bits are in the opposite order to normal.
SR. This bit is set to one during the reset phase
and will generate a software reset if cleared to
zero.
C. This is the watchdog activation bit that is hardware set to one; the user can not change the value
of this bit. The watchdog function is always activated independently of changes of value of this bit.
The register reset value is FEh (Bit 1-7 set to one,
Bit 0 cleared).
SERIAL PERIPHERAL INTERFACE
The ST631xx Serial Peripheral Interface (SPI) has
been designed to be cost effective and flexible in
interfacing the various peripherals in TV applications.
It maintains the software flexibility but adds hardware configurations suitable to drive devices which
require a fast exchange of data. The three pins
dedicated for serial data transfer (single master
only) can operate in the following ways:
- as standard I/O lines (software configuration)
- as S-BUS or as I2CBUS (two pins)
- as standard (shift register) SPI
When using the hardware SPI, a fixed clock rate of
62.5kHz is provided.
It has to be noted that the first bit that is output on
the data line by the 8-bit shift register is the MSB.
SPI Data/Control Registers
For I/O details on SCL (Serial Clock), SDA (Serial
Data) and SEN (Serial Enable) please refer to I/O
Ports description with reference to the following
registers:
Port B data register, Address C1h (Read/Write).
- BIT D5 “SCL”
- BIT D6 “SDA”
- BIT D7 “SEN”
Port B data direction register, Address C5h
(Read/Write).
Figure 36. SPI Serial Data Register
SSDR
SPI Serial Data Register
(CCh, Read/ Write)
D7 D6 D5 D4 D3 D2 D1 D0
D0-D7 = Data Bits
D7-D0. These are the SPI data bits. They can be
neither read nor written when SPI is operating
(BUSY bit set). They are undefined after reset.
31/82

ST63140,142,126,156
SERIAL PERIPHERAL INTERFACE (Continued)
Figure 38. SPI Control Register 2
Figure 37. SPI Control Register 1
SCR1
SCR2
SPI Control Register 1
(EBh, Write Only)
SPI Control Register 2
(ECh, Read/ Write)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
2
BSY = Busy Bit 0
ACN = Acknowledge Bit
VRY/S = Verify/Sync.Enab le
TX/RX = Enable Bit
Unuse d
S-BUS/I C BUS Selection
STD/SPI Enable
STP = Stop Bit 2
STR = Start Bit 3
Unused
D7-D4. These bits are not used.
STR. This is Start bit for I2CBUS/S-BUS. This bit is
meaningless when STD/SPI enable bit is cleared to
zero. If this bit is set to one STD/SPI bit is also set to
“1” and SPI Start generation, before beginning of
transmission, is enabled. Set to zero after reset.
STP. This is Stop bit for I2CBUS/S-BUS. This bit is
meaningless when STD/SPI enable bit is cleared
to zero. If this bit is set to one STD/SPI bit is also
set to “1” and SPI Stop condition generation is enabled. STP bit must be reset when standard protocol is used (this is also the default reset
conditions). Set to zero after reset.
STD, SPI Enable. This bit, in conjunction with SBUS/I2CBUS bit, allows the SPI disable and will
select between I2CBUS/S-BUS and Standard
shift register protocols. If this bit is set to one, it
selects both I2CBUS and S-BUS protocols; final
selection between them is made by S-BUS/I2CBUS
bit. If this bit is cleared to zero when S-BUS/I2CBUS
is set to “1” the Standard shift register protocol is
selected. If this bit is cleared to “0” when SBUS/I2CBUS is cleared to 0 the SPI is disabled.
Set to zero after reset.
S-BUS/I2CBUS Selection. This bit, in conjunction
with STD/SPI bit, allows the SPI disable and will
select between I2CBUS and S-BUS protocols. If
this bit is cleared to “0” when STD bit is also “0”, the
SPI interface is disabled. If this bit is cleared to zero
when STD bit is set to “1”, the I2CBUS protocol will
be selected. If this bit is set to “1” when STD bit is
set to “1”, the S-BUS protocol will be selected.
Cleared to zero after reset.
Table 10. SPI Modes Selection
D1
STD/SP
D0
2
S-BUS/I C BUS
0
0
Disabled
0
1
STD Shift Reg.
1
0
I2C BUS
1
1
S-BUS
SPI Function
32/82

D7-D4. These bits are not used.
TX/RX.Write Only. When this bit is set, current byte
operation is a transmission. When it is reset, current operation is a reception. Set to zero after reset.
VRY/S.Read Only/Write Only. This bit has two different functions in relation to read or write operation. Reading Operation: when STD and/or TRX
bits is cleared to 0, this bit is meaningless. When
bits STD and TX are set to 1, this bit is set each
time BSY bit is set. This bit is reset during byte operation if real data on SDA line are different from
the output from the shift register. Set to zero after
reset. Writing Operation : it enables (if set to one)
or disables (if cleared to zero) the interrupt coming
from VSYNC pin. Undefined after reset. Refer to
OSD description for additional information.
ACN.Read Only. If STD bit (D1 of SCR1 register) is
cleared to zero this bit is meaningless. When STD
is set to one, this bit is set to one if no Acknowledge
has been received. In this case it is automatically
reset when BSY is set again. Set to zero after reset.
BSY.Read/Set Only. This is the busy bit. When a
one is loaded into this bit the SPI interface start the
transmission of the data byte loaded into SSDR
data register or receiving and building the receive
data into the SSDR data register. This is done in
accordance with the protocol, direction and
start/stop condition(s). This bit is automatically
cleared at the end of the current byte operation.
Cleared to zero after reset.
Note :
The SPI shift register is also the data transmission
register and the data received register; this feature
is made possible by using the serial structure of the
ST631xx and thus reducing size and complexity.
ST63140,142,126,156
SERIAL PERIPHERAL INTERFACE (Continued)
During transmission or reception of data, all access to serial data register is therefore disabled.
The reception or transmission of data is started by
setting the BUSY bit to “1”; this will be automatically reset at the end of the operation. After reset,
the busy bit is cleared to “0”, and the hardware SPI
disabled by clearing bit 0 and bit 1 of SPI control
register 1 to “0”. The outputs from the hardware
SPI are “ANDed” to the standard I/O software controlled outputs. If the hardware SPI is in operation
the Port C pins related to the SPI should be configured as outputs using the Data Direction Register
and should be set high. When the SPI is configured
as the S-BUS, the three pins PC0, PC1 and PC3
become the pins SCL, SDA and SEN respectively.
When configured as the I2CBUS the pins PC0 and
PC1 are configured as the pins SCL and SDA; PC3
is not driven and can be used as a general purpose
I/O pin. In the case of the STD SPI the pins PC0
and PC1 become the signals CLOCK and DATA,
PC3 is not driven and can be used as general purpose I/O pin. The VERIFY bit is available when the
SPI is configured as either S-BUS or I2CBUS. At
the start of a byte transmission, the verify bit is set
to one. If at any time during the transmission of the
following eight bits, the data on the SDA line does
not match the data forced by the SPI (while SCL is
high), then the VERIFY bit is reset. The verify is
available only during transmission for the S-BUS
and I2CBUS; for other protocol it is not defined.
The SDA and SCL signal entering the SPI are buffered in order to remove any minor glitches. When
STD bit is set to one (S-BUS or I2CBUS selected),
and TRX bit is reset (receiving data), and STOP bit
is set (last byte of current communication), the SPI
interface does not generate the Acknowledge, according to S-BUS/I2CBUS specifications. PCOSCL, PC1-SDA and PC3-SEN lines are standard
drive I/O port pins with open-drain output configuration (maximum voltage that can be applied to these
pins is VDD+ 0.3V).
S-BUS/I2CBUS Protocol Information
The S-BUS is a three-wire bidirectional data-bus
with functional features similar to the I2CBUS. In
fact the S-BUS includes decoding of Start/Stop
conditions and the arbitration procedure in case of
multimaster system configuration (the ST631xx
SPI allows a single-master only operation). The
SDA line, in the I2CBUS represents the AND combination of SDA and SEN lines in the S-BUS. If the
SDA and the SEN lines are short-circuit connected, they appear as the SDA line of the
I2CBUS. The Start/Stop conditions are detected (by
the external peripherals suited to work with SBUS/I2CBUS) in the following way:
S-BUS by a transition of the SEN line (1 to 0
- On
Start, 0 to 1 Stop) while the SCL line is at high
level.
I2CBUS by a transition of the SDA line (10
- On
Start, 01Stop) while the SCL line is at high
level.
Start and Stop condition are always generated by
the master (ST631xx SPI can only work as single
master). The bus is busy after the start condition and
can be considered again free only when a certain
time delay is left after the stop condition. In the SBUS configuration the SDA line is only allowed to
change during the time SCL line is low. After the start
information the SEN line returns to high level and remains unchangedfor all the data transmission time.
When the transmission is completed the SDA line is
set to high level and, at the same time, the SEN line
returns to the low level in order to supply the stop information with a low to high transition, while the SCL
line is at high level. On the S-BUS, as on the I2CBUS,
each eight bit information (byte) is followed by one
acknowledged bit which is a high level put on the
SDA line by the transmitter. A peripheral that acknowledges has to pull down the SDA line during the
acknowledge clock pulse. An addressed receiver
has to generate an acknowledge after the reception
of each byte; otherwise the SDA line remains at the
high level during the ninth clock pulse time. In this
case the master transmitter can generate the Stop
condition, via the SEN (or SDA in I2CBUS) line, in
order to abort the transfer.
33/82

ST63140,142,126,156
SERIAL PERIPHERAL INTERFACE (Continued)
Start/Stop Acknowledge. The timing specs of the
S-BUS protocol require that data on the SDA (only
on this line for I2CBUS) and SEN lines be stable
during the “high” time of SCL. Two exceptions to
this rule are foreseen and they are used to signal
the start and stop condition of data transfer.
S-BUS by a transition of the SEN line (10
- On
Start, 01 Stop) while the SCL line is at high
level.
I2CBUS by a transition of the SDA line (10
- On
Start, 01 Stop) while the SCL line is at high
level.
Data are transmitted in 8-bit groups; after each
group, a ninth bit is interposed, with the purpose of
acknowledging the transmitting sequence (the
transmit device place a “1” on the bus, the acknowledging receiver a “0”).
Interface Protocol. This paragraph deals with the
description of data protocol structure. The interface protocol includes:
- A start condition
- A “slave chip address” byte, transmitted by the
master, containing two different information:
a. the code identifying the device the master
wants to address (this information is present in
the first seven bits)
b. the direction of transmission on the bus (this
information is given in the 8th bit of the byte);
“0” means “Write”, that is from the master to
the slave, while “1” means “Read”. The addressed slave must always acknowledge.
34/82

The sequence from, now on, is different according
to the value of R/W bit.
1. R/W = “0” (Write)
In all the following bytes the master acts as transmitter; the sequence follows with:
a. an optional data byte to address (if needed) the
slave location to be written (it can be a word address in a memory or a register address, etc.).
b. a “data” byte which will be written at the address given in the previous byte.
c. further data bytes.
d. a STOP condition
A data transfer is always terminated by a stop condition generated from the master. The ST631xx
peripheral must finish with a stop condition before
another start is given. Figure 44 shows an example
of write operation.
2. R/W = “1” (Read)
In this case the slave acts as transmitter and,
therefore, the transmission direction is changed. In
read mode two different conditions can be considered:
a. The master reads slave immediately after first
byte. In this case after the slave address sent
from the master with read condition enabled
the master transmitter becomes master receiver and the slave receiver becomes slave
transmitter.
b. The master reads a specified register or location of the slave. In this case the first sent byte
will contain the slave address with write condition enabled, then the second byte will specify
the address of the register to be read. At this
moment a new start is given together with the
slave address in read mode and the procedure
will proceed as described in previous point “a”.
ST63140,142,126,156
SERIAL PERIPHERAL INTERFACE (Continued)
Figure 39.Master Transmit to Slave Receiver (Write Mode)
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
MSB
S
SLAVE ADDRESS
0
A
WORD ADDRESS
A
DATA
A
STOP
R/W
START
P
Figure 40.Master Reads Slave Immediately After First Byte (read Mode)
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM MASTER
MSB
MSB
S
SLAVE ADDRESS
1
A
DATA
A
R/W
START
NO ACKNOWLEDGE
FROM MASTER
DATA
1
n BYTES
P
STOP
Figure 41.Master Reads After Setting Slave Register Address (Write Address, Read Data)
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
S
SLAVE ADDRESS
0
A
X
WORD ADDRESS
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM MASTER
START
1
NO ACKNOWLEDGE
FROM MASTER
MSB
MSB
SLAVE ADDRESS
P
STOP
R/W
START
S
A
A
DATA
R/W
A
DATA
1
P
STOP
35/82

ST63140,142,126,156
SERIAL PERIPHERAL INTERFACE (Continued)
S-BUS/I2CBUS Timing Diagrams
The clock of the S-BUS/I2CBUS of the ST631xx
SPI (single master only) has a fixed bus clock frequency of 62.5kHz. All the devices connected to
the bus must be able to follow transfers with
Figure 42. S-BUS Timing Diagram
36/82

frequencies up to 62.5kHz, either by being able to
transmit or receive at that speed or by applying the
clock synchronization procedure which will force
the master into a wait state and stretch low periods.
ST63140,142,126,156
SERIAL PERIPHERAL INTERFACE (Continued)
Figure 43. I2C BUS Timing Diagram
2
Note: The third pin, SEN, should be high; it is not used in the I CBUS. Logically SDA is the AND of the S-BUS SDA and SEN.
37/82

ST63140,142,126,156
SERIAL PERIPHERAL INTERFACE (Continued)
Compatibility S-BUS/I2CBUS
Using the S-BUS protocol it is possible to implement mixed system including S-BUS/I2CBUS bus
peripherals. In order to have the compatibility with
the I2CBUS peripherals, the devices including the
S-BUS interface must have their SDA and SEN
pins connected together as shown in the following
Figure 44 (a and b). It is also possible to use mixed
S-BUS/I2CBUS protocols as showed in Figure 48
(c). S-BUS peripherals will only react to S-BUS
protocol signals, while I2CBUS peripherals will
only react to I2CBUS signals. Multimaster configuration is not possible with the ST631xx SPI (single
master only).
Figure 44.S-BUS/I2C BUS Mixed Configurations
(a)
(c)
38/82

(b)
ST63140,142,126,156
SERIAL PERIPHERAL INTERFACE (Continued)
Figure 45.STD Bus (Hardware Bus Disabled) Timing Diagram
STD SPI Protocol (Shift Register)
This protocol is similar to the I2CBUS with the exception that there is no acknowledge pulse and
there are no stop or start bits. The clock cannot be
slowed down by the externalperipherals.
The I/O ports associated with the SPI should be
programmed as outputs with data high in order not
to inhibit the functionality of the hardware SPI.
SPI APPLICATION NOTES
Stop Clock Slowdown: In the ST631xx family of
devices when operating in the I2C or SBUS modes,
there is no internal clock slowdown for the final
STOP clock. Slowdown means that if an external
peripheral requires extra time it will hold the
ST631xx SCL clock low. To be fully I2C and SBUS
compatible in this respect, the SW should check
that the SCL line is indeed high beforeproceeding
with the START of another I2C or SBUS transmission. In all other cases the SCL clock slowdown
feature is operational.
SPI Standard Bus Protocol: The standard bus
protocol is selected by loading the SPI Control
Register 1 (SCR1 Add. EBh). Bit 0 named I2C must
be set at one and bit 1 named STD mut be reset.
When the standard bus protocol is selected bit 2 of
the SCR1 is meaningless.
This bit named STOP bit is used only in I2CBUS or
SBUS. However take care thet THE STOP BIT
MUST BE RESET WHEN THE STANDARD PROTOCOL IS USED. This bit is set to ZERO after RESET.
39/82

ST63140,142,126,156
14-BIT VOLTAGE SYNTHESIS TUNING
PERIPHERAL
The ST631xx on-chip voltage synthesis tuning peripheral has been integrated to allow the generation of tuning reference voltage in low/mid end TV
set applications. The peripheral is composed of a
14-bit counter that allows the conversion of the
digital content in a tuning voltage, available at the
VS output pin, by using Pulse Width Modification
(PWM), and Bit Rate Multiplier (BRM) techniques.
The 14-bit counter gives 16384 steps which allows
a resolution of approximately 2mV over a tuning
voltage of 32V; this corresponds to a tuning resolution of about 40kHz per step in the UHF band (the
actual value will depend on the characteristics of
the tuner).
The tuning word consists of a 14-bit word contained in the registers VSDATA1 (location 0EDh)
and VSDATA2 (location 0EEh). Coarse tuning
(PWM) is performed using the seven MSBits, while
fine tuning (BRM) is performed using the data in
the seven LSBits. With all zeros loaded the output
is zero; as the tuning voltage increases from all zeros, the number of pulses in one period increas to
128 with all pulses being the same width. For values larger than 128, the PWM takes over and the
number of pulses in one period remains constant
at 128, but the width changes. At the other end of
the scale, when almost all ones are loaded, the
pulses will start to link together and the number of
pulses will decrease. When all ones are loaded,
the output will be almost 100% high but will have a
low pulse (1/16384 of the high pulse).
Output Details
Inside the on-chip Voltage Synthesis are included
the register latches, a reference counter, PWM and
BRM control circuitry. In the ST631xx the clock for
the 14-bit reference counter is 2MHz derived from
the 8MHz system clock. From the circuit point of
view, the seven most significant bits control the
coarse tuning, while the seven least significant bits
control the fine tuning. From the application and
software point of view, the 14 bits can be considered as one binary number.
As already mentioned the coarse tuning consists of
a PWM signal with 128 steps; we can consider the
fine tuning to cover 128 coarse tuning cycles. The
addition of pulses is described in the following Table.
Table 11. Fine Tuning Pulse Addition
Fine Tuning
(7 LSB)
N° of Pulses added at
the following cycles
(0...127)
0000001
64
0000010
32, 96
0000100
16, 48, 80, 112
0001000
8, 24, ....104, 120
0010000
4, 12, ....116, 124
0100000
2, 6, .....122, 126
1000000
1, 3, .....125, 127
The VS output pin has a standard drive push-pull
output configuration.
VS Tuning Cell Registers
Figure 46. Voltage Synthesis Data Register 1
VSDR1
Voltage Synthesis Data Register 1
(EDh, Write only)
D7 D6 D5 D4 D3 D2 D1 D0
VS Data Bits (LSB)
D7-D0. These are the 8 least significant VS data
bits. Bit 0 is the LSB. This register is undefined on
reset.
Figure 47. Voltage Synthesis Data Register 2
VSDR2
Voltage Synthesis Data Register 2
(EEh, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
VS Data Bits (LSB)
Unuse d
D7-D6. These bits are not used.
D5-D0. These are the 6 most significant VS data
bits. Bit 5 is the MSB. This register is undefined on
reset.
40/82

ST63140,142,126,156
6-BIT PWM D/A CONVERTER AND 62.5 kHz
OUTPUT FUNCTION
The D/A macrocell contains four PWM D/A outputs
(31.25kHz repetition, DA0-DA3) with six bit resolution plus a 62.5kHz open-drain output pin (OUT1)
specially suited for multistandard chroma processors driving. Both the D/A and OUT1 functions can
be disabled by software allowing the DA0-DA3 and
OUT1 pins to be used as general purpose opendrain output pins able to withstand signals with up
to 12V amplitude.
6-Bit D/A Converters
Each D/A converter of ST631xx is composed by
the following main blocks:
- pre-divider
- 6-bit counter
- data latches and compare circuits
The pre-divider uses the clock input frequency
(8MHz) and its output clocks the 6-bit free-running
counter. The data latched in the four registers
(E0h, E1h, E2h and E3h) control the four D/A outputs (DA0,1,2 and 3). When all zeros are loaded
the relevant output is an high logic level; all 1’s correspond to a pulse with a 1/64 duty cycle and almost 100% zero level. A 7th bit (bit D6) is used to
enable the relevant D/A output; when zero, the D/A
is no longer enabled and it forces the output to
zero. If the other six bits are all zero then the output
is controlled only by the enable bit.
The repetition frequency is 32.5kHz and is related
to the 8MHz clock frequency. All D/A outputs are
open-drain with standard current drive capability
and able to withstand up to 12V.
Figure 48. 6-bit PWM D/A & 62.5kHz Output
Configuration
62.5 kHz Output
This pin provides a 62.5 kHz signal with a 50% duty
cycle; the output is enabled by a dedicated enable
bit (E0h register bit 7). When the 62.5kHz frequency is disabled then the output is controlled by
the OUT1 bit and the line can be used as general
purpose open-drain output (E1h bit 7). The OUT1
output is open-drain with standard current drive capability and able to withstand signals with up to
12V amplitude.
D/A and OUT1 Data/Control Registers
This paragraph deals with the description of D/A
and OUT1 data/control registers. Some bits of DA2
and DA3 data/control registers are used for external interrupt enable and A/D reference voltage
shift, please refer to A/D and IR descriptions for additional information.
Figure 49. DA0 Data/Enable Register
DA0
DA0 Data/Contr ol Registers
(E0h, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
DAE D/A Enable Bit
FO1 62.5 kHzSelection Bit
DA0-DA5. These are the 6 bits of the PWM digital
to analog converter . Undefined after reset.
DAE. This is the D/A 0 enablebit. If zero, the output of
the D/A is forced to zero; if one, the output of the D/A
dependson bits DA0..DA5. Undefinedafter reset.
FO1. This is the 62.5kHz frequency output/ OUT1
selection bit. If one, the OUT1 pin will give a
62.5kHz frequency; if zero the OUT1 pin can be
used as general purpose open-drain output and
the value present on the pin depends on the value
of OUT1 bit programmed in the DA1 data/control
register. Undefined after reset.
41/82

ST63140,142,126,156
6-BIT PWM D/A CONVERTERS AND 62.5 kHz
OUTPUT FUNCTION (Continued)
Figure 50. DA1 Data/Enable Register
DA1
DA1 Data/Control Registers
(E1h, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
DAE D/A Enable Bit
OUT1 Data Bit
DA0-DA5. These are the 6 bits of the PWM digital
to analog converter. Undefined after reset.
DAE. This is the D/A 1 enable bit. If zero, the output of the D/A is forced to zero; if one, the output of
the D/A depends on bits DA0..DA5. Undefined after reset.
OUT1. This is the OUT1 data bit. The content of
this bit is output on the OUT1 pin when the 62.5kHz
frequency function is disabled (FO1 bit in DA0 register is cleared to zero). Undefined after reset.
Figure 51. DA2 Data/Enable Register
DA2
DA2 Data/Control Registers
(E2h Write Only)
DA0-DA5. These are the 6 bits of the PWM digital
to analog converter bits. Undefined after reset.
DAE. This is the D/A 2 enable bit. If zero, the output of the D/A is forced to zero; if one, the output of
the D/A depends on bits DA0..DA5. Undefined after reset.
IEN. This is the external interrupt enable. If set to
one, the interrupt coming from the external interrupt pin is enabled, if this bit is cleared the interrupt
is disabled. Undefined after reset. This interrupt is
associated to the NMI interrupt vector. Refer to IR
and interrupt descriptions for additional information.
Figure 52. DA3 Data/Enable Register
DA3
DA3 Data/Contr ol Registers
(E3h, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
DAE D/A Enable Bit
ADSH A/D ReferenceShift
DA0-DA5. These are the 6 bits of the PWM digital
to analog converter. Undefined after reset.
DAE. This is the D/A 3 enable bit. If zero, the output of the D/A is forced to zero; if one, the output of
the D/A depends on bits DA0..DA5. Undefined after reset.
ADSH. This is the analog to digital converter reference voltage shift bit. If set to one, the AFC block
has reference voltages on 1V border. If set to zero,
on 0.5V border. Undefined after reset. Refer to
AFC for additional information.
D7 D6 D5 D4 D3 D2 D1 D0
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
DAE D/A Enable Bit
IEN IR Interrupt Enable
42/82

ST63140,142,126,156
AFC A/D INPUT, KEYBOARD INPUTS
AND BANDSWITH OUTPUTS
The AFC macrocell contains an A/D comparator
with five levels at intervals of 1V from 1V to 5V. The
levels can all be lowered by 0.5V to effectively double the resolution. This A/D can be used to perform
the AFC function. In addition this cell offers also a
keyboard input register of three bits used to perform a keyboard scan and 4 open-drain outputs
(able to withstand signals up to 12V) that can be
used to perform band switch function.
Figure 54. BSW, DA, OUT1 Output Configuration Diagram
Figure 53. AFC, KBY Inputs Configuration Diagrams
A/D Comparator
The A/D used to perform the AFC function (when
high threshold is selected) has the following voltage levels: 1,2,3,4 and 5V. Bits 0-2 of AFC result
register (E4h address) will provide the result in binary form (less than 1V is 000, greater than 5V is
101).
If the application requires a greater resolution, the
sensitivity can be doubled by clearing to zero bit 7 of
DA3 Data/Control register, address E3h (refer to
D/A description for additional information). In this
case all levels are shifted lower by 0.5V. If the two
results are now added within a software routine
then the A/D S-curve can be located within a resolution of 0.5V. The A/D input has high impedance able
to withstand up to 13V signals (input level tolerances ± 200mv absolute and ± 100mv relative to
5V).
AFC, Keyboard Inputs and Bandswitch Outputs Data/Control Registers
Figure 55. AFC Result Register
AFCR
AFC Result Register
(E4h, Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
AD2-AD0 A/D = Conversion
Result
Unuse d
D7-D3. These bits are not used.
AD0-AD2. These bits store the real time conversion of the value present on the AFC input pin. No
reset value.
43/82

ST63140,142,126,156
AFC A/D INPUT, KEYBOARD INPUTS
AND BANDSWITH OUTPUTS (Continued)
INFRARED INPUT (IRIN)
The IRIN pin is directly connected to the NMI interrupt and acts as external interrupt pin (refer to interrupt description for additional information).
The enable/disable of this interrupt can be managed with the write only IEN bit available in the
DA2 Data/Control Register (Address E2h, bit D7).
When this bit is set to one the interrupt is enabled
otherwise it is disabled.
The IRIN pin is RISING EDGE sensitive.
Figure 56. Keyboard Input Register
KBYREG
Keyboard Input Register
(E5h, Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
KBY0 Input Data Bit
KBY1 Input Data Bit
KBY2 Input Data Bit
Unused
D7-D3. These bits are not used.
KBY0-KBY2. These bits store the logic level present at KBY0, KBY1 and KBY2 input pins. No reset
value. This input pins have CMOS levels with onchip pull-up resistor (100kΩ typical).
Figure 57. Bandswitch Output Register
BSWREG
Bandswitch Output Register
(E9h, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
BSW0 Output
BSW1 Output
BSW2 Output
Unused
BSW3 Output
Bit
Bit
Bit
Bit
D6-D3. These bits are not used.
BSW0-BSW2,BSW3. The writing into these bits
will cause the corresponding BSW open-drain output line to switch to the programmed level. Undefined after reset.
44/82

Application Note
When the IR interrupt is enabled, then a rising
edge on the IR pin will generate an interrupt; if the
IR interrupt is disabled, no IR interrupts can occur.
Care should be taken because if the IR pin is high
when the IR interrupt is enabled, an interrupt will
also be generated; the following method to eliminate noise can also be used if the SW engineer
wishes to enable/disable the IR interrupt.
If a Low-cost infra-red receiver is used, the cusstomer may wish to test the IR signal by software
after an interrupt in order to verify that there is a
good pulse and not just noise. The IRIN pin cannot
be read, so in this case it should be connected in
parallel with another pin so the signal can be read.
Furthermore the IRIN pin is sensitive to a rising
edge interrupt; this means that the input to the pin
should be low in the presence of no infra-red signal, but since most infra-red receiver modules give
a high signal, the signal will need to be inverted
with a transistor.
ST63140,142,126,156
ON-SCREEN DISPLAY (OSD)
The ST631xx OSD macrocell is a CMOS LSI character generator which enable display of characters
and symbols on the TV screen. The character
rounding function enhances the readability of the
characters. The ST631xx OSD receives horizontal
and vertical synchronization signal and outputs
screen information via R, G, B and blanking pins.
The main characteristics of the macrocell are listed
below:
of display characters: 5 lines by 15
- Number
columns.
of character types: 128 characters in
- Number
two banks of 64 characters. Only one bank
per screen can be used.
size: Four character heights (18h,
- Character
36h 54h, 72h), two heights are available per
screen, programmable by line.
format: 6x9 dots with character
- Character
rounding function.
colour: Eight colours available pro- Character
grammable by word.
position: 64 horizontal positions by
- Display
2/fosc and 63 vertical positions by 4 h
- Word spacing: 64 positions programmable
from 2/fosc to 128/fosc.
spacing: 63 positions programmable from
- Line
4 to 252 h.
- Background: No background, square background or fringe background programmable by
word.
colour: Two of eight colours avail- Background
able programmable by word.
output: Three character data output
- Display
terminals (R,G,B) and a blank output terminal.
- Display on/off: Display data may be programmed on or off by word or entire screen.
The entire screen may be blanked.
Format Specification
The entire display can be turned on or off through
the use of the global enable bit or the display may
be selectively turned on or off by word. To turn off
the entire display, the global enable bit (GE) should
be zero. If the global enable is one, the display is
controlled by the word enable bits (WE). Theglobal
enable bit is located in the global enable register
and the word enable bit is located in the space
character preceding the word.
Each line must begin with a format character which
describes the format of that line and of the first
word. This character is not displayed.
A space character defines the format of subsequent words. A space character is denoted by a
one in bit 6 in the display RAM. If bit 6 of the display
RAM is a zero, the other six bits define one of the
64 display characters.
The colour, background and enable can be programmed by word. This information is encoded in
the space character between words or in the format character at the beginning of each line. Five
bits define the colour and background of the following word, and determine whether it will be displayed or not.
Characters are stored in a 6 x 9 dot format. One dot
is defined vertically as 2h (horizontal lines) and
horizontally as 2/fosc if the smallest character size
is enabled. There is no space between characters
or lines if the vertical space enable (VSE) and horizontal space enable (HSE) bits are both zero. This
allows the use of special graphics characters.
The normal alphanumeric character set is formatted to be 5 x 7 with one empty row at the top and
one at the bottom and one empty column at the
right. If VSE and HSE are both zero, then the spacing between alphanumeric characters is 1 dot and
the spacing between lines ofalphanumeric characters is 2h.
The character size is programmed by line through
the use of the size bit (S) in the format character
and the global size bits (GS1 and GS2). The vertical spacing enable bit (VSE) located in the format
character controls the spacing between lines. If
this bit is set to one, the spacing between lines is
defined by the vertical spacing register, otherwise
the spacing between lines is 0.
The spacing between words is controlled by the
horizontal space enable bit (HSE) located in the
space character. If this bit is set to one, the spacing
between words is defined by the horizontal spacing
register, otherwise the space character width of 6
dots is the spacing between words.
The formats for the display character, space
character and format character are described
hereafter.
45/82

ST63140,142,126,156
ON-SCREEN DISPLAY (Continued)
Figure 58. Space Character Register
Explanation
Space Character Format
See Data RAM Table Description
for Specific Address
( Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
HSE = Horizontal SpaceEnab le
WE = Word Enable Bit
BGS = Backround Select
B = B Colour Bit
G = G Colour Bit
R = R Colour Bit
Fixed to “1”
Unused
D7. Not used.
D6. This pin is fixed to “1”.
R, G, B. Colour. The 3 colour control bits define the
colour of the following word as shown in table below.
Space Character Register Colour Setting.
R
G
B
Colour
0
0
0
Black
0
0
1
Blue
0
1
0
Green
0
1
1
Cyan
1
0
0
Red
1
0
1
Magenta
1
1
0
Yellow
1
1
1
White
WE. Word Enable. The word enable bit defines
whether or not the following word is displayed.
“0” -The word is not displayed.
“1” -If the global enable bit is one, then the word is
displayed.
HSE. Horizontal Space Enable. The horizontal
space enable bit determines the spacing between
words. The space between characters is always 0.
The alphanumeric character set is implemented in
a 5 x 7 format with one empty column to the right
and one empty row above and below so that the
space between alphanumeric characters will be
one dot.
“0” -The space between words is equal to the width
of the space character, which is 6 dots.
“1” -The space between words is defined by the
value in the horizontal space register plus the
width of the space character.
Figure 59. Format Character Register
Explanation
Format Character
See Data RAM Table Description
for Specific Address
( Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
VSE = Vertical Space Enable
WE = Word Enable Bit
BGS = Backround Select
B = B Colour Bit
G = G Colour Bit
R = R Colour Bit
S = Character Size Control Bit
Unuse d
BGS. Background Select. The background select
bit selects the desired background for thefollowing
word. There are two possible backgrounds defined
by the bits in the Background Control Register.
“0” -The background on the following word is enabled by BG0 and the colour is set by R0, G0,
and B0.
“1” -The background on the following word is enabled by BG1 and the colour is set by R1, G1,
and B1.
46/82

D7. This bit is not used
S. Character Size. The character size bit, along
with the global size bits (GS2 and GS1) located in
the horizontal space register, specify the character
size for each line as defined in Table 14.
R, G, B. Colour. The 3 colour control bits define the
colour of the following word as shown in Table 13.
BGS. Background Select. The background select
bit selects the desired background for thefollowing
word. There are two possible backgrounds defined
by the bits in the Background Control Register.
“0” -The background on the following word is enabled by BG0 and the colour is set by R0, G0,
and B0.
ST63140,142,126,156
ON-SCREEN DISPLAY (Continued)
“1” -The background on the following word is enabled by BG1 and the colour is set by R1, G1,
and B1.
WE. Word Enable. The word enable bit defines
whether or not the following word is displayed.
“0” -The word is not displayed.
“1” -If the global enable bit is one, then the word is
displayed.
VSE. Vertical Space Enable. The vertical space
enable bit determines the spacing between lines.
“0” -The space between lines is equal to 0h. The alphanumeric character set is implemented in a
5 x 7 format with one empty column to the right
and one empty row above and one below and
stored in a 6 x 9 format.
“1” -The space between lines is defined by the
value in the vertical space register.
Table 13. Format Character Register Colour
Setting.
R
G
B
Colour
0
0
0
Black
0
0
1
Blue
0
1
0
Green
0
1
1
Cyan
1
0
0
Red
1
0
1
Magenta
1
1
0
Yellow
1
1
1
White
Table 14. Format Character Register Size
Setting
GS2 GS1
S
Vertical Height
Horizontal length
0
0
0
18h
6 TDOT
0
0
1
36h
12 TDOT
0
1
0
18h
6 TDOT
0
1
1
54h
18 TDOT
1
0
0
36h
12 TDOT
1
0
1
54h
18 TDOT
1
1
0
36h
12 TDOT
1
1
1
72h
24 TDOT
Figure 60. Display Character Register
Explanation
Display Character
See Data RAM Table Description
for specific Addresses
( Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
C5-C0 = Character Types
control Bit
Fixed to “0”
Unuse d
D7. This bit is not used.
D6. This bit is fixed to “0”.
C5-C0. Character type. The 6 character type bits
define one of the 64 available character types.
These character types are shown on the following
pages.
Character Types
The character set is user defined as ROM mask
option.
Register and RAM Addressing
The OSD contains seven registers and 80 RAM locations. The seven registers are the Vertical Start
Address register, Horizontal Start Address register, Vertical Space register, Horizontal Space register, Background Control register, Global Enable
register and Character Bank Select register. The
Global Enable register can be written at any time
by the ST631xx Core. The other six registers and
the RAM can only be read or written to if the global
enable is zero.
The six registers and the RAM are located on two
pages of the paged memory of the ST631xx
MCUs; the Character Bank Select register is located outside the paged memory at address EDh.
Each page contains 64 memory locations. This
paged memory is at memory locations 00h to 3Fh
in the ST631xx memory map. A page of memory is
enabled by setting the desired page bit, located in
the Data Ram Bank Register, to a one. The page
register is location E8h. A one in bit five selects
page 5, located on the OSD and a one in bit 6 selects page 6 on the OSD. Table 15 shows the addresses of the OSD registers and RAM.
TDOT= 2/fosc
47/82

ST63140,142,126,156
ON-SCREEN DISPLAY (Continued)
Table 15. OSD Control Registers and Data
RAM Addressing
Figure 62. Vertical Start Address Register
Page
Address
Register or RAM
VSAR
5
00h - 3Fh
RAM Locations 00h - 3Fh
Vertical Start Address Register
(10h - Page 6, Write Only)
6
00h - 0Fh
RAM Locations 00h - 0Fh
6
10h
Vertical Start Register
6
11h
Horizontal Start Register
6
12h
Vertical Space Register
6
13h
Horizontal Space Register
6
14h
Background Control Register
6
17h
Global Enable Register
No
Page
EDh
Character Bank Select Register
D7 D6 D5 D4 D3 D2 D1 D0
OSD Global Enable Register
This register contains the global enable bit (GE). It
is the only register that can be written at any time
regardless of the state of the GE bit. It is a write
only register.
Figure 61. Global Enable Bit
Global Enable
Register
17h - Page 6
( Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
GE = Global Enable Bit
Unused
D7-D1. These bits are not used
GE. Global Enable. This bit allows the entire display to be turned off.
“0” - The entire display is disabled. The RAM and
other registers of the OSD can be accessed by
the Core.
“1” - Display of words is controlled by the word enable bits (WE) located in the format or space character. The other registers and RAM cannot be
accessed by the Core.
48/82

VSA5-VSA0 = Vertical Start
Address bits
FR = Fringe Backround
Control bit
Unuse d
D7. This bit is not used
FR. Fringe Background.This bit changes the background from a box background to a fringe background. The background is enabled by word as
defined by either BG0 or BG1.
“0” - The background is defined to be a box which
is 7 x 9 dots.
“1” - The background is defined to be a fringe.
VSA5-VSA0. Vertical Start Address. These bits
determine the start position of the first line in the
vertical direction. The 6 bits can specify 63 display
start positions of interval 4h. The first start position
will be the fourth line of the display. The vertical
start address is defined VSA0 by the following formula.
Vertical Start Address = 4h(25(VSA5) + 24(VSA4) +
23(VSA3) + 22(VSA2) + 21(VSA1) + 20(VSA0))
The case of all Vertical Start Address bits being
zero is illegal.
ST63140,142,126,156
ON-SCREEN DISPLAY (Continued)
Figure 63. Horizontal Start Address Register
Figure 64. Vertical Space Register
HSAR
VSR
Horizontal Start Address Register
(11h - Page 6, Write Only)
Vertical Space Register
(12h - Page 6, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
HSA5-HSA0 = Horizontal Start
Address bits
SBD = Space Blanking
Disabled bit
Unused
D7. This bit is not used.
SBD. Space Blanking Disable. This bit controls
whether or not the background is displayed when
outputting spaces. If two background colours are
used on adjacent words, then the background
should not be displayed on spaces in order to
make a nice break between colours. If an even
background around an area of text is desired, as in
a menu, then the background should be displayed
when outputting spaces.
“0” -The background during spaces is controlled by
the background enable bits (BG0 and BG1) located in the Background Control register.
“1” -The background is not displayed when outputting spaces.
HSA5, HSA0 - Horizontal Start Address bits.
These bits determine the start position of the first
character in the horizontal direction. The 6 bits can
specify 64 display start positions of interval 2/fosc or
400ns. The first start position will be at 4.0µs because of the time needed to access RAM and
ROM before the first character can be displayed.
The horizontal start address is defined by the following formula.
Horizontal Start Address = 2/fosc(10.0 + 25(HSA5)
+ 24(HSA4) + 23(HSA3) + 22(HSA2) + 21(HSA1) +
20(HSA0))
VS5-VS0 = Vertical Space
SCB = Screen Blanking bit
Unuse d
D7. This bit is not used
SCB. Screen Blanking. This bit allows the entire
screen to be blanked.
“0” -The blanking output signal (VBLK) is active
only when displaying characters.
“1” -The blanking output signal (VBLK) is always
active. Characters in the display RAM are still
displayed.
When this bit is set to one, the screen is blanked
also without setting the Global Enable bit to one
(OSD disabled).
VS5 , VS0. Vertical Space. These bits determine
the spacing between lines if the Vertical Space Enable bit (VSE) in the format character is one. If VSE
is zero there will be no spaces between lines. The
Vertical Space bits can specify one of 63 spacing
values from 4h to 252h. The space between lines
is defined by the following formula.
Space between lines = 4h(25(VS5) + 24(VS4) +
23(VS3) + 22(VS2) + 21(VS1) + 20(VS0))
The case of all Vertical Start Address bits being
zero is illegal.
49/82

ST63140,142,126,156
ON-SCREEN DISPLAY (Continued)
Background Control Register
This register sets up two possible backgrounds.
The background select bit (BGS) in the format or
space character will determine which background
is selected for the current word.
Figure 65. Horizontal Space Register
HSR
Horizontal Space Register
(13h - Page 6, Write Only)
Figure 66. Background Control Register
D7 D6 D5 D4 D3 D2 D1 D0
BCR
HS5-HS0 = Horizontal Space
GS1 = Global Size Bit 1
Backround Control Register
(14h - Page 6, Write Only)
GS2 = Global Size Bit 2
D7 D6 D5 D4 D3 D2 D1 D0
BK0 = Backround Enable Bit 0
BK1 = Backround Enable Bit 1
B0 = B Colour Backround Bit 0
B1 = B Colour Backround Bit 1
G0 = G Colour Backround Bit 0
G1 = G Colour Backround Bit 1
R0 = R Colour Backround Bit 0
R1 = R Colour Backround Bit 1
GS2,GS1. Global Size. These bits along with the
size bit (S) located in the Character format word
specify the character size for each line as defined
in Table 16.
Table 16. Horizontal Space Register Size
Setting.
GS2 GS1
S
Vertical Height
Horizontal
Length
R1,R0,G1,G0,B1,B0. Background Colour.
These bits define the colour of the specified background, either background 1 or background 0 as
defined in Table 17.
0
0
0
18h
6 TDOT
0
0
1
36h
12 TDOT
0
1
0
18h
6 TDOT
0
1
1
54h
18 TDOT
1
0
0
36h
12 TDOT
RX
GX
BX
Colour
1
0
1
54h
18 TDOT
0
0
0
Black
1
1
0
36h
12 TDOT
0
0
1
Blue
1
1
1
72h
24 TDOT
0
1
0
Green
0
1
1
Cyan
1
0
0
Red
1
0
1
Magenta
1
1
0
Yellow
1
1
1
White
Table 17. Background Register Colour
Setting.
Note: TDOT= 2/fOSC
HS5, HS0 . Horizontal Space . These bits determine the spacing between words if the Horizontal
Space Enable bit (HSE) located in the space character is a one. The space between words is then equal
to the width of the space character plus the number
of tdots specified by the HorizontalSpace bits. The 6
bits can specify one of 64 spacing values ranging
from 2/fosc to 128/fosc. The formula is shown below
for the smallest size character(18h). If larger size
characters are being displayed the spacing between
words will increase proportionately. Multiply the
value below by 2, 3 or 4 for character sizes of 36h,
54h and 72h respectively.
Space between words (not including the space
character)=2/fosc(1+25(HS5)+24(HS4)+23(HS3)
+22(HS2)+ 21(HS1)+20(HS0))
50/82

ST63140,142,126,156
ON-SCREEN DISPLAY (Continued)
Figure 67. Character Bank Select Register
CBSR
Character Bank Select Register
(EFh - No Page , Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
BS = Bank Select Bit
Unused
BK1,BK0. Background Enable.These bits determine if the specified background is enabled or not.
“0” -The following word doesnot havea background.
“1” -There is a background around the following
word.
D7-D1. These bits are not used
BS. Bank Select. This bit select the character bank
to be used. The lower bank is selected with 0. The
value can be modified only when the OSD is OFF
(GE=0). No reset value.
OSD Data RAM
The contents of the data RAM can be accessed by
the ST631xx MCUs only when the global enable bit
(GE) in the Global Enable register is a zero.
The first character in every line is the format character. This character is not displayed. It defines the
size of the characters in the line and contains the
vertical space enable bit. This character also defines the colour, background and display enable for
the first word in the line. Subsequent characters
are either spaces or one of the 64 available character types.
The space character defines the colour, background, display enable and horizontal space enable for the following word. Since there are 5
display lines of 15 characters each, the display
RAM must contain 5 lines x (15 characters + 1 format character) or 80 locations. The RAM size is 80
locations x 7 bits. The data RAM map is shown
inTable 12.
51/82

ST63140,142,126,156
ON-SCREEN DISPLAY (Continued)
Table 12. OSD RAM Map
Column
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Page
A5
A4
LINE
5
0
0
1
FT
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
5
0
1
2
FT
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
5
1
0
3
FT
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
5
1
1
4
FT
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
6
0
0
5
FT
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
Ch
AVAILABLE SCREEN SPACE
Notes: FT. The format character required for each line. Characters in columns 1 thru 15 are displayed.
Ch. (Byte) Character (Index into OSD character generator) or space character
Emulator Remarks
There are a few differences between emulator and
silicon. For noise reasons, the OSD oscillator pins
are not available: the internal oscillator cannot be
disabled and replaced by an external coil. In the
emulator, the Character Bank Select register can
be written also with Global Enable bit set, while this
is not allowed in the device.
Application Notes
1 - The OSD character generator is composed of a
dual port video ram and some circuitry. It needs
two input signals VSYNC and HSYNC to syncronize its dedicated oscillator to the TV picture. It generates 4 output signals, that can be used from the
TV set to generate the characters on the screen.
For instance, they can be used to feed the SCART
plug, providing an adequate buffer to drive the low
impedance (75 Ω) of the SCART inputs.
2 - The Core sees the OSD as a number of RAM
locations (80) plus a certain number of control registers (6). These 86 locations are mapped in two
pages of the dynamic data ram address range
(0h..3Fh).
In page 5 (load 20h in the register 0E8h), there are
64 bytes of RAM, the ones of the first 4 rows (16
bytes each row, 15 characters per row maximum,
52/82

plus an hidden leading formatcharacter). In page 6
(load 40h in register 0E8h), the 16 bytes of the fifth
row (0..0Fh), and the 6 control registers
(10h..14h,17h).
3 - The video RAM is a dual port ram. That means
that it can be addressed either from the Core or
from the OSD circuitry itself. To reduce the complexity of the circuitry, and thus its cost, some restrictions have been introduced in the use of the
OSD.
a. The Core can Only write to any of the 86 locations (either video RAM or control registers).
b. The Core can Only write to any of the leading
85 locations when the OSD oscillator is OFF.
Only the last location (control register 17h in
page 6) can be addressed at any time. This is
the Global Enable Register, which contains
only the GE bit. If it is set, the OSD is on, if it is
reset the OSD is off.
4 - The timing of the on/off switching of the OSD
oscillator is the following:
a. GE bit is set. The OSD oscillator will start on
the next VSYNC signal.
b. GE bit is reset. The OSD oscillator will be immediately switched off.
ST63140,142,126,156
ON-SCREEN DISPLAY (Continued)
To avoid a bad visual impression, it is important
that the GE bit is set before the end of the flyback
time when changing characters. This can be done
inside the VSYNC interrupt routine. The following
diagram can explain better:
Figure 68. OSD Oscillator ON/OFF Timing
Notes: A - Picture time: 20 mS in PAL/SECAM.
B - VSYNC interrupt, if enabled.
C - Starting of OSD oscillator, if GE = 1.
D - Flyback time.
When modifying the picture display (i.e.: a bar
graph for an analog control), it is important that the
switching on of the GE bit is done before the the
end of the flyback time (D in Figure 68). If the GE
bit is set after the end of the flyback time then the
OSD will not start until the begining of the next
frame. This results in one frame being lost and will
result in a Flicker on the screen. One method to be
sure to avoid the flicker is to wait for the VSYNC interrupt at the start of the flyback; once the VSYNC
interrupt is detected, then the GE bit can be set to
zero, the characters changed, and the GE set to
one. All this should occur before the end of the flyback time in order not to lose a frame. The correct
edge of the interrupt must be chosen.
The VSYNC pin may alternatively be sampled by
software in order to know the status; this can be
done by reading bit 4 of register E4h; this bit is inverted with respect to the VSYNC pin.
6 - An OSD end of line Bar is present in the
ST63P1xx piggyback and ST631xx ROM, EPROM
and OTP devices when using the background
mode. If this bar is present with software running in
the piggybacks then it is also present on the ROM
mask version. If the end of line bar is seen to be
eliminated by software in the piggyback, then it is
also be eliminated in the ROM mask version.
The bar appears at the end of the line in the background mode when the last character is a space
character, the first format character is defined with
S=0 (size 0)and the backround is not displayed
during the space. The bar is the colour of the background defined by the space character. To eliminate the bar:
a. If two backgrounds are used then the bar
should be moved off the screen by using large
word spaces instead of character spaces. If
there are not enough spaces before the end of
the line, then the location of the valid characters should be moved so they appear at the
end of the line (and hence no bar); positioning
can be compensated using the horizontal start
register.
b. If only one background is used, then the other
background should be transparent in order to
eliminate the bar.
7 - The OSD oscillator external network should
consist of a capacitor on each of the OSD oscillator
pins to ground together with an inductance between pins. The user should select the two capacitors to be the same value (15pF to 25pF each is
recommended). The inductance is chosen to give
the desired OSD oscillator frequency for the application (typically 56µH).
53/82

ST63140,142,126,156
SOFTWARE DESCRIPTION
The ST631xx software has been designed to fully
use the hardware in the most efficient way possible
while keeping byte usage to a minimum; in short to
provide byte efficient programming capability. The
ST631xx Core has the ability to set or clear any
register or RAM location bit of the Data space with
a single instruction. Furthermore, the program may
branch to a selected address depending on the
status of any bit of the Data space. The carry bit is
stored with the value of the bit when the SET or
RES instruction is processed.
Addressing Modes
The ST631xx Core has nine addressing modes
which are described in the following paragraphs.
The ST631xx Core uses three different address
spaces : Program space, Data space, and Stack
space. Program space contains the instructions
which are to be executed, plus the data for immediate mode instructions. Data space contains the
Accumulator, the X,Y,V and W registers, peripheral
and Input/Outputregisters, the RAM locations and
Data ROM locations (for storage of tables and
constants). Stack space contains six 12-bit RAM
cells used to stack the return addresses for subroutines and interrupts.
Immediate. In the immediate addressing mode,
the operand of the instruction follows the opcode
location. As the operand is a ROM byte, the immediate addressing mode is used to access constants
which do not change during program execution
(e.g., a constant used to initialize a loop counter).
Direct. In the direct addressing mode, the address
of the byte that is processed by the instruction is
stored in the location that follows the opcode. Direct
addressing allows the user to directly address the
256 bytes in Data Space memory with a single
two-byte instruction.
Short Direct. The Core can address the four RAM
registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in
the short-direct addressing mode. In this case, the
instruction is only one byte and the selection of the
location to be processed is contained in the opcode. Short direct addressing is a subset of the
direct addressing mode. (Note that 80h and 81h
are also indirect registers).
Extended. In the extended addressing mode, the
12-bit address needed to define the instruction is
obtained by concatenating the four less significant
bits of the opcode with the byte following the opcode. The instructions (JP, CALL) that use the
extended addressing mode are able to branch to
any address of the 4K bytes Program space.
An extended addressing mode instruction is twobyte long.
54/82

Program Counter Relative. The relative addressing mode is only used in conditional branch instructions. The instruction is used to perform a test and,
if the condition is true, a branch with a span of -15
to +16 locations around the address of the relative
instruction. If the condition is not true, the instruction that follows the relative instruction is executed.
The relative addressing mode instruction is onebyte long. The opcode is obtained in adding the
three most significant bits that characterize the kind
of the test, one bit that determines whether the
branch isa forward (when it is 0) or backward (when
it is 1) branch and the four less significant bits that
give the span of the branch (0h to Fh) that must be
added or subtracted to the address of the relative
instruction to obtain the address of the branch.
Bit Direct. In the bit direct addressing mode, the
bit to be set or cleared is part of the opcode, and
the byte following the opcode points to the address
of the byte in which the specified bit must be set or
cleared. Thus, any bit in the 256 locations of Data
space memory can be set or cleared.
Bit Test & Branch. The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The bit test and branch
instruction is three-byte long. The bit identification
and the tested condition are included in the opcode
byte. The address of the byte to be tested follows
immediately the opcode in the Program space. The
third byte is the jump displacement, which is in the
range of -126 to +129. This displacement can be
determined using a label, which is converted by the
assembler.
Indirect. In the indirect addressing mode, the byte
processed by the register-indirect instruction is at
the address pointed by the content of one of the
indirect registers, X or Y (80h,81h). The indirect
register is selected by the bit 4 of the opcode. A
register indirect instruction is one byte long.
Inherent. In the inherent addressing mode, all the
information necessary to execute the instruction is
contained in the opcode. These instructions are
one byte long.
ST63140,142,126,156
SOFTWARE DESCRIPTION (Continued)
Instruction Set
The ST631xx Core has a set of 40 basic instructions. When these instructions are combined with
nine addressing modes, 244 usable opcodes can
be obtained. They can be divided into six different
types:load/store, arithmetic/logic, conditional
branch, control instructions, jump/call, bit manipulation. The following paragraphs describe the different types.
All the instructions within a given type are presented in individual tables.
Load & Store. These instructions use one,two or
three bytes in relation with the addressing mode.
One operand is the Accumulator for LOAD and the
other operand is obtained from data memory using
one of the addressing modes.
For Load Immediate one operand can be any of the
256 data space bytes while the other is always
immediate data. See Table 13.
Table 13. Load & Store Instructions
Instruction
LD A, X
Addressing Mode
Bytes
Short Direct
1
Flags
Cycles
4
Z
C
∆
*
LD A, Y
Short Direct
1
4
∆
*
LD A, V
Short Direct
1
4
∆
*
LD A, W
Short Direct
1
4
∆
*
LD X, A
Short Direct
1
4
∆
*
LD Y, A
Short Direct
1
4
∆
*
LD V, A
Short Direct
1
4
∆
*
LD W, A
Short Direct
LD A, rr
Direct
2
1
2
4
4
∆
*
∆
*
LD rr, A
Direct
∆
*
LD A, (X)
Indirect
1
4
∆
*
LD A, (Y)
Indirect
1
4
∆
*
4
LD (X), A
Indirect
1
4
∆
*
LD (Y), A
Indirect
1
4
∆
*
LDI A, #N
Immediate
2
4
LDI rr, #N
Immediate
3
4
∆
*
*
*
Notes:
X,Y. Indirect Register Pointers, V & W Short Direct Registers
# . Immediate data (stored in ROM memory)
rr. Data space register
∆ . Affected
* . Not Affected
55/82

ST63140,142,126,156
SOFTWARE DESCRIPTION (Continued)
Arithmetic and Logic. These instructions are
used to perform the arithmetic calculations and
logic operations. In AND, ADD, CP, SUB instructions one operand is always the accumulatorwhile
the other can be either a data space memory
content or an immediate value in relation with the
addressing mode. In CLR, DEC, INC instructions
the operand can be any of the 256 data space
addresses. In COM, RLC, SLA the operand is
always the accumulator. See Table 14.
Table 14. Arithmetic & Logic Instructions
Instruction
Addressing Mode
ADD A, (X)
ADD A, (Y)
ADD A, rr
Indirect
Indirect
Direct
ADDI A, #N
Immediate
AND A, (X)
AND A, (Y)
AND A, rr
Indirect
Indirect
Direct
ANDI A, #N
Immediate
CLR A
CLR rr
Short Direct
Direct
COM A
Inherent
CP A, (X)
CP A, (Y)
CP A, rr
Indirect
Indirect
Direct
CPI A, #N
Immediate
2
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
Short Direct
Short Direct
Short Direct
Short Direct
Direct
Direct
Indirect
Indirect
1
1
1
1
INC
INC
INC
INC
INC
INC
INC
INC
X
Y
V
W
A
rr
(X)
(Y)
X
Y
V
W
A
rr
(X)
(Y)
Bytes
1
1
4
4
2
4
2
4
1
1
4
4
2
4
2
4
2
3
1
1
1
1
*
*
*
∆
*
∆
*
4
∆
∆
4
4
4
4
∆
∆
∆
∆
∆
∆
∆
∆
*
*
*
*
*
*
*
*
4
4
4
4
∆
∆
∆
∆
∆
∆
∆
∆
*
*
*
*
*
*
*
*
4
4
1
1
∆
∆
∆
∆
∆
∆
4
4
2
2
∆
∆
∆
∆
4
4
1
1
∆
∆
4
2
2
∆
∆
∆
∆
4
4
2
C
∆
∆
∆
*
4
1
1
Z
∆
4
4
1
Short Direct
Short Direct
Short Direct
Short Direct
Direct
Direct
Indirect
Indirect
Flags
Cycles
4
4
RLC A
Inherent
1
4
∆
∆
SLA A
Inherent
2
4
∆
∆
SUB A, (X)
SUB A, (Y)
SUB A, rr
Indirect
Indirect
Direct
∆
∆
∆
∆
∆
∆
SUBI A, #N
Immediate
∆
∆
1
1
4
4
2
4
2
Notes:
X,Y. Indirect Register Pointers, V & W Short Direct Registers
# . Immediate data (stored in ROM memory)
rr. Data space register
∆. Affected
* . Not Affected
56/82

4
ST63140,142,126,156
SOFTWARE DESCRIPTION (Continued)
Conditional Branch. The branch instructions
achieve a branch in the program when the selected
condition is met. See Table 15.
Bit Manipulation Instructions. These instructions can handle any bit in data space memory. One
group either sets or clears. The other group (see
Conditional Branch) performs the bit test branch
operations. See Table 16.
Control Instructions. The control instructions
control the MCU operations during program execution. See Table 17.
Jump and Call. These two instructions are used to
perform long (12-bit) jumps or subroutines call
inside the whole program space. Refer to Table 18.
Table 15. Conditional Branch Instructions
Instruction
Branch If
JRC e
JRNC e
JRZ e
JRNZ e
JRR b, rr, ee
JRS b, rr, ee
C=1
C=0
Z=1
Z=0
Bit = 0
Bit = 1
Bytes
Cycles
1
1
1
1
3
3
2
2
2
2
5
5
Notes:
b. 3-bit address
rr. Data space register
e. 5 bit signed displacement in the range -15 to +16
ee. 8 bit signed displacement in the range -126 to +129
∆
Flags
Z
C
*
*
*
*
*
*
*
*
*
*
∆
∆
. Affected
* . Not Affected
Table 16. Bit Manipulation Instructions
Instruction
Addressing
Mode
SET b,rr
RES b,rr
Bit Direct
Bit Direct
Notes:
b. 3-bit address;
rr. Data space register;
Bytes
Cycles
2
2
4
4
Bytes
Cycles
1
1
1
1
1
2
2
2
2
2
Flags
Z
C
*
*
*
*
* . Not Affected
Table 17. Control Instructions
Instruction
Addressing
Mode
NOP
RET
RETI
STOP (1)
WAIT
Inherent
Inherent
Inherent
Inherent
Inherent
Flags
Z
C
*
*
∆
*
*
*
*
∆
*
*
Notes:
1. This instruction is deactivated and a WAITis automatically executed instead of a STOP if the hardware activated
watchdog function is selected.
∆ . Affected
* . Not Affected
Table 18. Jump & Call Instructions
Instruction
Addressing
Mode
CALL abc
JP abc
Extended
Extended
Bytes
Cycles
2
2
4
4
Flags
Z
C
*
*
*
*
Notes:
abc.12-bit address;
* . Not Affected
57/82

ST63140,142,126,156
SOFTWARE DESCRIPTION (Continued)
Opcode Map Summary. The following table containsan opcode map for the instructions used on the MCU.
Low
Low
0
0000
1
0001
2
0010
3
0011
2 JRNZ
e
1
pcr
2 JRNZ
e
1
pcr
2 JRNZ
e
1
pcr
4 CALL
abc
2
ext
4 CALL
abc
2
ext
4 CALL
abc
2
ext
2 JRNC
e
1
pcr
2 JRNC
e
1
pcr
2 JRNC
e
1
pcr
5 JRR
b0 ,rr,ee
3
bt
5 JRS
b0 ,rr,ee
3
bt
5 JRR
b4 ,rr,ee
3
bt
4
010 0
5
0101
6
0110
7
0111
8
10 00
9
1001
A
1010
B
1011
2 JRNC
e
1
pcr
2 JRNC
e
1
pcr
2 JRNC
e
1
pcr
4 RES
b0 ,rr
2
b.d
4 SET
b0 ,rr
2
b.d
4 RES
b4 ,rr
2
b.d
C
1100
D
1101
E
1110
LDI
rr,nn
3 imm
4 DEC
x
1
sd
4 COM
a
1
inh
2 JRC
e
1
pcr
2 JRC
e
1
pcr
2 JRC
e
1
pcr
F
1111
Hi
0
00 00
1
00 01
2
00 10
3
0011
4
01 00
5
0101
6
0110
7
0111
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
Hi
2
1
2
1
2
1
JRZ
2 JRC
e
#
e
pcr
1
prc
JRZ 4 INC 2 JRC
e
x
e
pcr 1
sd 1
prc
JRZ
2 JRC
e
#
e
pcr
1
prc
4
LD
a,(x)
1
ind
4 LDI
a,n n
2 imm
4
CP
a,(x)
1
ind
2 JRNZ
e
1
pcr
2 JRNZ
e
1
pcr
2 JRNZ
e
1
pcr
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4
LD 2 JRC 4 CPI 2 JRNZ
e
abc
e
b4 ,rr,ee
e
a,x
e
a,nn
e
1
pcr 2
ext 1
pcr 3
bt 1
pcr 1
sd 1
prc 2 imm 1
pcr
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ
2 JRC 4 ADD 2 JRNZ
e
abc
e
b2 ,rr,ee
e
#
e
a,(x)
e
1
pcr 2
ext 1
pcr 3
bt 1
pcr
1
prc 1
ind 1
pcr
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 ADDI 2 JRNZ
e
abc
e
b2 ,rr,ee
e
y
e
a,n n
e
1
pcr 2
ext 1
pcr 3
bt 1
pcr 1
sd 1
prc 2 imm 1
pcr
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ
2 JRC 4 INC 2 JRNZ
e
abc
e
b6 ,rr,ee
e
#
e
(x)
e
1
pcr 2
ext 1
pcr 3
bt 1
pcr
1
prc 1
ind 1
pcr
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4
LD 2 JRC
2 JRNZ
e
abc
e
b6 ,rr,ee
e
a,y
e
#
e
1
pcr 2
ext 1
pcr 3
bt 1
pcr 1
sd 1
prc
1
pcr
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ
2 JRC 4
LD 2 JRNZ
e
abc
e
b1 ,rr,ee
e
#
e
(x),a
e
1
pcr 2
ext 1
pcr 3
bt 1
pcr
1
prc 1
ind 1
pcr
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC
2 JRNZ
e
abc
e
b1 ,rr,ee
e
v
e
#
e
1
pcr 2
ext 1
pcr 3
bt 1
pcr 1
sd 1
prc
1
pcr
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ
2 JRC 4 AND 2 JRNZ
e
abc
e
b5 ,rr,ee
e
#
e
a,(x)
e
1
pcr 2
ext 1
pcr 3
2 JRNZ 4 CALL 2 JRNC 5
e
1
pcr 2
abc
ext 1
e
bt 1
JRS 2
pcr
JRZ 4
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
1
prc 1
ind 1
pcr 2
LD 2 JRC 4 ANDI 2 JRNZ 4
#
1
pcr 2
ext 1
pcr 3
2 JRNZ 4 CALL 2 JRNC 5
1
prc 1
ind 1
pcr 2
INC 2 JRC 4 SUBI 2 JRNZ 4
e
pcr 2
2 JRNZ
e
1
pcr
2 JRNZ
e
1
pcr
abc
ext 1
4 CALL
abc
2
ext
4 CALL
abc
2
ext
e
2
1
2
1
2
1
JRZ
e
pcr
JRZ
e
pcr
JRZ
e
pcr
4
4
LD
a,(y)
1
ind
4
LD
a,rr
2
dir
4
CP
a,(y)
1
ind
JP 2 JRNC 4 SET 2 JRZ 4
LD 2 JRC 4
CP
abc
e
b4 ,rr
e
x,a
e
a,rr
ext 1
pcr 2 b.d. 1
JP 2 JRNC 4 RES 2
pcr 1
sd 1
pcr 2
dir
JRZ 2 RETI 2 JRC 4 ADD
abc
e
b2 ,rr
e
ext 1
pcr 2
b.d 1
pcr 1
JP
abc
ext
JP
abc
ext
JP
abc
ext
JP
abc
ext
JP
abc
ext
JP
abc
2 JRNC
e
1
pcr
2 JRNC
e
1
pcr
2 JRNC
e
1
pcr
2 JRNC
e
1
pcr
2 JRNC
e
1
pcr
2 JRNC
e
4 SET
b2 ,rr
2
b.d
4 RES
b6 ,rr
2
b.d
4 SET
b6 ,rr
2
b.d
4 RES
b1 ,rr
2
b.d
4 SET
b1 ,rr
2
b.d
4 RES
b5 ,rr
2
1
2
1
2
1
2
1
2
1
2
ext 1
pcr 2
b.d 1
JP 2 JRNC 4 SET 2
JRZ
e
pcr
JRZ
e
pcr
JRZ
e
pcr
JRZ
e
pcr
JRZ
e
pcr
JRZ
e
e
inh 1
pcr 1
a,(y)
ind
DEC 2 JRC 4 ADD
y
e
a,rr
1
sd 1
pcr 2
dir
2 STOP 2 JRC 4 INC
e
(y)
1
inh 1
pcr 1
ind
4
LD 2 JRC 4 INC
y,a
e
rr
1
sd 1
pcr 2
dir
2 JRC 4
LD
#
e
(y),a
1
pcr 1
ind
4 DEC 2 JRC 4
LD
v
e
rr,a
1
sd 1
pcr 2
dir
4 RLC 2 JRC 4 AND
a
e
a,(y)
bt 1
JRS 2
pcr
JRZ 4
pcr 1
JRZ 4
2 JRC 4 SUB 2 JRNZ 4
JP 2 JRNC 4 RES 2 JRZ 2
e
a,(x)
e
abc
e
b3 ,rr
e
ext 1
pcr 2
JP 2 JRNC 4
b.d 1
SET 2
inh 1
pcr 1
ind
LD 2 JRC 4 AND
RET 2 JRC 4 SUB
e
a,(y)
pcr 1
inh 1
pcr 1
ind
JRZ 4 DEC 2 JRC 4 SUB
b3 ,rr,ee
e
w
e
a,n n
e
abc
e
b3 ,rr
e
w
e
a,rr
pcr 3
bt 1
pcr 1
sd 1
prc 2 imm 1
pcr 2
ext 1
pcr 2
b.d 1
pcr 1
sd 1
pcr 2
dir
2 JRNC
e
1
pcr
2 JRNC
e
1
pcr
5 JRR
b7 ,rr,ee
3
bt
5 JRS
b7 ,rr,ee
3
bt
2
JRZ
e
#
1
pcr
2 JRZ 4
LD
e
a,w
1
pcr 1
sd
2 JRC 4 DEC
e
(x)
1
prc 1
ind
2 JRC
e
#
1
prc
Abbreviations for Addressing Modes:
Legend:
dir
Direct
# Indicates Illegal Instructions
sd
Short Direct
e 5 Bit Displacement
imm Immediate
b 3 Bit Address
inh
Inherent
rr1byte dataspace address
ext
Extended
nn 1 byte immediate data
b.d
Bit Direct
abc 12 bit address
bt
Bit Test
ee 8 bit Displacement
pcr
Program Counter Relative
ind
Indirect
58/82

2 JRNZ
e
1
pcr
2 JRNZ
e
1
pcr
4
JP
abc
2
ext
4
JP
abc
2
ext
2 JRNC
e
1
pcr
2 JRNC
e
1
pcr
4 RES
b7 ,rr
2
b.d
4 SET
b7 ,rr
2
b.d
2
JRZ
e
1
pcr
2 JRZ
e
1
pcr
0
0000
1
0001
2
0010
3
0011
4
0100
4
b5 ,rr,ee
e
a,v
e
a,nn
e
abc
e
b5 ,rr
e
v,a
e
a,rr
pcr 3
bt 1
pcr 1
sd 1
prc 2 imm 1
pcr 2
ext 1
pcr 2
b.d 1
pcr 1
sd 1
pcr 2
dir
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ
e
abc
e
b3 ,rr,ee
e
1
JP
abc
ext
JP
abc
ext
JP
abc
ext
2 WAIT 2 JRC
e
1
inh 1
pcr
4
LD 2 JRC
w,a
e
1
sd 1
pcr
Cycles
Operand
Bytes
Addressing Mode
2 JRC
e
1
pcr
4 DEC
(y)
1
ind
4 DEC
rr
2
dir
5
0101
6
0110
7
0111
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
Mnemonic
ST63140,142,126,156
Power Considerations. The average chip-junction temperature, Tj, in Celsius can be obtained
from :
Tj =
TA + PD x RthJA
Ambient Temperature.
Where :TA =
RthJA = Package thermal resistance
(junction-to ambient).
PD =
Pint + Pport.
Pint = IDD x VDD (chip internal power).
Pport = Port power dissipation
(determinated by the user).
ABSOLUTE MAXIMUM RATINGS
This product contains devices to protect the inputs
against damage due to high static voltages, however it is advised to take normal precaution to avoid
application of any voltage higher than maximum
rated voltages.
For proper operation it is recommended that VI and
VO must be higher than VSS and smaller than VDD.
Reliability is enhanced if unused inputs are connected to an appropriated logic voltage level (VDD
or VSS).
Symbol
VDD
Parameter
Value
Supply Voltage
Unit
-0.3 to 7.0
V
VI
Input Voltage (AFC IN)
VI
Input Voltage (Other Inputs)
VO
Output Voltage (PA4-PA7, PC4-PC7, DA0-DA5)
VO
Output Voltage (Other Outputs)
IO
Current Drain per Pin Excluding V DD, VSS, PA6, PA7
± 10
mA
IO
Current Drain per Pin (PA6, PA7)
± 50
mA
V
- 0.3 to +13
V
- 0.3 to VDD +0.3
V
SS
V
SS
VSS - 0.3 to +13
V
SS
V
- 0.3 to VDD +0.3
IVDD
Total Current into VDD (source)
50
mA
IVSS
Total Current out of VSS (sink)
150
mA
V
°C
Tj
Junction Temperature
150
TSTG
Storage Temperature
-60 to 150
°C
Note : Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device . This is a stress rating only
and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
THERMAL CHARACTERISTIC
Symbol
Parameter
Value
Test Conditions
Min.
RthJA
Unit
Typ.
Max.
PDIP40
PDIP28
Thermal Resistance
38
55
°C/W
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
TA
Operating Temperature
VDD
Operating Supply Voltage
fOSC
Oscillator Frequency
RUN & WAIT Modes
fOSDOSC
Value
Test Conditions
0
4.5
5.0
Min.
Typ.
70
°C
6.0
V
8
On-screen Display Oscillator
Frequency
Unit
Max.
8.1
MHz
8.0
MHz
59/82

ST63140,142,126,156
EEPROM INFORMATION
The ST631xx EEPROM single poly process has been specially developed to achieve 300.000
Write/Erase cycles and a 10 years data retention.
DC ELECTRICAL CHARACTERISTICS
(TA = 0 to +70°C unless otherwise specified)
Symbol
Parameter
Test Conditions
Value
Min.
Typ.
Max.
Unit
VIL
Input Low Level Voltage
All I/O Pins, KBY0-2
VIH
Input High Level Voltage
All I/O Pins, KBY0-2
Hysteresis Voltage(1)
All I/O Pins, KBY0-2
VDD = 5V
Low Level Output Voltage
Port B/C, DA0-3,
BSW0-3, OUT1,
VS, OSD Outputs,
VDD = 4.5V
IOL = 1.6mA
IOL = 5.0mA
0.4
1.0
V
V
0.4
1.0
V
V
VHYS
VOL
VOL
Low Level Output Voltage
Port A
VDD = 4.5V
IOL= 3.2mA
IOL= 30mA
VOL
Low Level Output Voltage
OSDOSCout, OSCout
VDD = 4.5V
IOL= 0.1mA
0.3xV
DD
0.75xVDD
V
V
1.0
V
V
0.4
(2)
VOH
VOH
High Level Output Voltage
High Level Output Voltage
Port B/C , VS
VDD = 4.5V
IOH = – 1.6mA
4.1
OSDOSCout, OSCout,
VDD = 4.5V
IOL= – 0.1mA
4.1
V
V
IPU
Input Pull Up Current
Input Mode with Pull-up
Port B/C, KBY0-2
(2)
VIN= VSS
– 100
– 50
– 25
mA
IIL
IIH
Input Leakage Current
OSCin
VIN= VSS
VIN= VDD
– 10
0.1
–1
1
– 0.1
10
µA
IIL
IIH
Input Leakage Current
All I/O Input Mode
no Pull-up
OSDOSCin
VIN= VDD or VSS
– 10
10
µA
IIL
IIH
Input Leakage Current
Reset Pin with Pull-up
VIN= VSS
– 50
– 10
µA
Input Leakage Current
AFC Pin
VIH= VDD
VIL= VSS
VIH= 12.0V
1
µA
IIL
IIH
– 30
–1
40
IOH
Output Leakage Current
Port A, DA0-3, BSW0-3
OUT1, OSDout
VOH = VDD
10
µA
IOH
Output Leakage Current High
Voltage
Port A, DA0-3, BSW0-3
OUT1
VOH = 12V
40
µA
60/82

ST63140,142,126,156
DC ELECTRICAL CHARACTERISTICS (Continued)
Symbol
Parameter
Test Conditions
Value
Min.
Typ.
Max.
Unit
IDD
Supply Current RUN Mode
fOSC= 8MHz, ILoad= 0mA
VDD= 6.0V
6
16
mA
IDD
Supply Current WAIT Mode
fOSC= 8MHz, ILoad= 0mA
VDD= 6V
3
10
mA
VON
Reset Trigger Level ON
RESET Pin
VOFF
Reset Trigger Level OFF
RESET Pin
VTA
Input Level Absolute
Tolerance
A/D AFC Pin
VDD = 5V
±200
mV
VTR
Input Level Relatice Tolerance
A/D AFC Pin
Relative to other levels
VDD = 5V
±100
mV
0.3xV
DD
0.8xVDD
V
V
Notes:
1. Not 100% Tested
2. Input pull-up option only
61/82

ST63140,142,126,156
AC ELECTRICAL CHARACTERISTICS
(TA = 0 to +70°C, fOSC=8MHz, VDD=4.5 to 6.0V unless otherwise specified )
Value
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
tWRES
Minimum Pulse Width
RESET Pin
125
ns
tO HL
High to Low Transition Time
PA6, PA7
VDD = 5V, CL = 1000pF (2)
100
ns
tO HL
High to Low Transition Time
DA0-DA5, PB0-PB6, OSD
Outputs, PC0-PC7,
VDD = 5V, CL = 100pF
20
ns
tO LH
Low to High Transition Time
PB0-PB6, PA0-PA3, OSD
Outputs, PC0-PC3
VDD = 5V, CL = 100pF
20
ns
tOH
Data HOLD Time
SPI after clock goes low
2
I CBUS/S-BUS Only
f DA
D/A Converter Repetition
(1)
Frequency
31.25
kHz
f SIO
SIO Baud Rate(1)
62.50
kHz
tWEE
EEPROM Write Time
TA = 25°C One Byte
Endurance
EEPROM WRITE/ERASE
Cycles
QA LOT
Acceptance Criteria
Retention
EEPROM Data Retention (4)
TA = 25°C
Input Capacitance (3)
All Inputs Pins
COUT
Output Capacitance (3)
All outputs Pins
COSCin,
COSCout
Oscillator Pins Internal
Capacitance(3)
COSDin,
COSDout
OSD Oscillator External
Capacitance
CIN
175
ns
5
300.000
10
ms
>1
million
cycles
10
years
10
pF
10
pF
5
Recommended
15
pF
25
Notes:
1. A clock other than 8 MHz will affect the frequency response of those peripherals (D/A, 62.5kHz and SPI) whose clock is
derived from the system clock.
2. The rise and fall times of PORT A have been reduced in order to avoid current spikes while maintaining a high drive capability
3. Not 100% Tested
4. Based on extrapolated data
62/82

pF
ST63140,142,126,156
PACKAGE MECHANICAL DATA
Figure 69. ST631xx 40 Pin Plastic Dual-In-line Package
Dim.
mm
Min
Typ
inches
Max
Min
Typ
Max
A
2.2
4.8
0.086
0.189
A1
0.51
1.77
0.010
0.069
B
0.38
0.58
0.015
0.023
B1
0.97
1.52
0.055
0.065
C
0.20
0.30
0.008
D
50.30
52.22 1.980
D1
–
E
–
–
0.009
20.560
–
–
15.2
E1
12.9
0.508
K1
–
–
–
–
–
K2
–
–
–
–
–
L
3.18
4.44
1.25
e1
–
0.600
–
–
0.174
2.54
0.10
Number of Pins
N
40
Figure 70. ST631xx 28-Pin Dual-In-line Package
Dim.
mm
Min
Typ
inches
Max
Min
Typ
Max
A
2.2
4.8
0.086
0.189
A1
0.51
1.77
0.010
0.069
B
0.38
0.58
0.015
0.023
B1
0.97
1.52
0.055
0.065
C
0.20
0.30
0.008
0.009
D
35.06
36.22 1.400
1.425
D1
–
E
–
–
–
15.2
E1
–
12.9
0.508
K1
–
–
–
–
–
K2
–
–
–
–
–
L
3.18
4.44
1.25
e1
–
0.600
2.54
–
–
0.174
0.10
Number of Pins
N
28
63/82

ST63140,142,126,156
ORDERING INFORMATION
The following chapter deals with the procedure for
transfer the Program/Data ROM codes to SGSTHOMSON.
Communication of the ROM Codes. To communicate the contents of Program /Data ROM memories to SGS-THOMSON, the customer has to send
a 5” Diskette with:
– one file in INTEL INTELLEC 8/MDS FORMAT
for the PROGRAM Memory
– one file in INTEL INTELLEC 8/MDS FORMAT
for the ODD and EVEN ODD OSD Characters
– one file in INTEL INTELLEC 8/MDS FORMAT
for the EEPROM initial content
(this file is optional)
– a filled Option List form as described in the
OPTION LIST paragraph.
The program ROM should respect the ROM Memory Map as in Table 19.
The ROM code must be generated with ST6 assembler. Before programming the EPROM, the
buffer of the EPROM programmer must be filled
with FFh.
Table 19. ROM Memory Map
ROM Page
Device
Address
EPROM
Address (1)
Description
Page 0
0000h-007Fh
0080h-07FFh
0000h-007Fh
0080h-07FFh
Reserved
User ROM
Page 1
“STATIC”
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Vector
Reset Vector
Page 2
0000h-000Fh
0010h-07FFh
1000h-100Fh
1010h-17FFh
Reserved
User ROM
Page 3
0000h-000Fh
0010h-07FFh
1800h-180Fh
1810h-1FFFh
Reserved
user ROM
Note 1. EPROM addresses are related to the use of ST63E1xx EPROM emulation devices.
64/82

ST63140,142,126,156
ORDERING INFORMATION (Continued)
Customer EEPROM Initial Contents:
Format
a. The content should be written into an INTEL
INTELLEC format file.
b. Undefined or don’t care bytes should have the
content FFh.
OSD Test Character. IN ORDER TO ALLOW THE
TESTING OF THE ON-CHIP OSD MACROCELL
THE FOLLOWING CHARACTER MUST BE PROVIDED AT THE FIXED 3Fh (63) POSITION OF
THE SECOND OSD BANK.
Listing Generation & Verification. When SGSTHOMSON receives the files, a computer listing is
generated from them. This listing refers extractly to
the mask that will be used to produce the microcontroller. Then the listing is returned to the customer
that must thoroughly check, complete, sign and
Figure 71. OSD Test Character
return it to SGS-THOMSON. The signed list constitutes a part of the contractual agreement for the
creation of the customer mask. SGS-THOMSON
sales organization will provide detailed information
on contractual points.
ORDERING INFORMATION TABLE
Sales Type
ROM/EEPROM
ST63140B1/XX
Temperature Range
Package
0 to + 70 ° C
PDIP28
ST63126B1/XX
8K (EPROM)
0 to + 70 ° C
/
128 Bytes
0 to + 70 ° C
PDIP40
ST63156B1/XX
0 to + 70 ° C
PDIP40
ST63142B1/XX
PDIP28
Note. /XX Is the ROM Code idebtifier that is allocated by SGS-THOMSON after receipt of all required options and the related ROM file
65/82

ST63140,142,126,156
ST631xx MICROCONTROLLER OPTION LIST
Customer:
Address:
Contact:
Phone No:
Reference:
.
.
.
.
.
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.
Device
[ ] ST63140
[ ] ST63142
Temperature Range
0 to 70°C
.
.
.
.
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[ ] ST63126
.
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[ ] ST63156
For marking one line with 12 characters maximum is possible
Special Marking
[ ] No
[ ] Yes Line1 “ _ _ _ _ _ _ _ _ _ _ _ _ ”
Letters, digits, ’ . ’, ’ - ’, ’ / ’ and spaces only
the default marking is equivalent to the sales type only (part number).
OSD POLARITY OPTIONS (Put a cross on selected item) :
POSITIVE
NEGATIVE
VSYNC,HSYNC
[ ]
[ ]
R,G,B
[ ]
[ ]
BLANK
[ ]
[ ]
CHECK LIST:
ROM CODE
OSD Code: ODD & EVEN
EEPROM Code (if Desired)
YES
[ ]
[ ]
[ ]
NO
[ ]
[ ]
[ ]
Signature ...................................
Date ...........................................
66/82

.
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.

ST63E140/T140, E142/T142
ST63E126/T126, E156/T156
8-BIT EPROM HCMOS MCUs FOR
TV FREQUENCY & VOLTAGE SYNTHESIS WITH OSD
PRELIMINARY DATA
4.5 to 6V operating Range
8MHz Maximum Clock Frequency
User Program EPROM: 7948 bytes
Reserved Test EPROM:
244 bytes
Data EPROM:
user selectable size
Data RAM:
256 bytes
Data EEPROM:
128 bytes
40-Pin Dual in Line Package for the
ST63x126, x156
28-Pin Dual in Line Package for the
ST63x140, x142
Up to 18 software programmable general
purpose Inputs/Outputs, including 8 direct LED
driving Outputs
3 Inputs for keyboard scan (KBY0-2)
Up to 4 high voltage outputs (BSW0-3)
Two Timers each including an 8-bit counter with
a 7-bit programmable prescaler
Digital Watchdog Function
Serial Peripheral Interface (SPI) supporting
S-BUS/ I2C BUS and standard serial protocols
Up to Four 6-bit PWM D/A Converters
62.5kHz Output pin
14 bit counter for voltage synthesis tuning
(ST63156, ST63140)
AFC A/D converter with 0.5V resolution
Four interrupt vectors (IRIN/NMI, Timer 1 & 2,
VSYNC.)
On-chip clock oscillator
5 Lines by 15 Characters On-Screen Display
Generator with 128 Characters (2 banks)
These EPROM and OTP versions are fully pin to
pin compatible with their respective ROM versions
The development tool of the ST631xx
microcontrollers consists of the ST63TVS-EMU
emulation and development system to be
connected via a standard RS232 serial line to an
MS-DOS Personal Computer.
EPROM programming board ST63E1XX-EPB
1
28
1
1
1
(Ordering Information at the end of the datasheet)
October 1993
This is Preliminary information from SGS-THOMSON. Details are subject to change without notice.
67/82
ST63E140,E142,E126,E156, T140,T142,T126,T156
Figure 1. ST63E126/T126, E156/T156 Pin Configuration
BSW0
BSW1
BSW2
BSW3
KBY0
KBY 1
KBY2
OSDOSCout
OSDOSCin
(SEN) PB7
(SDA) PB6
(SCL) PB5
(HSYNC) PB3
(VSYNC) PB2
AFC
(1)
TEST
PA6
PA5
PA4
V SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
DA3
DA2
DA1
DA0
OUT1
IRIN
PC7 (B)
PC6 (G)
PC5 (R)
PC3 (BLANK)
PC2 (ON/OFF)
PC1
PC0
OSCout
OSCin
RESET
PA1
PA2
PA3
VA00282
ST63E126/T126
BSW0
BSW
BSW2
BSW3
KBY0
KBY 1
KBY2
OSDOSCout
OSDOSCin
(SEN) PB7
(SDA) PB6
(SCL) PB5
(HSYNC) PB3
(VSYNC) PB2
AFC
(1)
TEST
PA6
PA5
PA4
V SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
DA3
DA2
DA1
DA0
OUT1
IRIN
VS
PC7 (B)
PC6 (G)
PC5 (R)
PC3 (BLANK)
PC2 (ON/OFF)
PC1
OSCout
OSCin
RESET
PA1
PA2
PA3
VA00288
ST63E156/T156
Note 1. This pin is also the V PP input for EPROM based devices
Figure 2. ST63E140/T140, E142/T142 Pin Configuration
BSW0
BSW1
1
2
28
27
V DD
DA0
BSW2
KBY0
KBY1
3
4
5
26
25
24
OUT1
VS
PC6 (G)
KBY2
OSDOSCout
OSDOSCin
6
7
8
23
22
21
PC4
PC3 (BLANK)
PC2
PB3 (HSYNC)
PB2 (VSYNC)
AFC
9
10
11
20
19
18
OSCout
OSCin
RESET
(1)
12
13
14
17
16
15
PA0
PA1
PA2
TEST
PA4
V SS
BSW0
1
28
VDD
BSW1
BSW2
KBY0
2
3
4
27
26
25
DA0
OUT1
IRIN
KBY1
KBY2
OSDOSCout
5
6
7
24
23
22
PC6 (G)
PC5 (R)
PC4
OSDOSCin
PB3 (HSYNC)
PB2 (VSYNC)
8
9
10
21
20
19
PC2
OSCout
OSCin
AFC
(1)
TEST
PA4
11
12
13
18
17
16
RESET
PA0
PA1
VSS
14
15
PA2
VR001390
VR001389
ST63E142/T142
ST63E140/T140
Note 1. This pin is also the V PP input for EPROM based devices
68/82

ST63E140,E142,E126,E156, T140,T142,T126,T156
GENERAL DESCRIPTION
The ST63E140/T140, E142/T142, E126/T126,
E156/T156 microcontrollers are members of the 8bit HCMOS ST631xx family, a series of devices
specially oriented to TV applications. Different peripheral configurations are available to give the
maximum application and cost flexibility. All
ST631xx members are based on a building block
approach: a common core is surrounded by a combination of on-chip peripherals (macrocells) available from a standard library. These peripherals are
designed with the same Core technology providing
full compatibility and short design time. Many of
these macrocells are specially dedicated to TV applications.
The macrocells of the ST631xx family are: two
Timer peripherals each including an 8-bit counter
with a 7-bit software programmable prescaler
(Timer), a digital hardware activated watchdog
function (DHWD), a 14-bit voltage synthesis tuning
peripheral, a Serial Peripheral Interface (SPI), up
to four 6-bit PWM D/A converters, an AFC A/D converter with 0.5V resolution, an on-screen display
(OSD) with 15 characters per line and 128 characters (in two banks each of 64 characters). In addition the following Memory resources are available:
program EPROM (8K), data RAM (256 bytes),
EEPROM (128 bytes).
Refer to pin configuration figures and to ST631xx
device summary (Table 1) for the definition of
ST631xx family members and a summary of differences among the different types.
69/82

ST63E140,E142,E126,E156, T140,T142,T126,T156
Figure 3. ST631xx family Block Diagram
* Refer To Pin Configuration For Additional Information
TEST/VP P
TEST
PORT A
PA0 - PA7
IRIN/NMI
IR INTERRUPT
Input
PORT B
PB2 - PB7 *
PORT C
PC0 - PC7 *
DATA ROM
USER SELECTABLE
USER PROGRAM
EPROM
8 KBytes
SERIAL PERIPHERAL
INTERFACE
DATA RAM
256 Bytes
TIMER 1
DATA EEPROM
128 Bytes
TIMER 2
DIGITAL
WATCHDOG/TIMER
PC
STACK
STACK
STACK
STACK
STACK
STACK
LEVEL 1
LEVEL 2
LEVEL 3
LEVEL 4
LEVEL 5
LEVEL 6
VSS
D / A Outputs
DA0 - DA3
VS output &
AFC input
AFC & VS *
8-BIT CORE
POWER SUPPLY
VDD
*
OSCILLATOR
OSCin
ON-SCREEN
DISPLAY
RESET
OSCout
RESET
OSDOSCin
R, G, B, BLANK
HSYNC (PB3)
VSYNC (PB2)
VR 01753F
OSDOSCout
Table 1. Device Summary
OTP RAM
ROM
(Bytes) (Bytes) (Bytes)
EPROM
DEVICE
ST63E140
8K
ST63T140
ST63E142
8K
8K
ST631T42
ST63E126
8K
8K
ST63T126
ST63E156
ST63T156
8K
8K
8K
I/O
KBY
I/O
BSW
OUT
AFC
VS
D/A
PACK.
TARGET
ROM
DEVICES
EEPROM
(Bytes)
256
128
6
3
3
YES
YES
1
PDIP28
ST63140
256
128
6
3
3
YES
YES
1
PDIP28
ST63140
256
128
6
3
3
YES
NO
1
PDIP28
ST63142
256
128
6
3
3
YES
NO
1
PDIP28
ST63142
256
128
12
3
4
YES
NO
4
PDIP40
ST63126
256
128
12
3
4
YES
NO
4
PDIP40
ST63126
256
128
11
3
4
YES
YES
4
PDIP40
ST63156
256
128
11
3
4
YES
YES
4
PDIP40
ST63156
70/82

ST63E140,E142,E126,E156, T140,T142,T126,T156
PIN DESCRIPTION
VDD and VSS. Power is supplied to the MCU using
these two pins. VDD is power and VSS is the ground
connection.
OSCin, OSCout. These pins are internally connected to the on-chip oscillator circuit. A quartz
crystal or a ceramic resonator can be connected
between these two pins in order to allow the correct operation of the MCU with various stability/cost trade-offs. The OSCin pin is the input pin,
the OSCout pin is the output pin.
RESET. The active low RESET pin is used to start
the microcontroller to the beginning of its program.
TEST/VPP. The TEST pin must be held at VSS for
normal operation. If this pin is connected to a
12.5V level during the reset phase, the EPROM
programming mode is entered.
Caution. Exceeding 13V on TEST/VPP pin will permanently damaged the device.
PA0-PA7. These 8 lines are organized as one I/O
port (A). Each line may be configured as either an
input or as an output under software control of the
data direction register. Port A has an open-drain
(12V drive) output configuration with direct LED
driving capability (30mA, 1V).
PB2-PB3, PB5-PB7. These lines are organized as
one I/O port (B). Each line may be configured as
either an input with or without internal pull-up resistor or as an output under software control of the
data direction register. PB2-PB3 have a push-pull
configuration in output mode while PB5-PB7 are
open-drain (5V drive).
PB2 and PB3 lines are connected to the VSYNC
and HSYNC control signals of the OSD cell; to provide the right signals to the OSD these I/O lines
should be programmed in input mode and the user
can read “on the fly” the state of VSYNC and
HSYNC signals. PB2 is also connected with the
VSYNC Interrupt. The active polarity of VSYNC Interrupt signal is software controlled. The active polarity of these synchronization input pins to the
OSD macrocell can be selected by the user as
ROM mask option. If the device is specified to have
negative logic inputs, then when these signals are
low the OSD oscillator stops. If the device is specified to have positive logic inputs, then when these
signals are high the OSD oscillator stops.
PB5, PB6 and PB7 lines, when in output modes,
are “ANDed” with the SPI control signals. PB5 is
connected with the SPI clock signal (SCL), PB6
with the SPI data signal (SDA) while PB7 is connected with SPI enable signal (SEN).
PC0-PC7. These 8 lines are organized as one I/O
port (C). Each line may be configured as either an
input with or without internal pull-up resistor or as
an output under software control of the data direction register. PC0-PC2, PC4 have a push-pull configuration in output mode while PC3, PC5-PC7
(OSD signals) are open-drain (5V drive). PC3, PC5 ,
PC6 and PC7 lines when in output mode are
“ANDed” with the character and blank signals of
the OSD cell. PC3 is connected with the OSD
BLANK signal, PC5, PC6 and PC7 with the OSD R,
G and B signals. The active polarity of these signals can be selected by the user as ROM mask option. PC2 is also used as TV set ON-OFF switch
(5V drive).
DA0-DA3. These pins are the four PWM D/A outputs (with 32kHz repetition) of the 6-bit on-chip D/A
converters. The PWM function can be disabled by
software and these lines can be used as general
purpose open-drain outputs (12V drive).
IRIN. This pin is the external NMI of the MCU.
OUT1. This pin is the 62.5kHz output specially
suited to drive multi-standard chroma processors.
This function can be disabled by software and the
pin can be used as general purpose open-drain
output (12V drive).
BSW0-BSW3. These output pins can be used to
select up to 4 tuning bands. These lines are configured as open-drain outputs (12V drive).
KBY0-KBY2. These pins are input only and can be
used for keyboard scan. They have CMOS threshold levels with Schmitt Trigger and on-chip 100kΩ
pull-up resistors.
AFC. This is the input of the on-chip 10 level comparator that can be used to implement the AFC
function. This pin is an high impedance input able
to withstand signals with a peak amplitude up to
12V.
OSDOSCin, OSDOSCout. These are the On
Screen Display oscillator terminals. An oscillation
capacitor and coil network have to be connected to
provide the right signal to the OSD.
VS. This is the output pin of the on-chip 14-bit voltage synthesis tuning cell (VS). The tuning signal
present at this pin gives an approximate resolution
of 40kHz per step over the UHF band. This line is a
push-pull output with standard drive (ST63140,
ST63156 only).
71/82

ST63E140,E142,E126,E156, T140,T142,T126,T156
PIN DESCRIPTION (Continued)
Table 2. Pin Summary
Pin Function
Description
DA0 to DA3
Output, Open-Drain, 12V
BSW0 to BSW3
Output, Open-Drain, 12V
IRIN
Input, Resistive Bias, Schmitt Trigger
AFC
Input, High Impedance, 12V
OUT1
Output, Open-Drain, 12V
KBY0 to KBY2
Input, Pull-up, Schmitt Trigger
R,G,B, BLANK
Output, Open-Drain, 5V
HSYNC, VSYNC
Input, Pull-up, Schmitt Trigger
OSDOSCin
Input, High Impedance
OSDOSCout
Output, Push-Pull
TEST/VPP
Input, Pull-Down
OSCin
Input, Resistive Bias, Schmitt Trigger to Reset Logic Only
OSCout
Output, Push-Pull
RESET
Input, Pull-up, Schmitt Trigger Input
VS
Output, Push-Pull
PA0-PA6
I/O, Open-Drain, 12V, No Input Pull-up, Schmitt Trigger, High Drive
PB2-PB3, PB5-PB7
I/O, Push-Pull, 5V, Input Pull-up, Schmitt Trigger
PB5-PB7
I/O, Open-Drain, 5V, Input Pull-up, Schmitt Trigger
PC0-PC2, PC4
I/O, Push-Pull, 5V, Input Pull-up, Schmitt Trigger
PC3, PC5-PC7
I/O, Open-Drain, 5V, Input Pull-up, Schmitt Trigger
VDD, VSS
Power Supply Pins
72/82

ST63E140,E142,E126,E156, T140,T142,T126,T156
MEMORY SPACE
Table 3. EPROM Memory Map
EPROM Page
Device Address
EPROM Address
Description
Page 0
0000h-007Fh
0080h-07FFh
0000h-007Fh
0080h-07FFh
Reserved
User ROM
Page 1
“STATIC”
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Vector
Reset Vector
Page 2
0000h-000Fh
0010h-07FFh
1000h-100Fh
1010h-17FFh
Reserved
User ROM
Page 3
0000h-000Fh
0010h-07FFh
1800h-180Fh
1810h-1FFFh
Reserved
user ROM
73/82

ST63E140,E142,E126,E156, T140,T142,T126,T156
EPROM/OTP DESCRIPTION.
The ST63E1xx represents the generic part number
for the EPROM versions of the ST63140, 42, 26,
56 ROM products. They are intended for use during the development of an application, and for preproduction and small volume production.
The ST63T1xx OTP have the same characteristics.
They both include EPROM memory instead of the
ROM memory of the ST631xx, and so the program
and constants of the program can be easily modified by the user with the ST63E1XX EPROM Programming Board from SGS-THOMSON.
The ROM mask options of the ST631xx for OSD
polarities (HSYNC, VSYNC, R, G, B, BLANK) are
emulated with an EPROM OPTION BYTE. This is
programmed by the SGS-THOMSON EPROM
programming board and its associated software.
The EPROM Option Byte content will define the
OSD options as follows :
7
Opt7
From a user point of view (with the following exceptions) the ST63E1xx,T1xx products have exactly
the same software and hardware features of the
ROM version. An additional mode is used to configure the part for programming of the EPROM, this
is set by a +12.5V voltage applied to the TEST/VPP
pin. The programming of the ST63E1xx,T1xxis described in the User Manual of the EPROM Programming board.
On the ST63E1xx, all the 7948 bytes of PROGRAM memory are available for the user, as all the
EPROM memory can be erased by exposure to UV
light. On the ST63T1xx (OTP device) a reserved
area for test purposes exists, as for the ST631xx
ROM device. In order to avoid any discrepancy between program functionality when using the
EPROM, OTP and ROM it is recommended NOT
TO USE THESE RESERVED AREAS, even when
using the ST63E1xx. The Table 3 is a summary of
the EPROM/ROM Map and its reserved area.
0
Opt6
Opt5
Opt4
Opt3
Opt 2
Opt 1
Opt 0
Opt7-Opt6. Device specific bits (1)
THE READER IS ASKED TO REFER TO THE
DATASHEET OF THE ST631xx ROM-BASED
DEVICE FOR FURTHER DETAILS.
EPROM ERASING
The EPROM of the windowed package of the
ST63E1xx may be erased by exposure to Ultra
Violet light.
Opt5 : This bit define the BLANK polarity,
if 0 the polarity will be negative
if 1 the polarity will be positive..
Opt 4 : This bit define the RGB polarity,
if 0 the polarity will be negative
if 1 the polarity will be positive..
Opt 3 : This bit define the OSD H/Vsync polarity,
if 0 the polarity will be negative
if 1 the polarity will be positive.
Opt2-Opt0. Device specific bits (1)
Note 1. Device specific bits. These reserved bits
must be programmed according to the following table for their relevant device.
Sales Type
Opt7-Opt6
Opt2-Opt0
ST63E140/T140
0 0
1 0 0
ST63E142/T142
0 0
1 0 1
ST63E126/T126
0 0
1 0 1
ST63E156/T156
0 0
1 0 1
74/82

The erasure characteristic of the ST63E1xx
EPROM is such that erasure begins when the
memory is exposed to light with wave lengths
shorter than approximately 4000Å. It should be
noted that sunlight and some types of fluorescent
lamps have wavelengths in the range3000-4000Å.
It is thus recommended that the window of the
ST63E1xx package be covered by anopaque label
to prevent unintentional erasure problems when
testing the application in such an environment.
The recommended erasure procedure of the
ST63E1xx EPROM is exposure to short wave ultraviolet light which haswavelength 2537Å. The integrated dose (i.e. UV intensity x exposure time)
2
for erasure should be a minimum of 15 W-sec/cm .
The erasure time with this dosage is approximately
15 to 20 minutes using an ultraviolet lamp with
12000µW/cm2 power rating. The ST63E1xx
should be placed within 2.5 cm (1 inch) of the lamp
tubes during erasure.
ST63E140,E142,E126,E156, T140,T142,T126,T156
ABSOLUTE MAXIMUM RATINGS
This product contains devices to protect the inputs
against damage due to high static voltages, however it is advised to take normal precaution to avoid
application of any voltage higher than maximum
rated voltages.
Power Considerations. The average chip-junction temperature, Tj, in Celsius can be obtained
from :
Tj =
TA + PD x RthJA
Ambient Temperature.
Where :TA =
RthJA = Package thermal resistance
(junction-to ambient).
PD =
Pint + Pport.
Pint =
IDD x VDD (chip internal power).
Pport = Port power dissipation
(determinated by the user).
For proper operation it is recommended that VI and
VO must be higher than VSS and smaller than VDD.
Reliability is enhanced if unused inputs are connected to an appropriated logic voltage level (VDD
or VSS).
Symbol
VDD
Parameter
Supply Voltage
Value
Unit
-0.3 to 7.0
VI
Input Voltage (AFC IN)
VI
Input Voltage (Other Inputs)
VO
Output Voltage (PA4-PA7, PC4-PC7, DA0-DA5)
VO
Output Voltage (Other Outputs)
VPP
EPROM programming Voltage
V
V
- 0.3 to +13
V
- 0.3 to VDD +0.3
V
SS
V
SS
VSS - 0.3 to +13
V
SS
V
- 0.3 to VDD +0.3
-0.3 to 13.0
V
V
IO
Current Drain per Pin Excluding VDD, VSS, PA6, PA7
± 10
mA
IO
Current Drain per Pin (PA6, PA7)
± 50
mA
IVDD
Total Current into VDD (source)
50
mA
IVSS
Total Current out of VSS (sink)
150
mA
°C
Tj
Junction Temperature
150
TSTG
Storage Temperature
-60 to 150
°C
Note : Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device . This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
TA
Operating Temperature
VDD
Operating Supply Voltage
fOSC
Oscillator Frequency
RUN & WAIT Modes
fOSDOSC
Value
Test Conditions
0
4.5
5.0
Min.
Typ.
70
°C
6.0
V
8
On-screen Display Oscillator
Frequency
Unit
Max.
8.1
MHz
8.0
MHz
75/82

ST63E140,E142,E126,E156, T140,T142,T126,T156
EEPROM INFORMATION
The ST631xx EEPROM single poly process has been speciallydeveloped to achieve 300.000
Write/Erase cycles and a 10 years data retention.
DC ELECTRICAL CHARACTERISTICS
(TA = 0 to +70°C unless otherwise specified)
Symbol
Parameter
Test Conditions
VIL
Input Low Level Voltage
All I/O Pins, KBY0-2
VIH
Input High Level Voltage
All I/O Pins, KBY0-2
VHYS
VOL
Value
Min.
0.3xV
DD
Unit
V
V
Hysteresis Voltage
All I/O Pins, KBY0-2
VDD = 5V
Low Level Output Voltage
Port B/C, DA0-3,
BSW0-3, OUT1,
VS, OSD Outputs,
VDD = 4.5V
IOL = 1.6mA
IOL = 5.0mA
0.4
1.0
V
V
0.4
1.0
V
V
(1)
1.0
VOL
Low Level Output Voltage
VOL
Low Level Output Voltage
OSDOSCout, OSCout
VDD = 4.5V
IOL= 0.1mA
0.4
Port B/C (2), VS
VDD = 4.5V
IOH = – 1.6mA
4.1
OSDOSCout, OSCout,
VDD = 4.5V
IOL= – 0.1mA
4.1
VOH
Max.
0.75xVDD
Port A
VDD = 4.5V
IOL= 3.2mA
IOL= 30mA
VOH
Typ.
High Level Output Voltage
High Level Output Voltage
V
V
V
V
IPU
Input Pull Up Current
Input Mode with Pull-up
Port B/C, KBY0-2
(2)
VIN= VSS
– 100
– 50
– 25
mA
IIL
IIH
Input Leakage Current
OSCin
VIN= VSS
VIN= VDD
– 10
0.1
–1
1
– 0.1
10
µA
IIL
IIH
Input Leakage Current
All I/O Input Mode
no Pull-up
OSDOSCin
VIN= VDD or VSS
– 10
10
µA
IIL
IIH
Input Leakage Current
Reset Pin with Pull-up
VIN= VSS
– 50
– 10
µA
Input Leakage Current
AFC Pin
VIH= VDD
VIL= VSS
VIH= 12.0V
1
µA
IIL
IIH
– 30
–1
40
IOH
Output Leakage Current
Port A, DA0-3, BSW0-3
OUT1, OSDout
VOH = VDD
10
µA
IOH
Output Leakage Current High
Voltage
Port A, DA0-3, BSW0-3
OUT1
VOH = 12V
40
µA
76/82

ST63E140,E142,E126,E156, T140,T142,T126,T156
DC ELECTRICAL CHARACTERISTICS (Continued)
Symbol
Parameter
Test Conditions
Value
Min.
Typ.
Max.
Unit
IDD
Supply Current RUN Mode
fOSC= 8MHz, ILoad= 0mA
VDD= 6.0V
6
16
mA
IDD
Supply Current WAIT Mode
fOSC= 8MHz, ILoad= 0mA
VDD= 6V
3
10
mA
VON
Reset Trigger Level ON
RESET Pin
0.3xV
VOFF
Reset Trigger Level OFF
RESET Pin
0.8xVDD
VTA
Input Level Absolute Tolerance
A/D AFC Pin
VDD = 5V
±200
mV
VTR
Input Level Relatice Tolerance
A/D AFC Pin
Relative to other levels
VDD = 5V
±100
mV
DD
V
V
77/82

ST63E140,E142,E126,E156, T140,T142,T126,T156
AC ELECTRICAL CHARACTERISTICS
(TA = 0 to +70°C, fOSC=8MHz, VDD=4.5 to 6.0V unless otherwise specified )
Value
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
tWRES
Minimum Pulse Width
RESET Pin
125
ns
tO HL
High to Low Transition Time
PA6, PA7
VDD = 5V, CL = 1000pF (2)
100
ns
tO HL
High to Low Transition Time
DA0-DA5, PB0-PB6, OSD
Outputs, PC0-PC7,
VDD = 5V, CL = 100pF
20
ns
tO LH
Low to High Transition Time
PB0-PB6, PA0-PA3, OSD
Outputs, PC0-PC3
VDD = 5V, CL = 100pF
20
ns
tOH
Data HOLD Time
SPI after clock goes low
2
I CBUS/S-BUS Only
f DA
D/A Converter Repetition
(1)
Frequency
31.25
kHz
f SIO
SIO Baud Rate(1)
62.50
kHz
tWEE
EEPROM Write Time
TA = 25°C One Byte
Endurance
EEPROM WRITE/ERASE Cycles
QA LOT
Acceptance Criteria
300.000
Retention
EEPROM Data Retention (4)
TA = 25°C
10
Input Capacitance (3)
All Inputs Pins
COUT
Output Capacitance (3)
All outputs Pins
COSCin,
COSCout
Oscillator Pins Internal
Capacitance(3)
COSDin,
COSDout
OSD Oscillator External
Capacitance
C IN
175
ns
5
10
ms
>1
million
cycles
years
10
pF
10
pF
5
Recommended
15
pF
25
Notes:
1.A clock other than 8 MHz will affect the frequency response of those peripherals (D/A, 62.5kHz and SPI) whose clock is
derived from the system clock.
2. The rise and fall times of PORT A have been reduced in order to avoid current spikes while maintaining a high drive capability
3. Not 100% Tested
4. Based on extrapolated data
78/82

pF
ST63E140,E142,E126,E156, T140,T142,T126,T156
PACKAGE MECHANICAL DATA
Figure 69. 40 Pin Ceramic Dual-In-line Package
Dim.
mm
Min
inches
Typ
Max
Min
Typ
Max
A
A1
B
0.45
.018
50.8
2.00
15.2 BSD
0.600 BSD
13.2
.52
B1
C
D
D1
E
E1
K
L
e1
Ø
Number of Pins
N
40
Figure 70. 28-Pin Ceramic Dual-In-line Package
Dim.
mm
Min
inches
Typ
Max
A
Min
Typ
5.71
Max
.225
A1
0.50
1.78
.020
B
0.40
0.55
.016
.022
B1
1.17
1.42
.046
.056
C
0.22
0.31
.009
D
D1
38.10
15.2
E
24.9
15.2 BSD
.070
.012
1.500
.060
.098
0.600 BSD
E1
13.05
L
3.00
13.36
.514
.526
e1
2.29
2.79
.090
.110
Ø
6.86
7.36
.270
.290
.118
Number of Pins
N
28
79/82

ST63E140,E142,E126,E156, T140,T142,T126,T156
ORDERING INFORMATION
To ensure compatibility between the EPROM/OTP
parts and the corresponding ROM families, the following information is provided. the user should
take this information into account when programming the memory and OSD characters of the
EPROM parts.
Communication of the ROM Codes. To communicate the contents of memories to SGS-THOMSON, the customer has to send:
– one file in INTEL INTELLEC 8/MDS FORMAT (either as an EPROM or in a MS-DOS 5”
diskette) for the ODD and EVEN OSD Character
OSD ROM/EEPROM
– one file in INTEL INTELLEC 8/MDS FORMAT (either as an EPROM or in a MS-DOS 5”
diskette) for the EEPROM initial content (this
file is optional)
– a filled Option List form as described in the
OPTION LIST paragraph.
The ROM code must be generated with ST6 assembler. Before programming the EPROM, the
buffer of the EPROM programmer must be filled
with FFh.
For shipment to SGS-THOMSON the EPROMs
should be placed in a conductive IC carrier and
packaging carefully.
Customer EEPROM Initial Contents:
Format
a. The content should be written into an INTEL INTELLEC format file.
b. Undefined or don’t care bytes should have the
content FFh.
80/82

OSD Test Character.IN ORDER TO ALLOWTHE
TESTING OF THE ON-CHIP OSD MACROCELL
THE FOLLOWING CHARACTER MUST BE PROVIDED AT THE FIXED 3Fh (63) POSITION OF
THE SECOND OSD BANK.
Listing Generation & Verification. When SGSTHOMSON receives the files, a computer listing is
generated from them. This listing refers extractly to
the mask that will be used to produce the microcontroller. Then the listing is returned to the customer that must thoroughly check, complete, sign
and return it to SGS-THOMSON. The signed list
constitutes a part of the contractual agreement for
the creation of the customer mask. SGS-THOMSON sales organization will provide detailed information on contractual points.
Figure 71. OSD Test Character
ST63E140,E142,E126,E156, T140,T142,T126,T156
ST63E1xx/T1xx MICROCONTROLLER OPTION LIST
Customer:
Address:
Contact:
Phone No:
Reference:
Device
....... ...... .... .... ............................. .... .
. .. .. .. .. .. .. . .. . . . .. . . .. . . .. . .. . . . .. . .. .. .. .. .. .. . .. ..
. . .. . . . . . .. . . .. . . . .. . .. .. .. .. . .. . .. . . .. .. .. . .. .. ... .. . .
. .. . .. . . .. .. . .. .. .. . . .. . . .. . . . ... .. . .. . . . .. . . .. . . .. .. ..
. . . .. . . ... .. . . .. . . .. ... .. . . .. . . ... .. .. . .. . .. . . . .. . . .. ..
[ ] ST63E140 [ ] ST63E142 [ ] ST63E126 [ ] ST63E156
[ ] ST63T140 [ ] ST63T142 [ ] ST63T126 [ ] ST63T156
Temperature Range
0 to 70°C
For marking one line with 10 characters maximum is possible
Special Marking
[ ] No
[ ] Yes Line1 “ _ _ _ _ _ _ _ _ _ _ ”
Letters, digits, ’ . ’, ’ - ’, ’ / ’ and spaces only
the default marking is equivalent to the sales type only (part number).
CHECK LIST:
OSD Code: ODD & EVEN
EEPROM Code (if Desired)
YES
[ ]
[ ]
NO
[ ]
[ ]
Signature ...................................
Date ...........................................
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ST63E140,E142,E126,E156, T140,T142,T126,T156
ORDERING INFORMATION TABLE
Sales Type
ROM/EEPROM
ST63E140D1
Temperature Range
Package
0 to + 70 ° C
CDIP28
ST63E126D1
8K (EPROM)
0 to + 70 ° C
/
128 Bytes
0 to + 70 ° C
CDIP40
ST63E156D1
0 to + 70 ° C
CDIP40
ST63E142D1
0 to + 70 ° C
ST63T140B1
ST63T126B1
8K (OTPROM)
0 to + 70 ° C
/
128 Bytes
0 to + 70 ° C
ST63T156B1
0 to + 70 ° C
ST63T142B1
CDIP28
PDIP28
PDIP28
PDIP40
PDIP40
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the
express written approval of SGS-THOMSON Microelectronics.
 1994 SGS-THOMSON Microelectronics - All rights reserved.
2
2
Purchase of I C Components by SGS-THOMSON Microelectronics conveys a license under the Philips I C Patent.
2
2
Rights to use these components in an I C system is granted provided that the system conforms to the I C Standard
Specification as defined by Philips.
SGS-THOMSON Microelectronics Group of Companies
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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