STMICROELECTRONICS ST70235A

ST70235A
ASCOTTM DMT TRANSCEIVER
PRELIMINARY DATA
■ DMT
MODEM
FOR
CPE
ADSL,
COMPATIBLE WITH THE FOLLOWING
STANDARDS:
- ANSI T1.413 ISSUE 2
- ITU-T G.992.1 (G.DMT)
- ITU-T G.992.2 (G.LITE)
■ SUPPORTS EITHER ATM (UTOPIA LEVEL
1 & 2) OR BITSTREAM INTERFACE
■ 16 BIT MULTIPLEXED MICROPROCESSOR
INTERFACE (LITTLE AND BIG ENDIAN
COMPATIBILITY)
■ ANALOG FRONT END MANAGEMENT
■ DUAL
LATENCY
INTERLEAVED
PATHS:
FAST
AND
■ ATM’S PHY LAYER: CELL PROCESSING
(CELL DELINEATION, CELL INSERTION,
HEC)
■ ADSL’S OVERHEAD MANAGEMENT
■ REED SOLOMON ENCODE/DECODE
■ TRELLIS ENCODE/DECODE (VITERBI)
GENERAL DESCRIPTION
The ST70235A is the DMT modem and ATM
framer of the STMicroelectronics ASCOT™
chipset. When coupled with ST70134 analog
front-end and an external controller running
dedicated firmware, the product fulfills ANSI
T1.413 "Issue 2" DMT ADSL specification. The
chip supports UTOPIA level 1 and UTOPIA level 2
interface.
The ST70235A can be split up into two different
sections. The physical one performs the
DMT modulation, demodulation, Reed-Solomon
encoding, bit interleaving and 4D trellis coding.
The ATM section embodies framing functions for
the generic and ATM Transmission Convergence
(TC) layers. The generic TC consists of data
scrambling and Reed Solomon error corrections,
with and without interleaving.
The ST70235A is controlled and programmed
by an external controller (ADSL Transceiver Controller, ATC) that sets the programmable coefficients. The firmware controls the initialization
phase and carries out the consequent adaptation
operations.
■ DMT MAPPING / DEMAPPING OVER 256
CARRIERS
■ FINE (2PPM) TIMING RECOVER USING
ROTOR AND ADAPTATIVE FREQUENCY
DOMAIN EQUALIZING
■ TIME DOMAIN EQUALIZATION
■ FRONT END DIGITAL FILTERS
■ 0.25µm HCMOS7 TECHNOLOGY
■ 144 PIN TQFP
■ POWER CONSUMPTION: 0.4 WATT
APPLICATIONS
Routers at SOHO, stand-alone modems, PC
modems.
TQFP144 Full Plastic
(20 x 20 x 1.40 mm)
ORDER CODE: ST70235A
October 2001
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/28
ST70235A
Figure 1 : Block Diagram
TEST SIGNALS
CLOCK
TEST MODULE
AFE
INTERFACE
AFE
CONTROL
DSP
FRONT-END
DATA SYMBOL TIMING UNIT
AFE CONTROL
INTERFACE
GENERIC
TC
REED/
SOLOMON
TRELLIS
CODING
MAPPER/
DEMAPPER
FFT/IFFT
ROTOR
VCXO
CONTROLLER
INTERFACE
CONTROLLER
BUS
INTERFACE
MODULE
UTOPIA
ATM
SPECIFIC TC
GENERAL
PURPOSE I/Os
Transient Energy Capabilities
ESD (Electronic Discharged) tests have been performed for the Human Body Model (HBM) and for the
Charged Device Model (CDM).
The pins of the device are to be able to withstand minimum 2000V for the HBM and minimum 250V for
CDM.
Latch-up
The maximum sink or source current from any pin is limited to 200mA to prevent latch-up.
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD 3.3
Supply Voltage
3.0
3.3
3.6
V
VDD 1.8
Supply Voltage
1.62
1.8
1.98
V
Ptot
Total Power Dissipation
300
400
mW
Tamb
Ambient Temperature 1m/s airflow
70
°C
Rth J/A
Thermal Resistivity
I3.3
Current Consumption
14
mA
I1.8
Current Consumption
135
mA
2/28
0
38
°C/W
ST70235A
VSS
RESERVED
RESERVED
TDI
TDO
TMS
VDD 3.3
TCK
VSS
TRSTB
TESTSE
GP_OUT
PDOWN
VDD 3.3
AFRXD_0
AFRXD_1
AFRXD_2
AFRXD_3
VSS
CLWD
MCLK
CTRLDATA
VDD 3.3
COMP_VDD_1.8
COMP_ROUT
VSS
DISABLE_COMP
RESERVED
VDD 1.8
IDDq
AFTXD_0
AFTXD_1
VSS
AFTXD_2
AFTXD_3
VDD 3.3
Figure 2 : Pin Connection
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
VSS
1
108
VDD 1.8
AD_0
2
107
RESERVED
AD_1
3
106
RESERVED
AD_2
4
105
RESERVED
VDD 3.3
5
104
RESERVED
AD_3
6
103
RESERVED
AD_4
7
102
VSS
VSS
8
101
RESERVED
AD_5
9
100
RESERVED
AD_6
10
99
RESERVED
VDD 3.3
11
98
RESERVED
AD_7
12
97
RESERVED
AD_8
13
96
RESERVED
AD_9
14
95
VDD 3.3
VSS
15
94
RESERVED
AD_10
16
93
RESERVED
AD_11
17
92
RESERVED
VDD 1.8
18
91
VSS
AD_12
19
90
RESERVED
VSS
20
89
U_TX_ADDR_0
PCLK
21
88
U_TX_ADDR_1
VDD 3.3
22
87
U_TX_ADDR_2
AD_13
23
86
VDD 1.8
AD_14
24
85
U_TX_ADDR_3
AD_15
25
84
U_TX_ADDR_4
VSS
26
83
U_TX_DATA_0
BE1
27
82
U_TX_DATA_1
ALE
28
81
VDD 1.8
VDD 3.3
29
80
U_TX_DATA_2
CSB
30
79
U_TX_DATA_3
WR_RDB
31
78
U_TX_DATA_4
RDYB
32
77
U_TX_DATA_5
OBC_TYPE
33
76
VDD 3.3
INTB
34
75
U_TX_DATA_6
RESETB
35
74
U_TX_DATA_7
VSS
36
73
VSS
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VDD 3.3
U_RXDATA_0
U_RXDATA_1
VSS
U_RXDATA_2
U_RXDATA_3
VDD 1.8
U_RXDATA_4
U_RXDATA_5
VSS
U_RXDATA_6
U_RXDATA_7
VDD 3.3
U_RX_ADDR_0
U_RX_ADDR_1
U_RX_ADDR_2
U_RX_ADDR_3
VSS
U_RX_ADDR_4
GP_IN0
VDD 3.3
GP_IN1
VSS
U_RX_REFB
U_TX_REFB
VDD 1.8
U_RXCLK
U_RXSOC
U_RXCLAV
U_RXENBB
VSS
U_TXCLK
U_TXSOC
U_TX_CLAV
U_TXENBB
VDD 3.3
ST70235A
3/28
ST70235A
PIN FUNCTIONS
Pin
Name
Type
PAD Type
HCMOS7
BS
Function
1
VSS
2
AD_0
B
BD8STARP
B
Data 0
3
AD_1
B
BD8STARP
B
Data 1
4
AD_2
B
BD8STARP
B
5
VDD 3.3
6
AD_3
B
BD8STARP
B
7
AD_4
B
BD8STARP
B
8
VSS
9
AD_5
B
BD8STARP
B
10
AD_6
B
BD8STARP
B
11
VDD 3.3
12
AD_7
B
BD8STARP
B
Address / Data 7
13
AD_8
B
BD8STARP
B
Address / Data 8
14
AD_9
B
BD8STARP
B
Address / Data 9
15
VSS
16
AD_10
B
BD8STARP
B
Address / Data 10
17
AD_11
B
BD8STARP
B
Address / Data 11
18
VDD 1.8
19
AD_12
20
VSS
21
PCLK
22
VDD 3.3
23
AD_13
B
BD8STARP
B
Address / Data 13
24
AD_14
B
BD8STARP
B
Address / Data 14
25
AD_15
B
BD8STARP
B
Address / Data 15
26
VSS
27
BE1
I
TLCHT
I
Address 1
28
ALE
I
TLCHT
C
Address Latch
29
VDD 3.3
30
CSB
I
TLCHT
I
Chip Select
31
WR_RDB
I
TLCHT
I
Specifies the direction of the access cycle
32
RDYB
OZ
BD4STARP
O
Controls the ATC bus cycle termination
33
OBC_TYPE
I-PD
TLCHTDQ
I
ATC Mode Selection (0 = i960; 1 = generic)
34
INTB
O
BD4STARP
O
Requests ATC interrupt service
35
RESETB
I
TLCHT
I
Hard reset
36
VSS
0V Ground
37
VDD 3.3
(VSS + 3.3V) Power Supply
38
U_RxData_0
OZ
BD8STARP
B
39
U_RxData_1
OZ
BD8STARP
B
40
VSS
4/28
0V Ground
Address / Data 2
(VSS + 3.3V) Power Supply
Address / Data 3
Address / Data 4
0V Ground
Address / Data 5
Address / Data 6
(VSS + 3.3V) Power Supply
0V Ground
(VSS + 1.8V) Power Supply
B
BD8STARP
B
Address / Data 12
0V Ground
I
TLCHT
I
Processor clock
(VSS + 3.3V) Power Supply
0V Ground
(VSS + 3.3V) Power Supply
Utopia RX Data 0
Utopia RX Data 1
0V Ground
ST70235A
PIN FUNCTIONS (continued)
Pin
Name
Type
PAD Type
HCMOS7
BS
Function
41
U_RxData_2
OZ
BD8STARP
B
Utopia RX Data 2
42
U_RxData_3
OZ
BD8STARP
B
43
VDD 1.8
44
U_RxData_4
OZ
BD8STARP
B
45
U_RxData_5
OZ
BD8STARP
B
46
VSS
47
U_RxData_6
OZ
BD8STARP
B
48
U_RxData_7
OZ
BD8STARP
B
49
VDD 3.3
50
U_RxADDR_0
I
TLCHT
I
Utopia RX Address 0
51
U_RxADDR_1
I
TLCHT
I
Utopia RX Address 1
52
U_RxADDR_2
I
TLCHT
I
Utopia RX Address 2
53
U_RxADDR_3
I
TLCHT
I
Utopia RX Address 3
54
VSS
55
U_RxADDR_4
I
TLCHT
I
Utopia RX Address 4
56
GP_IN_0
I-PD
TLCHTDQ
I
General purpose input 0
57
VDD 3.3
58
GP_IN_1
I-PD
TLCHTDQ
I
General purpose input 1
59
VSS
60
U_RxRefB
O
BD4STARP
O
8kHz clock to ATM device
61
U_TxRefB
I
TLCHT
I
8kHz clock from ATM device
62
VDD 1.8
63
U_Rx_CLK
I
TLCHT
64
U_Rx_SOC
OZ
BD8STARP
65
U_RxCLAV
OZ
BD8STARP
66
U_RxENBB
I
TLCHT
67
VSS
68
U_Tx_CLK
I
TLCHT
Utopia TX Clock
69
U_Tx_SOC
I
TLCHT
Utopia TX Start of Cell
70
U_TxCLAV
OZ
BD8SCR
71
U_TxENBB
I
TLCHT
72
VDD 3.3
(VSS + 3.3V) Power Supply
73
VSS
0V Ground
74
U_TxData_7
I
TLCHT
I
Utopia TX Data 7
75
U_TxData_6
I
TLCHT
I
Utopia TX Data 6
76
VDD 3.3
77
U_TxData_5
I
TLCHT
I
Utopia TX Data 5
78
U_TxData_4
I
TLCHT
I
Utopia TX Data 4
79
U_TxData_3
I
TLCHT
I
Utopia TX Data 3
80
U_TxData_2
I
TLCHT
I
Utopia TX Data 2
Utopia RX Data 3
(VSS + 1.8V) Power Supply
Utopia RX Data 4
Utopia RX Data 5
0V Ground
Utopia RX Data 6
Utopia RX Data 7
(VSS + 3.3V) Power Supply
0V Ground
(VSS + 3.3V) Power Supply
0V Ground
(VSS + 1.8V) Power Supply
Utopia RX Clock
Utopia RX Start of Cell
Utopia RX Cell Available
Utopia RX Enable
0V Ground
Utopia TX Cell Available
Utopia TX Enable
(VSS + 3.3V) Power Supply
5/28
ST70235A
PIN FUNCTIONS (continued)
Pin
Name
Type
PAD Type
HCMOS7
BS
Function
81
VDD 1.8
(VSS + 1.8V) Power Supply
82
U_TxData_1
I
TLCHT
I
Utopia TX Data 1
83
U_TxData_0
I
TLCHT
I
Utopia TX Data 0
84
U_TxADDR_4
I
TLCHT
I
Utopia TX Address 4
85
U_TxADDR_3
I
TLCHT
I
Utopia TX Address 3
86
VDD 1.8
87
U_TxADDR_2
I
TLCHT
I
Utopia TX Address 2
88
U_TxADDR_1
I
TLCHT
I
Utopia TX Address 1
89
U_TxADDR_0
I
TLCHT
I
Utopia TX Address 0
90
RESERVED
91
VSS
92
RESERVED
BD4STARP
Reserved 1
93
RESERVED
BD4STARP
Reserved 2
94
RESERVED
BD4STARP
95
VDD 3.3
96
RESERVED
BD4STARP
Reserved 4
97
RESERVED
BD4STARP
Reserved 5
98
RESERVED
BD4STARP
Reserved 6
99
RESERVED
BD4STARP
Reserved 7
100
RESERVED
BD4STARP
Reserved 8
101
RESERVED
BD4STARP
Reserved 9
102
VSS
103
RESERVED
TLCHTDQ
Reserved 10
104
RESERVED
TLCHTDQ
Reserved 11
105
RESERVED
TLCHTDQ
Reserved 12
106
RESERVED
TLCHTDQ
Reserved 13
107
RESERVED
BD4STARP
Reserved 14
108
VDD 1.8
(VSS + 1.8V) Power Supply
109
VSS
0V Ground
110
RESERVED
(VSS + 1.8V) Power Supply
BD4STARP
Reserved 0
0V Ground
Reserved 3
(VSS + 3.3V) Power Supply
0V Ground
BD4STARP
Reserved 15
111
RESERVED
BD4STARP
Reserved 16
112
TDI
I-PU
TLCHTUQ
JTAG I/P
113
TDO
OZ
BD4STARP
JTAG O/P
114
TMS
I-PU
TLCHTUQ
JTAG Made Select
115
VDD 3.3
116
TCK
117
VSS
118
TRSTB
119
120
6/28
(VSS + 3.3V) Power Supply
I-PD
TLCHTDQ
JTAG Clock
I-PD
TLCHTDQ
JTAG Reset
TESTSE
I
TLCHTDQ
none
Enables scan test mode
GP_OUT
O
BD8STARP
O
General purpose output
0V Ground
ST70235A
PIN FUNCTIONS (continued)
Pin
Name
Type
PAD Type
HCMOS7
BS
O
BD4STARP
O
Power down analog front end (Reset)
Function
121
PDOWN
122
VDD 3.3
123
AFRXD_0
I
TLCHT
I
Receive data nibble
124
AFRXD_1
I
TLCHT
I
Receive data nibble
125
AFRXD_2
I
TLCHT
I
Receive data nibble
126
AFRXD_3
I
TLCHT
I
Receive data nibble
127
VSS
128
CLWD
I
TLCHT
I
Start of word indication
129
MCLK
I
TLCHT
C
Master clock
130
CTRLDATA
O
BD4STARP
O
Serial data Transmit channel
131
VDD 3.3
132
COMP_VDD_1.8
133
COMP_ROUT
134
VSS
135
DISABLE_COMP
136
RESERVED
137
VDD 1.8
138
IDDq
I
TLCHT
none
Test pin, active high
139
AFTXD_0
O
BD8STARP
O
Transmit data nibble
140
AFTXD_1
O
BD8STARP
O
Transmit data nibble
141
VSS
142
AFTXD_2
O
BD8STARP
O
Transmit data nibble
143
AFTXD_3
O
BD8STARP
O
Transmit data nibble
144
VDD 3.3
(VSS + 3.3V) Power Supply
0V Ground
(VSS + 3.3V) Power Supply
COMP_1V60
O
COMP_1V60
Compensation Cell VDD 1.8V (see note 1)
none
COMP_1V60
I
Compensation Cell Resistor (see note 1)
0V Ground
TLCHTDQ
Disable Compensation Cell (see note 1)
Reserved
(VSS + 1.8V) Power Supply
0V Ground
(VSS + 3.3V) Power Supply
Note: Compensation cell - The COMP_OUT pin must be connected at GND by a 100K Ω resistor on board.
Specifications of the resistor have to meet the following requirements:
± 5% allowed on the value, ±1% is preferred.
Advice is given to place the resistor so that there will be the shortest path between it and the pin.
Using the DISABLE_COMP signal is possible to disable the slew rate control of IOs, in this mode the IOs are however still functional,
but dynamic performances are affected.
An internal pull-down on DISABLE_COMP pin enables the slew rate control of IOs, an external pull-up resistor (connected at 3.3V)
must be inserted in order to disable the slew rate control.
Table 1 : I/O Driver Function
Driver
Function
BD4STARP
TTL Three Volt capable Schmitt Trigger Bidirectional Pad Buffer, 4mA, with Test pins, with Active Slew
Rate Control
BD8STARP
TTL Three Volt capable Schmitt Trigger Bidirectional Pad Buffer, 8mA, with Test pins, with Active Slew
Rate Control
TLCHTDQ
TTL Three Volt capable Input Buffer with Active Pull-Down and Test pin
TLCHTUQ
TTL Three Volt capable Input Buffer with Active Pull-Up and Test pin
TLCHT
TLL Three Volt capable Input Pad Buffer
7/28
ST70235A
PIN SUMMARY
Mnemonic
Type
BS Type ofNumber
Signals
Function
Power Supply
VDD 3.3
VDD 1.8
(VSS + 3.3V) Power supply
(VSS + 1.8V) Power supply
VSS
0V Ground
ATC INTERFACE
ALE
I
C
1
Used to latch the address of the internal register to be accessed
PCLK
I
I
1
Processor clock
CSB
I
I
1
Chip selected to respond to bus cycle
BE1
I
I
1
Address 1 (not multiplexed)
WR_RDB
I
I
1
Specifies the direction of the access cycle
RDYB
OZ
O
1
Controls the ATC bus cycle termination
INTB
O
O
1
Requests ATC interrupt service
IO
B
16
Multiplexed Address/Data bus
I-PD
I
1
Select between i960 (0) or generic (1) controller interface
Refer to section
AD
OBC_TYPE
TEST ACCESS PART INTERFACE
TDI
I-PU
1
TDO
OZ
1
TCK
I-PD
1
TMS
I-PU
1
TRSTB
I-PD
1
ANALOG FRONT END INTERFACE
AFRXD
I
I
4
Receive data nibble
AFTXD
O
O
4
Transmit data nibble
CLWD
I
I
1
Start of word indication
PDOWN
O
O
1
Power down analog front end
CTRLDATA
O
O
1
Serial data transmit channel
MCLK
I
C
1
Master cloc
ATM UTOPIA INTERFACE
U_RxData
OZ
B
8
Receive interface Data
U_TxData
I
I
8
Transmit interface Data
U_RxADDR
I
I
5
Receive interface Address
U_TxADDR
I
I
5
Transmit interface Address
U_RxCLAV
OZ
O
1
Receive interface Cell Available
U_TxCLAV
OZ
O
1
Transmit interface Cell Available
U_RxENBB
I-TTL
I
1
Receive interface Enable
U_TxENBB
I-TTL
I
1
Transmit interface Enable
U_RxSOC
OZ
O
1
Receive interface Start of Cell
U_TxSOC
I-TTL
I
1
Transmit interface Start of Cell
U_RxCLK
I-TTL
C
1
Receive interface Utopia Clock
U_TxCLK
I-TTL
C
1
Transmit interface Utopia Clock
U_RxRefB
O
O
1
8kHz reference clock to ATM device
U_TxRefB
I-TTL
I
1
8kHz reference clock from ATM device
8/28
ST70235A
PIN SUMMARY (continued)
Type
BS Type
Number
of Signals
I-PD
I
2
GP_OUT
O
O
1
General purpose output
RESETB
I
I
I
Hard reset
TESTSE
I
none
none
Enable scan test mode
IDDq
I
none
none
Test pin, active high
COMP_ROUT
O
none
1
Compensation cell resistor
I-PD
I
1
Disable compensation cell
Mnemonic
Function
MISCELLANEOUS
GP_IN
DISABLE_COMP
General purpose input
I
I-PU
= Input, CMOS levels
= Input with pull-up resistance, TTL
levels
I-PD
= Input with pull-down resistance, TTL
levels
I-TTL = Input TTL levels
O
= Push-pull output
OZ
= Push-pull output with high-impedance
state
IO
= Input / Tristate Push-pull output
BS cell = Boundary-Scan cell
I
= Input cell
O
= Output cell
B
= Bidirectional cell
C
= Clock
Main Block Description
The following drawings describe the sequence of
functions performed by the chip.
DSP Front-End
The DSP Front-End contains 4 parts in the
receive direction: the Input Selector, the Analog
Front-End Interface, the Decimator and the Time
Equalizer.
The input selector is used internally to enable test
loopbacks inside the chip. The Analog Front-End
lnterface transfers 16-bit words, multiplexed on 4
input/output signals. Word transfer is carried out in
4 clock cycles.
The Decimator receives 16-bit samples at 8.8MHz
(as sent by the Analog Front-End chip: ST70134)
and reduces this rate to 2.2MHz.
The Time Equalizer (TEQ) module is a FIR filter
with programmable coefficients. Its main purpose
is to reduce the effect of Inter-Symbol
Interferences (ISI) by shortening the channel
impulse response.
Both the Decimator and TEQ can be bypassed. In
the transmit direction, the DSP Front-End
includes: sidelobe filtering, clipping, delay
equalization and interpolation. The sidelobe
filtering and delay equalization are implemented
by IIR Filters, reducing the effect of echo in FDM
systems.
Clipping is a statistical process limiting the
amplitude of the output signal, optimizing the
dynamic range of the AFE. The interpolator
receives data at 2.2MHz and generates samples
at a rate of 8.8MHz.
DMT Modem
This module is a programmable DSP unit. Its
instruction set enables the basic functions of the
DMT algorithm like FFT, IFFT, Scaling, Rotor and
Frequency Equalization (FEQ) in compliance with
ANSI T1.413 specifications.
In the RX path, the 512-point FFT transforms the
time-domain DMT symbol into a frequency
domain representation which can be further
decoded by the subsequent demapping stages.
In other words, the Fast Fourier Transform
process is used to transform from time domain to
frequency domain (receive path). 1024 time
samples are processed. After the first stage time
domain equalization and FFT block an ICI
(InterCarrier Interference) free information stream
turns out.
9/28
ST70235A
Figure 3 : DSP Front-End Receive
BYPASS
From
Analog
Front-end
IN
SELECT
AFE
I/F
DEC
TEC
To DMT
Modem
Figure 4 : DSP Front-End Transmit
From
DMT
Modem
FILTERING
CLIPPING
DELAY
EQUALIZER
INTERPOLATOR
AFE
I/F
OUT
SELECT
To Analog
Front End
Figure 5 : DMT Modem (Rx & Tx)
TREILLIS
CODING
DECODING
To/From
DSP FE
FFT
IFFT
FEQ
FTG
ROTOR
FEQ COEFFICIENTS
FEQ Update
This stream is still affected by carrier specific
channel distortion resulting in an attenuation of
the signal amplitude and a rotation of the signal
phase. To compensate, a Frequency domain
equalizer (FEQ) and a Rotor (phase shifter) are
implemented. The frequency domain equalization
performs an operation on the received vector in
order to match it with the associated point in the
constellation. The coefficient used to perform the
equalization are floating point, and may be
updated by hardware or software, using a
mechanism of active and inactive table to avoid
DMT synchro problems.In the transmit path, the
10/28
MAPPER
DEMAPPER
To/From
TC
MONITOR
Monitor Indications
IFFT reverses the DMT symbol from frequency
domain to time domain.
The IFFT block is preceded by Fine Tune Gain
(FTG) and Rotor stages, allowing for a
compensation of the possible frequency mismatch
between the master clock frequency and the
transmitter clock frequency (which may be locked
to another reference).
The Inverse Fast Fourier Transform process is
used to transform from frequency domain to time
domain (transmit path). 256 positive frequencies
are processed, giving 512 samples in the time
domain.
ST70235A
The FFT module is a slave DSP engine controlled
by the firmware running on an external controller.
It works off line and communicates with other
blocks through buffers controlled by the "Data
Symbol Timing Unit". The DSP executes a
program stored in a RAM area, which constitutes
a flexible element that allows for future system
enhancements.
signal power, pilot phase deviations, symbol
erasures generation, loss of frame, etc.
DPLL
The Digital PLL module receives a metric for the
phase error of the pilot tone. In general, the clock
frequencies at the ends (transmitter and receiver)
do not match exactly. The phase error is filtered
and integrated by a low pass filter, yielding an
estimation of the frequency offset. Various
processes can use this estimate to deal with the
frequency mismatch.
In particular, small accumulated phase error can
be compensated in the frequency domain by a
rotation of the received code constellation (Rotor).
Larger errors are compensated in the time domain
by inserting or deleting clock cycles in the sample
input sequence.
Eventually that leads to achieve less than 2ppm
between the two ends.
The data received from the demapper may be
split into two paths, one dedicated to an
interleaved data flow the other one for a fast data
flow. No external RAM is needed for the
interleaved path.
Mapper/Demapper, Monitor, Trellis Coding,
FEQ Update
The Demapper converts the constellation points
computed by the FFT to a block of bits. This
means to identify a point in a 2D QAM
constellation plane. The Demapper supports
Trellis coded demodulation and provides a Viterbi
maximum likelihood estimator. When the Trellis is
active, the Demapper receives an indication for
the most likely constellation subset to be used.
In the transmit direction, the mapper receives a bit
stream from the Trellis encoder and modulates
the bit stream on a set of carriers (up to 256). It
generates coordinates for 2n QAM constellation,
where n < 15 for all carriers.
The Mapper performs the inverse operation,
mapping a block of bits into one constellation
point (in a complex x+jy representation) which is
passed to the IFFT block. The Trellis Encoder
generates redundant bits to improve the
robustness of the transmission, using a
4-Dimensional Trellis Coded Modulation scheme.
This feature can be disabled.The Monitor
computes error parameters for carriers specified
in the Demapper process. Those parameters can
be used for updates of adaptive filters coefficients,
clock phase adjustments, error detection, etc. A
series of values is constantly monitored, such as
Generic TC Layer Functions
These functions relate to byte oriented data
streams. They are completely described in ANSI
T 1.4 13. Additions described in the Issue 2 of this
specification are also supported.
The interleaving/deinterleaving is used to
increase the error correcting capability of block
codes for error bursts.
After deinterleaving (if applicable), the data flow
enters a Reed-Solomon error correcting code
decoder, able to correct a number of bytes
containing bit errors.
The decoder also uses the information of previous
receiving stages that may have detected the error
bytes and have labelled them with an "erasure
indication". Each time the RS decoder detects and
corrects errors in a RS codeword, an RS
correction event is generated.
The occurrence of such events can be signalled to
the management layer.After the RS decoder, the
corrected byte stream is descrambled in the PMD
(Physical Medium Dependent) descramblers. Two
descramblers are used, for interleaved and
non-interleaved data flows. These are defined in
ANSI T1.413. After descrambling, the data flows
enter the Deframer that extracts and processes
bytes to support Physical layer related functions
according to ANSI T1.413. The ADSL frames
indeed contain physical layer-related information
in addition to the data passed to the higher layers.
In particular, the deframer extracts the EOC
(Embedded Operations Channel), the AOC
(ADSL Overhead Control) and the indicators bits
and passes them to the appropriate processing
unit (e.g. the transceiver controller). The deframer
also performs a CRC check (Cyclic Redundancy
Check) on the received frame and generates
events in case of error detection.Event counters
can be read by management processes.
The outputs of the deframer are an interleaved
and a fast data streams. These data streams can
either carry ATM cells or another type of traffic. In
the latter case, the ATM specific TC layer
functional block, described hereafter, is bypassed
and the data stream is directly presented at the
input of the interface module.
11/28
ST70235A
Figure 6 : Generic TC Layer Functions
Indication Bits AOC EOC
To/From
Demapper
FAST
F
DATA PATX MERGER
RS
CODING
DECODING
INTERLEAVER
DE-INTERLEAVER
ATM Specific TC Layer Functions
The 2 bytes streams (fast and slow) are received
from the byte-based processing unit. When ATM
cells are transported, this block provides basic cell
functions such as cell synchronization, cell
payload descrambling, idle/unassigned cell filter,
cell Header Error Correction (HEC) and detection.
The cell processing happens according to ITU-T
I.163 standard. Provision is also made for BER
I
PMD
SCRAMBLER
DESCRAMBLER
F
FRAMER
DEFRAMER
I
PMD
SCRAMBLER
DESCRAMBLER
measurements at this ATM cell level. When non
cell oriented byte streams are transported, the cell
processing unit is not active. The interface module
collects cells (from the cell-based function
module). Cells are stored in FIFO’s (424 bytes or
8 cell wide, transmit buffers have the same size),
from which they are extracted by 2 interface
submodules, one providing a Utopia level 1
interface and the other a Utopia level 2 interface.
Figure 7 : ATM Specific TC Layer Functions
BER
FAST
From
Generic
TC
SLOW
CELL SCRAMBLER
DESCRAMBLER
SYNCHRONIZER
HEC
CELL SCRAMBLER
DESCRAMBLER
SYNCHRONIZER
HEC
CELL
INSERTION/
FILTER
CELL
INSERTION/
FILTER
BER
Figure 8 : Interface Module
UTOPIA
LEVEL
1
UTOPIA
LEVEL
2
UTOPIA
LEVEL
1
UTOPIA
LEVEL
2
FAST ATM
From
ATM
TC
SLOW ATM
12/28
To
ATM
TC
To
Interface
Module
ST70235A
DMT Symbol Timing Unit (DSTU)
Data and addresses are multiplexed
The DSTU interfaces with various modules, like
DSP FrontEnd, FFT/IFFT, Mapper/Demapper, RS,
Monitor and Transceiver Controller. It consists of a
real time and a scheduler modules.
ST70235A works in 16 bits data access, so
address bit 0 is not used. Address bit 1 is not
multiplexed with data. It has its own pin : BE1.
The real time unit generates a timebase for the
DMT symbols (sample counter), superframes
(symbol counter) and hyper-frames (sync
counter). The timebases can be modified by
various control features. They are continuously
fine-tuned by the DPLL module.
Byte access are not supported. Access cycle read
or write are always in 16 bits data wide, ie bit
address A0 is always zero value.
The DSTU schedulers execute a program,
controlled by program opcodes and a set of
variables, the most important of which are real
time counters.
The interrupt request pin to the processor is INTB,
and is an Open Drain output.
The ST70235A supports both little and big endian.
The default feature is big endian.
Figure 9 : ST70235A Interfaces
The transmit and receive sequencers are
completely independent and run different
programs. An independent set of variables is
assigned to each of them. The sequencer
programs can be updated in real time.
AFE INTERFACE TO ADSL LINE (ST70134)
RESET
JTAG
CLOCK
PROCESSOR
INTERFACE
(ATC)
ST70235A
ST70235A interfaces
Overview
DIGITAL INTERFACE UTOPIA
See Figure 9.
Generic Interface
Processor Interface (ATC)
The ST70235A is controlled and configured by an
external processor across the processor interface.
All programmable coefficients and parameters are
loaded through this path.
This interface is suitable for a number of
processors using a multiplexed Address/data bus.
In this case, synchronization of the input signals
with PCLK pin is not necessary.
Figure 10 : Generic Processor Interface Write Timing Cycle
MClk
ALE
Talew
Tale2cs
CSB
Trdy2cs
Tavs Tavh
Address/DATA
Twr2Mclk
Twr2d
WRB
1
Tcs2wr
RDYB
Trdy2wr
Twr2rdy
1: RDB = WR_RDB is high.
Tcsre
Tmclk
13/28
ST70235A
Figure 11 : Generic Processor Interface Read Timing Cycle
MClk
Tale2Z
Talew
ALE
Tale2cs
T rdy2cs
CSB
Tavh
Tavs
Address/DATA
T rd2Mclk
RDB
Tdvs
T dvh
T cs2rd
1
Twrw
RDYB
T rdy2rd
T rd2rdy
1: WRB = BE1 is high.
T csre
Tmclk
Generic processor interface Cycle Timing
All AC characteristics are indicated for a 100pF capacitive load.Cycle timing for generic interface.
Table 2 : Cycle timing
Symbol
Parameters
Minimum
Maximum
Unit
900
µs
Tcsre
Access Time
Talew
Ale pulse width
12
ns
Tavs
Address valid setup time
10
ns
Tavh
Address valid hold time
10
ns
Tale2cs
ALE to CSB
0
ns
Tale2Z
ALE to high Z state of bus
Tcs2wr
CSB to WRB
0
Tcs2rd
CSB to RDB
0
Twr2d
WR to data
15
ns
Twr2rdy
WR to Dy asserted
60
ns
Trd2rdy
RD to Rdy asserted
60
ns
Trdy2wr
Rdyb to WRB
0
ns
Trdy2rd
Rdyb to RDB
0
ns
Tdvs
Data valid setup time
10
ns
Tdvh
Data valid hold time
1/2 Tmclk
Trdy2cs
RdyB to CSB
Tmclk
master clock timing : cf specifications
Twr2Mclk
Trd2Mclk
50
ns
ns
ns
Tmclk
ns
0
ns
Setup time according to the master clock
10
ns
Setup time according to the master clock
10
ns
The timing are generally presented with the write signal, but as shown on the read diagram, they are also
valid for the read signal, so for example the Trdy2wr timing is the same as what can be Trdy2rd.
14/28
ST70235A
Figure 12 : Receive Interface
Generic Processor Interface Pins and
Functional Description
Name
AD[0..15]
PHY
Type
Function
I/O
Multiplexed address / data bus
ATM
RxREF*
RxCLAV
ALE
I
Address Latch Enable
RDB
I
Read cycle indication
WRB
I
Write cycle indication
RxDATA
CSB
I
Chip Select
RxSOC
RDYB
OZ
INTB
O
RxENB*
PHY
RECEIVE
8
Bus cycle ready indication
Interrupt
Figure 13 : Transmit Interface
Digital interface ATM or serial
Digital Interface
before modulation
demodulation.
CELL
RECEIVE
RxCLK
for
and
data to
from the
the
loop
loop
after
PHY
ATM LAYER
TxREF*
TxCLAV
This interface collects cells (from the cell based
function module) or a byte stream (from the
deframer).
Cells are stored in a fifo, 2 interfaces submodules
can extract data from the fifo.
TxENB*
PHY
TRANSMIT
CELL
TRANSMIT
TxCLK
TxDATA
8
TxSOC
2 kinds of interface are allowed:
– Utopia Level 1
– Utopia Level 2
The interface selection is programmed by writing
the Utopia PHY address register.
Only one interface can be enabled in a ST70235A
configuration.
Utopia Level 1 supports only one PHY device.
Utopia Level 2 supports multi-PHY devices (See
Utopia Level 2 specifications).
Each buffer provides storage for 8 ATM cells (both
directions for Fast and Interleaved channel).
The Utopia Level 2 supports point to multipoint
configurations by introducing an addressing
capability and by making distinction between
polling and selecting a device.
Utopia Level 1 Interface
The ATM forum takes the ATM layer chip as a
reference. It defines the direction from ATM to
physical layer as the Transmit direction. The
direction from physical layer to ATM is the
Receive direction.
Figures 12 & 13 show the interconnection
between ATM and PHY layer devices, the optional
signals are not supported and not shown. The
Utopia interface transfers one byte in a single
clock cycle, as a result cells are transformed in 53
clock cycles.
Both transmit and receive are synchronized on
clocks generated by the ATM layer chip, and no
specific relationship between receive and transmit
clocks is required. In this mode, the ST70235A
can only support one data flow : either interleaved
or fast.
15/28
ST70235A
Figure 14 : Timing (Utopia 2 Receive Interface)
Detection
Selection
Polling
Polling
Polling:
1
2
3
4
5
6
7
1F N-3
1F
N+1
1F
N-1
1F
8
9
10
11
12
13
14
15
16
17
18
1F
N+3
1F
N-1
1F
N-3
1F
N-3
1F
N+1
19
20
RxClk
RxAddr
N
N-3
RxClav
N-3
N+1
P43 P44
P45
N-1
N
N+3
N-3
1F
N+2
N+1
N-1
RxEnb*
RxData P41 P42
P46
P47
P48
XX
H1
H2
H3
RxSOC
Cell transmission from:
PHY N
PHY N-3
Pin Description
Name
Type
Meaning
Usage
Remark
RxClav
O
Receive Cell available
Signals to the ATM chip that the ST70235A
has a cell ready for transfer
Remains active for the entire
cell transfer
RxEnb 1
I
Receive Enable
Signals to the ST70235A that the ATM chip
will sample and accept data during next
clock cycle
RxData and RxSOC could be
tri-state when RxEnb* is
inactive (high). Active low
signal
RxClk
I
Receive Byte Clock
Gives the timing signal for the transfer,
generated by ATM layer chip.
RxData
O
Receive Data (8bits)
ATM cell data, from ST70235A chip to ATM
chip, byte wide. Rx Data [7] is the MSB.
RxSOC
O
Receive Start Cell
Identifies the cell boundary on RxData
Indicate to the ATM layer
chip that RxData contains
the first valid byte of a cell
RxRef 1
O
Reference Clock
8 kHz clock transported over the network
Active low signal
Note
1. Active low signal
When RxEnb is asserted, the ST70235A reads data from its internal fifo and presents it on RxData and
RxSOC on each low-to-high transition of RxClk, ie the ATM layer chip samples all RxData and RxSOC on
the rising edge of RxSOC on the rising edge of RxClk.
16/28
ST70235A
Pin Description
Name
Type
Meaning
Usage
Remark
TxClav
O
Transmit Cell
available
Signals to the ATM chip that the physical
Remains active for the entire
layer chip is ready to accept a complete cell cell transfer
TxEnb 1
I
Transmit Enable
Signals to the ST70235A that TxData and
TxSOC are valid
TxClk
I
Transmit Byte Clock
Gives the timing signal for the transfer,
generated by ATM layer chip.
TxData
I
Transmit Data (8bits)
ATM cell data, from ATM layer chip to
ST70235A, byte wide. TxData [7] is the MSB.
TxSOC
I
Transmit Start of Cell
Identifies the cell boundary on TxData
TxRef 1
I
Reference Clock
8kHz clock from the ATM layer chip
Note
TxData contains the first
valid byte of the cell.
1. Active low signal
The ST70235A samples TxData and TxSOC signals on the rising edge of TxClk, if TxEnb is asserted.
TxClk, RxClk, AC Electrical Characteristics
Symbol
Parameters
Minimum
Maximum
Unit
F
Clock frequency
1.5
25
MHz
Tc
Clock duty cycle
40
60
%
Tj
Clock peak to peak jitter
5
%
Trf
Clock rise fall time
4
ns
L
Load
100
pF
Maximum
Unit
TxData, TxSOC, TxAddr, TxEnb, AC Electrical Characteristics
Symbol
Parameters
Minimum
T5
Input set-up time to TxClk
10
ns
T6
Hold time to TxClk
1
ns
L
Load
100
pF
Maximum
Unit
Note: Tx data hold time is 1.2ns. All the UTOPIA hold time are guarantee by design.
RxData, RxSOC, RxClav, TxClav, AC Electrical Characteristics
Symbol
Parameters
Minimum
T7
Input set-up time to TxClk
10
ns
T8
Hold time to Tx Clk
1
ns
T9
Signal going low impedance to RxClk
10
ns
T10
Signal going High impedance to RxClk
0
ns
T11
Signal going low impedance to RxClk
1
ns
T12
Signal going High impedance to RxClk
1
ns
L
Load
100
pF
17/28
ST70235A
RxAddr, RxEnb, AC Electrical Characteristics
Symbol
Parameters
Minimum
Maximum
Unit
T5
Input setup time to RxClk
10
ns
T6
Hold time to RxClk
1
ns
L
Load
100
pF
Figure 15 : Timing (Utopia 2 Transmit Interface)
Detection
Selection
Polling
Polling
Polling:
1
2
3
1F N+1
1F
4
5
6
7
8
9
10
11
1F
N+2
1F
N-1
1F
12
13
14
15
16
1F
N+3
1F
N+3
17
18
19
20
N-2
1F
N-3
TxClk
TxAddr
N
1F
N+3
N
N+3
TxClav
N+1
N
N+3
N+2
N-1
1F
N+3
N+1
N
N-2
TxEnb*
TxData
P45
P46 P47
H1
P48
H2
H3
TxSOC
Cell transmission from:
PHY N
PHY N+3
Figure 16 : Timing Specification (Utopia 2)
Clock
T6, T8
T5, T7
Signal
(at input)
Signal
(highz)
T11
18/28
T9
T12
T10
H4
ST70235A
DIGITAL INTERFACE
Utopia Level 2 Interface
The ATM forum takes the ATM layer chip as a
reference. It defines the direction from ATM to
physical layer as the Transmit direction. The
direction from physical layer to ATM is the Receive
direction. Figure 17 shows the interconnection
between ATM and PHY layer devices, the optional
signals are not supported and not shown.
The UTOPIA interface transfers one byte in a
single clock cycle, as a result cells are transferred
in 53 clock cycles.Both transmit and receive
interfaces are synchronized on clocks generated
by the ATM layer chip, and no specific relationship
between Receive and Transmit clock is assumed,
they must be regarded as mutually asynchronous
clocks. Flow control signals are available to match
the bandwidth constraints of the physical layer
and the ATM layer. The UTOPIA level 2 supports
point to multipoint configurations by introducing
on addressing capability and by making a
distinction between polling and selecting a device:
– The ATM chip polls a specific physical layer chip
by putting its address on the address bus when
the Enb* line is asserted. The addressed physical layer answers the next cycle via the Clav line
reflecting its status at that time.
– The ATM chip selects a specific physical layer
by putting its address on the address bus when
the Enb* line is deasserted and asserting the
Enb* line on the next cycle. The addressed
physical layer chip will be the target or source of
the next cell transfer (see Figure 17).
Utopia Level 2 Signals
The physical chip sends cell data towards the
ATM layer chip. The ATM layer chip polls the
status of the fifo of the physical layer chip. The cell
exchange proceeds like:
a) The physical layer chip signals the availability
of a cell by asserting RxClav when polled by
the ATM chip.
b) The ATM chips selects a physical layer chip,
then starts the transfer by asserting RxEnb*.
c) If the physical layer chip has data to send, it
puts them on the RxData line the cycle after it
sampled RxEnb* active. It also advances the
offset in the cell. If the data transferred is the
first byte of a cell, RxSOC is 1b at the time of
the data transfer, 0b otherwise.
d) The ATM chip accepts the data when they are
available. If RxSOC was 1b during the transfer,
it resets its internal offset pointer to the value 1,
otherwise it advances the offset in the cell.
Figure 17 : Signal at Utopia Level 2 Interface
PHY
ATM
RxADDR 5
RxCLAV 1
RxENB*
PHY
RECEIVE
RxCLK
ATM
RECEIVE
RxDATA 8
RxSOC
RxREF*
TxADDR 5
TxCLAV 1
TxENB*
PHY
TRANSMIT
TxCLK
ATM
TRANSMIT
TxDATA 8
TxSOC
TxREF*
ST70235A Utopia Level 2 MPHY Operation
Utopia level 2 MPHY operation can be done by
various interface schemes. The ST70235A
supports only the required mode, this mode is
referred to as "Operation with 1 TxClav and 1
RxClav".
PHY Device Identification
The ST70235A holds 2 PHY layer Utopia ports,
one is dedicated to the fast data channel, the
other one to the interleaved data channel. The
associated PHY address is specified by the
PHY_ADDR_x fields in the Utopia PHY address
register.
19/28
ST70235A
Beware that an incorrect address configuration may lead to bus conflicts. A feature is defined to disable
(tri-state) all outputs of the Utopia interface. It is enabled by the TRI_STATE_EN bit in the Rx_interface
control register.
Pin Description Utopia 2 (Receive Interface)
Name
Type
Meaning
Usage
Remark
RxClav
O
Receive Cell available
Signals to the ATM chip that
the STLC60135 has a cell
ready for transfer
Remains active for the entire
cell transfer
RxEnb*
I
Receive Enable
Signals to the physical layer
that the ATM chip will sample
and accept data during next
clock cycle
RxData and RxSOC could be
tri-state when RxEnb* is
inactive (high)
RxClk
I
Receive Byte Clock
Gives the timing signal for the
transfer, generated by ATM
layer chip.
RxData
O
Receive Data (8 bits)
ATM cell data, from physical
layer chip to ATM chip, byte
wide.
RxSOC
O
Receive Start Cell
Identifies the cell boundary on
RxData
RxAddr
I
Receive Address (5 bits)
Use to select the port that will
be active or polled
RxRef *
O
Reference Clock
8kHz clock transported over
the network
Note
Indicate to the ATM layer chip
that RxData contains the first
valid byte of a cell.
*Active low signal
Pin Description Utopia 2 (Transmit interface)
Name
Type
Meaning
Usage
TxClav
O
Transmit Cell available
Signals to the ATM chip that the
physical layer chip is ready to
accept a cell
TxEnb*
I
Transmit Enable
Signals to the physical layer
that TxData and TxSOC are
valid
TxClk
I
Transmit Byte Clock
Gives the timing signal for the
transfer, generated by ATM
layer chip.
TxData
I
Transmit Data (8 bits)
ATM cell data, to physical layer
chip to ATM chip, byte wide.
TxSOC
I
Transmit Start of Cell
Identifies the cell boundary on
TxData
TxAddr
I
Transmit Address (5 bits)
Use to select the port that will
be active or polled
TxRef *
I
Reference Clock
8kHz clock from the ATM layer
chip
Note
20/28
*Active low signal
Remark
Remains active for the entire
cell transfer
ST70235A
Analog Front End Control Interface
The Analog Front End Interface is designed to be
connected to the ST70134 Analog Front End
component.
The ST70235A fetches the 16 bit word to be
multiplexed on AFTXD from the Tx Digital
Front-End module.
Receive Interface
Transmit Interface
The 16 bit words are multiplexed on 4 AFTXD
output signals. As a result 4 cycles are needed to
transfer 1 word. Refer to table 1 for the bit/pin
allocation for the 4 cycles.
The first of 4 cycles is identified by the CLWD
signal. Refer to Figure 18.
The 16 bit receive word is multiplexed on 4
AFRXD input signals. As a result 4 cycles are
needed to transfer 1 word.
Refer to Table 2 for the bit / pin allocation for the 4
cycles. The first of 4 cycles is identified by the
CLWD must repeat after 4 MCLK cycles.
Figure 18 : Transmit Word Timing Diagram
MCLK
CLWD
AFTXD
Cycle0
Cycle1
Cycle2
Cycle3
Test0
Test1
Test2
Test3
GP_OUT
Figure 19 : Receive Word Timing Diagram
MCLK
CLWD
AFRXD
Cycle0
Cycle1
Cycle2
Cycle3
Test0
Test1
Test2
Test3
GP_IN(0)
21/28
ST70235A
Figure 20 : Transmit Interface
Table 3 : Transmitted Bits Assigned to Signal /
Time Slot
Cycle 0
Cycle 1
Cycle 2
Cycle 3
AFTXD[0]
b0
b4
b8
b12
AFTXD[1]
b1
b5
b9
b13
AFTXD[2]
b2
b6
b10
b14
AFTXD[3]
b3
b7
b11
b15
MCLK
Tv
AFTXD
Figure 21 : Receive Interface
Table 4 : Transmitted Bits Assigned to Signal /
Time Slot
MCLK
Ts
Th
AFRXD
Tc
CLWD
Cycle 0
Cycle 1
Cycle 2
Cycle 3
AFRXD[0]
b0
b4
b8
b12
AFRXD[1]
b1
b5
b9
b13
AFRXD[2]
b2
b6
b10
b14
AFRXD[3]
b3
b7
b11
b15
Table 5 : Master Clock (MCLK) AC Electrical Characteristics
Symbol
Parameter
F
Clock Frequency
Tper
Clock Period
Th
Clock Duty Cycle
Minimum
Typical
Maximum
Unit
35.328
MHz
28.3
ns
40
60
%
Maximum
Unit
Table 6 : AFTXD, AFTXED, CLWD AC Electrical Characteristics
Symbol
Parameter
Minimum
Typical
Tv
Data Valid Time
0
13
ns
Tc
Data Valid Time
0
10
ns
Maximum
Unit
Table 7 : AFRXD AC Electrical Characteristics
Symbol
Parameter
Minimum
Typical
Ts
Data setup Time
5
ns
Th
Data hold Time
5
ns
22/28
ST70235A
Tests, Clock, JTAG Interface
Table 8 : Boundary Scan Chain Sequence
– Mclk: Master Clock (35.328MHz) generated by
VCXO
Signal
Name
Sequence
Number
BS
Type
– ATM receive interface, asynchronous clock generated by Utopia Master
Csb
IO30
I
Wr_Rdb
IO31
I
Rdyb
IO32
B
Obc_Type
IO33
I
Intb
IO34
O
Resetb
IO35
I
U_Rxdata[0]
IO38
B
U_Rxdata[1]
IO39
B
U_Rxdata[2]
IO41
B
U_Rxdata[3]
IO42
B
U_Rxdata[4]
IO44
B
U_Rxdata[5]
IO45
B
U_Rxdata[6]
IO47
B
U_Rxdata[7]
IO48
B
– ATM transmit interface, asynchronous clock
generated by Utopia Master
– ATC clock (Pclk): external asynchronous clock
(synchronous with ATC in case of i960 specific
interface)
JTAG TP interface: Standard Test Access Port,
Used with the boundary scan for chip and board
testing. This JTAG TAP interface consists in 5
signals:
TDI, TDO, TCK & TMS.
TSRTB: Test Reset, reset the TAP controller.
TRSTB is an active low signal.
Table 8 : Boundary Scan Chain Sequence
Signal
Name
Sequence
Number
BS
Type
Ad[0]
IO2
B
U_Rxaddr[0]
IO50
I
Ad[1]
IO3
B
U_Rxaddr[1]
IO51
I
Ad[2]
IO4
B
U_Rxaddr[2]
IO52
I
Ad[3]
IO6
B
U_Rxaddr[3]
IO53
I
Ad[4]
IO7
B
U_Rxaddr[4]
IO55
I
Ad[5]
IO9
B
Gp_In[0]
IO56
I
Ad[6]
IO10
B
Gp_In[1]
IO58
I
Ad[7]
IO12
B
U_Rxrefb
IO60
O
Ad[8]
IO13
B
U_Txrefb
IO61
I
Ad[9]
IO14
B
U_Rxclk
IO63
C
Ad[10]
IO16
B
U_Rxsoc
IO64
I
Ad[11]
IO17
B
U_Rxclav
IO65
O
Ad[12]
IO19
B
U_Rxenb
IO66
I
Pclk
IO21
C
U_Txclk
IO68
C
Ad[13]
IO23
B
U_Txsoc
IO69
I
Ad[14]
IO24
B
U_Txclav
IO70
O
Ad[15]
IO25
B
U_Txenb
IO71
I
Be1
IO27
I
U_Txdata[7]
IO74
I
Ale
IO28
C
U_Txdata[6]
IO75
I
23/28
ST70235A
Table 8 : Boundary Scan Chain Sequence
Table 8 : Boundary Scan Chain Sequence
Signal
Name
Sequence
Number
BS
Type
Signal
Name
Sequence
Number
BS
Type
U_Txdata[5]
IO77
I
Pdown
IO121
O
U_Txdata[4]
IO78
I
Afrxd[0]
IO123
I
U_Txdata[3]
IO79
I
Afrxd[1]
IO124
I
U_Txdata[2]
IO80
I
Afrxd[2]
IO125
I
U_Txdata[1]
IO82
I
Afrxd[3]
IO126
I
U_Txdata[0]
IO83
I
Clwd
IO128
I
U_Txaddr[4]
IO84
I
Mclk
IO129
C
U_Txaddr[3]
IO85
I
Ctrldata
IO130
O
U_Txaddr[2]
IO87
I
Disable_Comp
IO135
I
U_Txaddr[1]
IO88
I
Iddq
IO138
C
U_Txaddr[0]
IO89
I
AFTXD[0]
IO139
NONE
Reserved 0
IO90
O
AFTXD[1]
IO140
NONE
Reserved 1
IO92
O
AFTXD[2]
IO142
NONE
Reserved 2
IO93
O
AFTXD[3]
IO143
NONE
Reserved 3
IO94
O
Reserved 4
IO96
O
Reserved 5
IO97
O
Reserved 6
IO98
O
Reserved 7
IO99
O
Reserved 8
IO100
NONE
Reserved 9
IO101
O
Reserved 10
IO103
I
Reserved 11
IO104
I
Reserved 12
IO105
I
Reserved 13
IO106
I
Reset Initialization
Reserved 14
IO107
O
The ST70235A supports two reset modes:
Reserved 15
IO110
O
Reserved 16
IO111
O
TDI
IO112
NONE
TDO
IO113
NONE
TMS
IO114
NONE
TCK
IO116
NONE
– A 'hardware' reset is activated by the RESETB
pin (active low). A hard reset occurs when a low
input value is detected at the RESETB input.
The low level must be applied for at least 1ms to
guarantee a correct reset operation. All clocks
and power supplies must be stable for
200ns prior to the rising edge of the RESETB
signal.
TRSTB
IO118
NONE
Testse
IO119
C
GP_Out
IO120
O
24/28
General purpose I/O register (0x40)
Field
Type
Position
Bits
Length
Function
GP_IN
R
[0,1]
2
Sampled
level on pins
GP_IN
GP_OUT
RW
[2]
1
Output level
on pins
GP_OUT
Bits from 3 to 15 are reserved
– 'Soft' reset activated by the controller write
access to a soft reset configuration bit. The reset
process takes less than 10000 MCLK clock
cycles.
ST70235A
ELECTRICAL SPECIFICATIONS
Generic DC Electrical Characteristics
The values presented in the following table apply for all inputs and/or outputs unless otherwise specified.
All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device.
IO Buffers Generic DC Characteristics
Symbol
Parameter
Test Condition
Minimum
Typical
Maximum
Unit
IIN
Input Leakage Current
VIN = VSS, VDD no
pull up /pull down
-4
4
µA
IOZ
Tristate Leakage Current
VIN = VSS, VDD no
pull up /pull down
-4
4
µA
IPU
Pull up Current
VIN = VSS
-15
-66
-125
µA
IPD
Pull Down Current
VIN = VDD
15
66
125
µA
RPU
Pull up Resistance
VIN = VSS
50
KΩ
RPD
Pull Down Resistance
VIN = VDD
50
KΩ
Input/ Output TTL Generic Characteristics
The values presented in the following table apply for all TTL inputs and/or outputs unless otherwise
specified.
Symbol
Parameter
Test Condition
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
VHY
Schmitt Trigger Hysteresis
Slow edge < 1V/µs
VOL
Low Level Output Voltage
IOUT = XmA*
VOH
High Level Output Voltage
IOUT = XmA*
Minimum
Typical
Maximum
Unit
0.8
V
2.0
0.4
2.4
V
0.7
V
0.4
V
V
* The reference current is dependent on the exact buffer chosen and is a part of the buffer name. The available values are 4 and 8mA.
25/28
ST70235A
TQFP144 PACKAGE MECHANICAL DATA
Figure 22 : Package Outline TQFP144
A
A2
A1
e
144
109
108
36
73
E3
E1
E
B
1
0,076 mm
0.03 inch
SEATING PLANE
c
72
L1
D3
D1
D
L
37
K
Millimeter
0,25 mm
.010 inch
GAGE PLANE
Inch
Dimension
Minimum
Typical
A
Minimum
Typical
1.60
A1
0.05
A2
1.35
B
0.17
C
0.09
0.15
0.002
0.006
1.40
1.45
0.053
0.055
0.057
0.22
0.27
0.0067
0.0087
0.011
0.20
0.0035
0.008
22.00
0.866
D1
20.00
0.787
D3
17.50
0.689
e
0.50
0.020
E
22.00
0.866
E1
20.00
0.787
E3
17.50
0.689
L1
K
0.45
Maximum
0.063
D
L
26/28
Maximum
0.60
0.75
0.018
1.00
0.024
0.039
0° (minimum), 7° (maximum)
0.030
ST70235A
27/28
ST70235A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco
Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
http://www.st.com
28/28
ST70235A.REF
© 2001 STMicroelectronics - All Rights Reserved