STMICROELECTRONICS ST72T754S9T1

ST72774/ST72754/ST72734
8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM,
ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I 2C
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User ROM/OTP/EPROM: up to 60 Kbytes
Data RAM: up to 1 Kbytes (256 bytes stack)
8 MHz Internal Clock Frequency in fast mode,
4 MHz in normal mode
Run and Wait CPU modes
System protection against illegal address jumps
and illegal opcode execution
Sync Processor for Mode Recognition, power
management and composite video blanking,
clamping and free-running frequency
generation
– Corrector mode
– Analyzer mode
USB (Universal Serial Bus) for monitor function 1
– Three endpoints
– Integrated 3.3V voltage regulator
– Transceiver
– Suspend and Resume operations
Timing
Measurement
Unit
(TMU)
for
autoposition and autosize 1
Fast I2C Single Master Interface
DDC Bus Interface with:
– DDC1/2B protocol implemented in hardware
– Programmable DDC CI modes
– Enhanced DDC (EDDC) address decoding
31 I/O lines
PSDIP42
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TQFP44
10 x 10
2 lines programmable as interrupt inputs
16-bit timer with 2 input captures and 2 output
compare functions
8-bit Analog to Digital Converter with 4 channels
on port B
8 10-bit PWM/BRM Digital to Analog outputs
Master Reset and Low Voltage Detector (LVD)
reset
Programmable Watchdog for system reliability
Fully static operation
63 basic instructions / 17 main addressing
modes
8x8 unsigned multiply instruction
True bit manipulation
Complete development support on PC/DOSWindows: Real-Time Emulator, EPROM
Programming Board and Gang Programmer
Full software package (assembler, linker, Ccompiler, source level debugger)
Device Summary
Features
Program Memory Bytes
RAM (stack) - Bytes
ST72(T/E)774(J/S)9 ST72(T)754(J/S)9 ST72774(J/S)7 ST72754(J/S)7 ST72(T/E)734J6
60K
USB
Peripherals
Operating Supply
Oscillator Frequency
Operating Temperature
Package
48K
1K (256)
No USB
USB
32K
No USB
ADC 3, 16-bit timer, I2C, DDC, TMU,Sync, PWM, LVD, Watchdog
512 (256)
No USB
ADC4, I2C,LVD,
DDC,Sync,
16-bit timer,
PWM, Watchdog
4.0V to 5.5V supply operating range
12 or 24 MHz
0 to +70°C
CSDIP42 or PSDIP42 or TQFP44
PSDIP42
CSDIP42
(1) On some devices only, refer to Device Summary; (2) Contact Sales office for availability
(3) 8-bit ±2 LSB A/D converter ; (4) 8-bit ±4 LSB A/D converter.
October 2003
1/144
1
Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 CLOCKS, RESET, INTERRUPTS & LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 Crystal Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
19
19
20
3.2.1 LVD and Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3 Illegal Address Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.4 Illegal Opcode Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
20
20
20
22
3.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4.2 HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2 Common Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
28
29
31
33
35
38
39
4.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 16-BIT TIMER (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
39
39
40
40
41
4.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
....
4.4 SYNC PROCESSOR (SYNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
41
41
51
56
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ST72774/ST727754/ST72734
4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.3 Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.4 Input Signal Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.5 Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.6 Input Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.7 Output Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.8 Analyzer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.9 Corrector Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.10Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 TIMING MEASUREMENT UNIT (TMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
56
57
57
57
61
64
65
67
68
75
4.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
75
75
77
79
4.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.5 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 I²C SINGLE MASTER BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
79
79
80
85
87
4.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.4 Functional Description (Master Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 DDC INTERFACE (DDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
87
87
89
91
95
4.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.8.2 DDC Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.8.3 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.8.4 I2C BUS Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.8.5 DDC Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.8.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.9 PWM/BRM GENERATOR (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
116
116
116
121
123
4.10.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10.3Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10.4Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10.5Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10.6Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
123
123
123
124
124
125
126
126
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5.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
127
127
127
127
127
128
128
129
6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.1 POWER CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.2 AC/DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
8 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
8.1 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
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Revision follow-up
Changes applied since version 4.0
Version 4.0
March 2001
Page 1:Addition of 72T774 (32KOTP).
Addition of 60K/48K ROM for ST72754
Deletion of table “ device summary”, replaced with cross reference to table 36 on page 147.
Version 4.1
page 13 - addition of section 1.4. external connections
July 2001
Initial format reapplied, text and related figures in the same page.
Table “Device summary” reinserted in cover page and updated.
Version 4.2
Update of table 36: ordering information (p143)
July 2001
Cover - addition of feature about system protection added,
table for device summary: addition of stack values
page 9 - figure 3: replaced 1KByte with 512 Bytes + notes about opcode fetch and HALT
mode
page 10 - table: CR replaced by WDGCR
TIM replaced with Timer and WDG replaced with Watchdog
page 115 - EDF register: addition of “read from RAM”, EDE: few changes
page 135 - Note 1 replaced, note 2 added SUSpend mode limitation..
Version 4.3
Whole document: all mentions of HALT mode either deleted or rewritten.
October 2001
p140, chapter 8, section 8.1code for unused bytes ( FFh) replaced with 9Dh (opcode for NOP)
page 141- update of table 36 “Ordering information”
page 142 - list of available devices updated
Version 4.3
page 114 - DDC DCR register: bit 5 = 1, text “or read from RAM” deleted
November 2001
page 10, one adddress corrected in the figure 3 “memory map”: 0400h
page 14: addition of mandatory 1K resistor (text and figure)
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ST72774/ST727754/ST72734
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST72774, ST72754 and ST72734 are
HCMOS microcontroller units (MCU) from the
ST727x4 family with dedicated peripherals for
Monitor applications.
They are based around an industry standard 8-bit
core and offer an enhanced instruction set. The
processor runs with an external clock at 12 or 24
MHz with a 5V supply. Due to the fully static design
of this device, operation down to DC is possible.
Under software control the ST727x4 can be placed
in WAIT mode thus reducing power consumption.
The HALT mode is no longer available.
The enhanced instruction set and addressing
modes afford real programming potential. Illegal
opcodes are patched and lead to a reset.
In addition to standard 8-bit data management the
ST7 features true bit manipulation, 8x8 unsigned
multiplication and indirect addressing modes.
The device includes an on-chip oscillator, CPU,
System protection against illegal address jumps,
Sync Processor for video timing & Vfback analysis,
up to 60K Program Memory, up to 1K RAM, USB/
DMA, a Timing Measurement Unit, I/O, a timer with
2 input captures and 2 output compares, a 4channel Analog to Digital Converter, DDC, I2C
Single Master, Watchdog Reset, and eight 10-bit
PWM/BRM outputs for analog DC control of
external functions.
Figure 1. ST727x4 Block Diagram
Up to 60K Bytes
PORT A
ROM/OTP/EPROM
PORT B
Up to 1K Bytes
RAM
CONTROL
8-BIT CORE
ALU
ADDRESS AND DATA BUS
RESET
ADC
PA0/OCMP1
PA1
PA2/VSYNCI2
PA3-PA6
PA7/BLANKOUT
PB6-PB7/AIN2-AIN3/PWM1-PWM2
PB4-PB5/AIN0-AIN1
I2C
PB3/SDAI
PB2/SCLI
DDC
PB1/SDAD
PB0/SCLD
USB
PORT D
TIMER
USBVCC
USBDP
USBDM
PD0/VSYNCO
PD1/HSYNCO
PD2/CSYNCI
PD3/ITA/VFBACK
PD4/ITB
PD5/HFBACK
PD6/CLAMPOUT
WATCHDOG
SYNC
OSCIN
OSCOUT
Mode
OSC :3 Selection
TMU
VDD
VSS
PROCESSOR
POWER SUPPLY
PORT C
DAC (PWM)
6/144
3
VSYNCI
HSYNCI
PC0/HSYNCDIV
PC1/AV
PC2-PC7/PWM3-PWM8
ST72774/ST727754/ST72734
1.2 PIN DESCRIPTION
PC5 / PWM6
PC4 / PWM5
PC3 / PWM4
PC2 / PWM3
PC1 / AV
PC0 / HSYNCDIV
PA0 / OCMP1
TEST / VPP
RESET
PA1
PA2/VSYNCI2
Figure 2. 44-pin TQFP and 42-Pin SDIP Package Pinouts
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
31
4
30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
PA3
PA4
PA5
PA6
OSCIN
OSCOUT
PA7 / BLANKOUT
PB3 / SDAI
PB2 / SCLI
PB1 / SDAD
NC
Vss
HSYNCI
VSYNCI
VSYNCO / PD0
HSYNCO / PD1
CSYNCI / PD2
VFBACK / ITA /PD3
ITB / PD4
HFBACK / PD5
CLAMPOUT / PD6
SCLD / PB0
PWM7 / PC6
PWM8 / PC7
PWM2 / AIN3 / PB7
PWM1 / AIN2 / PB6
AIN1 / PB5
AIN0 / PB4
NC
VDD
USBVCC
USBDM
USBDP
HSYNCDIV / PC0
1
2
42
41
PA0 / OCMP1
TEST / VPP
3
40
4
5
39
38
RESET
PA1
6
37
36
PA3
PA4
35
34
PA5
9
10
11
33
32
12
31
USBVCC
13
14
30
29
USBDM
USBDP
15
16
28
27
PB1 / SDAD
PB0 / SCLD
26
25
PD6 / CLAMPOUT
AV / PC1
PWM3 / PC2
PWM4 / PC3
PWM5 / PC4
PWM6 / PC5
PWM7 / PC6
PWM8 / PC7
PWM2 / AIN3 / PB7
PWM1 / AIN2 / PB6
AIN1 / PB5
AIN0 / PB4
VDD
7
8
VSS
17
HSYNCI
VSYNCI
18
19
VSYNCO / PD0
20
24
23
HSYNCO / PD1
21
22
PA2/VSYNCI2
PA6
OSCIN
OSCOUT
PA7 / BLANKOUT
PB3 / SDAI
PB2 / SCLI
PD5 / HFBACK
PD4 / ITB
PD3 / ITA / VFBACK
PD2 / CSYNCI
NC = Not connected
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3
ST72774/ST727754/ST72734
PIN DESCRIPTION (Cont’d)
TEST/VPP: Input. EPROM programming voltage.
This pin must be held low during normal operating
modes.
RESET: Bidirectional. This active low signal forces
the initialization of the MCU. This event is the top
priority non maskable interrupt. This pin is
switched low when the Watchdog has triggered or
VDD is low. It can be used to reset external
peripherals.
VSS: Digital Ground.
OSCIN/OSCOUT: Input/Output Oscillator pin.
These pins connect a parallel-resonant crystal, or
an external source to the on-chip oscillator.
Alternate Functions: several pins of the I/O ports
assume
software
programmable
alternate
functions as shown in the pin description
VDD: Power supply voltage (4.0V-5.5V)
Table 1. ST727x4 Pin Description
TQFP44
SDIP42
Pin No.
39
1
PC0/HSYNCDIV
I/O
Port C0 or HSYNCDIV output (HSYNCO divided by 2)
40
2
PC1/AV
I/O
Port C1 or “Active Video” input
41
3
PC2/PWM3
I/O
Port C2 or 10-bit PWM/BRM output 3
42
4
PC3/PWM4
I/O
Port C3 or 10-bit PWM/BRM output 4
43
5
PC4/PWM5
I/O
Port C4 or 10-bit PWM/BRM output5
44
6
PC5/PWM6
I/O
Port C5 or 10-bit PWM/BRM output 6
1
7
PC6/PWM7
I/O
Port C6 or 10-bit PWM/BRM output 7
2
8
PC7/PWM8
I/O
Port C7 or 10-bit PWM/BRM output 8
3
9
PB7/AIN3/PWM2
I/O
Port B7 or ADC analog input 3 or 10-bit PWM/BRM
output 2
4
10
PB6/AIN2/PWM1
I/O
Port B6 or ADC analog input 2 or 10-bit PWM/BRM
output 1
5
11
PB5/AIN1
I/O
Port B5 or ADC analog input 1
I/O
Pin Name
Type
Description
6
12
PB4/AIN0
8
13
VDD
S
Supply (4.0V - 5.5V)
9
14
USBVCC
S
USB power supply (output 3.3V +/- 10%)
10
15
USBDM
I/O
USB bidirectional data
11
16
USBDP
I/O
USB bidirectional data
12
17
VSS
S
Ground 0V
13
18
HSYNCI
I
SYNC horizontal synchronisation input
14
19
VSYNCI
15
20
PD0/VSYNCO
I/O
Port D0 or SYNC vertical synchronisation output
16
21
PD1/HSYNCO
I/O
Port D1 or SYNC horizontal synchronisation output
17
22
PD2/CSYNCI
I/O
Port D2 or SYNC composite synchronisation input
8/144
3
I
Remarks
For analog controls,
after external filtering
Port B4 or ADC analog input 0
SYNC vertical synchronisation input
Must be tied to ground
for devices without
USB peripheral
TTL levels
Refer to Figure 16
TTL levels with pull-up
(SYNC input)
ST72774/ST727754/ST72734
TQFP44
SDIP42
Pin No.
Pin Name
18
23
PD3/VFBACK/ITA
I/O
Refer to Figure 16 and
Port D3 or SYNC Vertical flyback input or interrupt fallTable 11 Port D Deing edge detector input A
scription
19
24
PD4/ITB
I/O
Port D4 or Interrupt falling edge detector input B
Refer to Table 11 Port
D Description
20
25
PD5/HFBACK
I/O
Port D5 or SYNC horizontal flyback input
TTL levels with pull-up
(SYNC input)
21
26
PD6/CLAMPOUT
I/O
Port D6 or SYNC clamping/ MOIRE output
22
27
PB0/SCLD
I/O
Port B0 or DDC serial clock
24
28
PB1/SDAD
I/O
Port B1 or DDC serial data
25
29
PB2/SCLI
I/O
Port B2 or I2C serial clock
26
30
PB3/SDAI
I/O
Port B3 or I2C serial data
27
31
PA7/BLANKOUT
I/O
Port A7 or SYNC blanking output
28
32
OSCOUT
O
Oscillator output
29
33
OSCIN
I
Oscillator input
30
34
PA6
I/O
Port A6
31
35
PA5
I/O
Port A5
32
36
PA4
I/O
Port A4
33
37
PA3
I/O
Port A3
34
38
PA2/VSYNCI2
I/O
Port A2 or SYNC vertical synchronisation input 2
35
39
PA1
I/O
Port A1
36
40
RESET
I/O
Reset pin
37
41
TEST/VPP
38
42
PA0/OCMP1
Type
S
I/O
Description
Remarks
DDC1 only
Active low
Test mode pin or EPROM programming voltage. This
pin should be tied low in user mode.
Port A0 or TIMER output compare 1
9/144
ST72774/ST727754/ST72734
1.3 MEMORY MAP
Figure 3. Memory Map
0000h
HW Registers
005Fh
0060h
0060h
(see Table 2)
Short Addressing
RAM (zero page)
0100h
512 Bytes RAM
256 Bytes Stack/
16-bit Addressing RAM
1 Kbyte RAM
01FFh
03FFh
0400h
0060h
Reserved
Short Addressing
RAM (zero page)
0100h
0FFFh
1000h
256 Bytes Stack/
16-bit Addressing RAM
60 Kbytes ROM/EPROM
01FFh
4000h
48 Kbytes
0200h
8000h
32 Kbytes
FFDFh
FFE0h
512 Bytes
Interrupt & Reset Vectors *
(see Table 3)
FFFFh
16-bit Addressing
RAM
03FFh
any opcode fetch in those areas is considered as illegal and generates a reset
(*) this block only contains addresses of interrupts and reset routines, no opcode is run from this block
10/144
ST72774/ST727754/ST72734
MEMORY MAP (Cont’d)
Table 2. Hardware Register Memory Map
Address
Block
0000h
Register Label
PADR
Register Name
Reset
Status
Remarks
Port A Data Register
00h
R/W
0001h
PADDR
Port A Data Direction Register
00h
R/W
0002h
PBDR
Port B Data Register
00h
R/W
0003h
PBDDR
Port B Data Direction Register
00h
R/W
0004h
PCDR
Port C Data Register
00h
R/W
0005h
PCDDR
Port C Data Direction Register
00h
R/W
0006h
PDDR
Port D Data Register
00h
R/W
0007h
PDDDR
Port D Data Direction Register
00h
R/W
0008h
Watchdog
WDGCR
Watchdog Control Register
7Fh
R/W
MISCR
Miscellaneous Register
10h
R/W
ADCDR
ADC Data Register
00h
Read only
ADCCSR
ADC Control Status register
00h
R/W
DDCDCR
DDC1/2B Control Register
00h
R/W
DDCAHR
DDC1/2B Address Pointer High Register
xxh
R/W
TMUCSR
TMU control status register
FCh
R/W
TMUT1CR
TMU T1 counter register
FFh
Read only
00010h
TMUT2CR
TMU T2 counter register
FFh
Read only
0011h
TIMCR2
Timer Control Register 2
00h
R/W
0012h
TIMCR1
Timer Control Register 1
00h
R/W
0013h
TIMSR
Timer Status Register
00h
Read only
0014h
TIMIC1HR
Timer Input Capture 1 High Register
xxh
Read only
0015h
TIMIC1LR
Timer Input Capture 1 Low Register
xxh
Read only
0016h
TIMOC1HR
Timer Output Compare 1 High Register
80h
R/W
0017h
TIMOC1LR
Timer Output Compare 1 Low Register
00h
R/W
0009h
000Ah
000Bh
000Ch
000Dh
ADC
DDC1/2B
000Eh
000Fh
0018h
TMU
Timer
TIMCHR
Timer Counter High Register
FFh
Read only
0019h
TIMCLR
Timer Counter Low Register
FCh
R/W
001Ah
TIMACHR
Timer Alternate Counter High Register
FFh
Read only
001Bh
TIMACLR
Timer Alternate Counter Low Register
FCh
R/W
001Ch
TIMIC2HR
Timer Input Capture 2 High Register
xxh
Read only
001Dh
TIMIC2LR
Timer Input Capture 2 Low Register
xxh
Read only
001Eh
TIMOC2HR
Timer Output Compare 2 High Register
80h
R/W
001Fh
TIMOC2LR
Timer Output Compare 2 Low Register
00h
R/W
0020h
to
0024h
Reserved Area (5 bytes)
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ST72774/ST727754/ST72734
Address
Block
Register Label
Register Name
Reset
Status
Remarks
0025h
USBPIDR
USB PID Register
XXh
Read only
0026h
USBDMAR
USB DMA address Register
XXh
R/W
R/W
0027h
USBIDR
USB Interrupt/DMA Register
XXh
0028h
USBISTR
USB Interrupt Status Register
00h
R/W
0029h
USBIMR
USB Interrupt Mask Register
00h
R/W
USBCTLR
USB Control Register
xxxx 0110
R/W
USBDADDR
USB Device Address Register
00h
R/W
USBEP0RA
USB Endpoint 0 Register A
0000 xxxx
R/W
R/W
002Ah
002Bh
USB
002Ch
002Dh
USBEP0RB
USB Endpoint 0 Register B
80h
002Eh
USBEP1RA
USB Endpoint 1 Register A
0000 xxxx
R/W
002Fh
USBEP1RB
USB Endpoint 1 Register B
R/W
0030h
USBEP2RA
USB Endpoint 2 Register A
0000
xxxx0000
0000
0031h
USBEP2RB
USB Endpoint2 Register B
xxxx0000
R/W
0032h
PWM1
80h
R/W
0033h
BRM21
00h
R/W
0034h
PWM2
80h
R/W
0035h
PWM3
80h
R/W
0036h
BRM43
00h
R/W
0037h
PWM4
80h
R/W
80h
R/W
0038h
PWM
PWM5
10 BIT PWM / BRM
R/W
0039h
BRM65
00h
R/W
003Ah
PWM6
80h
R/W
003Bh
PWM7
80h
R/W
003Ch
BRM87
00h
R/W
003Dh
PWM8
80h
R/W
003Eh
PWMCR
00h
R/W
003Fh
PWM output enable register
Reserved Area (1 byte)
0040h
SYNCCFGR
SYNC Configuration Register
00h
R/W
0041h
SYNCMCR
SYNC Multiplexer Register
20h
R/W
0042h
SYNCCCR
SYNC Counter Register
00h
R/W
SYNCPOLR
SYNC Polarity Register
08h
R/W
SYNCLATR
SYNC Latch Register
00h
R/W
0045h
SYNCHGENR
SYNC H Sync Generator Register
00h
R/W
0046h
SYNCVGENR
SYNC V Sync Generator Register
00h
R/W
0047h
SYNCENR
SYNC Processor Enable Register
C3h
R/W
0043h
0044h
0048h
to
004Fh
12/144
SYNC
Reserved Area (8 bytes)
ST72774/ST727754/ST72734
Address
Block
Register Label
Register Name
Reset
Status
Remarks
0050h
DDCCR
DDC/CI Control Register
00h
R/W
0051h
DDCSR1
DDC/CI Status Register 1
00h
Read only
DDCSR2
DDC/CI Status Register 2
00h
Read only
00h
R/W
00h
R/W
00h
R/W
0052h
0053h
DDC/CI
0054h
Reserved
DDCOAR
0055h
DDC/CI (7 Bits) Slave address Register
Reserved
0056h
DDCDR
DDC/CI Data Register
0057h
Reserved Area (2 bytes)
0058h
0059h
I2CDR
I2C Data Register
005Ah
Reserved
005Bh
Reserved
I2CCCR
I2C Clock Control Register
00h
R/W
005Dh
I2CSR2
I2C Status Register 2
00h
Read only
005Eh
I2CSR1
I2C Status Register 1
00h
Read only
I2CCR
I2C
00h
R/W
005Ch
I2C
005Fh
Control Register
Table 3. Interrupt Vector Map
Vector Address
Description
FFE0-FFE1h
FFE2-FFE3h
FFE4-FFE5h
FFE6-FFE7h
FFE8-FFE9h
FFEA-FFEBh
FFEC-FFEDh
FFEE-FFEFh
FFF0-FFF1h
FFF2-FFF3h
FFF4-FFF5h
FFF6-FFF7h
FFF8-FFF9h
FFFA-FFFBh
FFFC-FFFDh
FFFE-FFFFh
Not used
Not used
Not used
USB interrupt vector
Not used
I2C interrupt vector
Timer Overflow interrupt vector
Timer Output Compare interrupt vector
Timer Input Capture interrupt vector
ITA falling edge interrupt vector
ITB falling edge interrupt vector
DDC1/2B interrupt vector
DDC/CI interrupt vector
USB End Suspend interrupt vector
TRAP (software) interrupt vector
RESET vector
Remarks
Internal Interrupts
External Interrupts
Internal Interrupt
CPU Interrupt
13/144
ST72774/ST727754/ST72734
1.4 External connections
The following figure shows the recommended external connections for the device.
The VPP pin is only used for programming OTP
and EPROM devices and must be tied to ground in
user mode.
The 10 nF and 0.1 µF decoupling capacitors on
the power supply lines are a suggested EMC performance/cost tradeoff.
The external reset network (including the mandatory 1K serial resistor) is intended to protect the
device against parasitic resets, especially in noisy
environments.
Unused I/Os should be tied high to avoid any unnecessary power consumption on floating lines.
An alternative solution is to program the unused
ports as inputs with pull-up.
Figure 4. Recommended External Connections
VPP
VDD
10nF
VDD
+
0.1µF
VSS
VDD
4.7K
0.1µF
RESET
EXTERNAL RESET CIRCUIT
1K
0.1µF
See
Clocks
Section
OSCIN
OSCOUT
Or configure unused I/O ports
by software as input with pull-up
VDD
14/144
10K
Unused I/O
ST72774/ST727754/ST72734
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
The Accumulator is an 8-bit general purpose
register used to hold operands and the results of
the arithmetic and logic calculations and to
manipulate data.
Index Registers (X and Y)
2.2 MAIN FEATURES
■
■
■
■
■
■
■
■
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede
instruction (PRE) to indicate that the following
instruction refers to the Y register.)
63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes
Two 8-bit index registers
16-bit stack pointer
Low power modes
Maskable hardware interrupts
Non-maskable software interrupt
The Y register is not affected by the interrupt
automatic procedures (not pushed to and popped
from the stack).
Program Counter (PC)
2.3 CPU REGISTERS
The 6 CPU registers shown in Figure 5 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 5. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
X INDEX REGISTER
RESET VALUE = XXh
7
0
Y INDEX REGISTER
RESET VALUE = XXh
15
PCH
8 7
PCL
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1 1 1 H I
0
N Z C
CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X
15
8 7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
15/144
ST72774/ST727754/ST72734
CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Reset Value: 111x1xxx
7
1
0
1
1
H
I
N
Z
C
The 8-bit Condition Code register contains the
interrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP
instructions.
These bits can be individually tested and/or
controlled by specific instructions.
enter it and reset by the IRET instruction at the end
of the interrupt routine. If the I bit is cleared by
software in the interrupt routine, pending interrupts
are serviced regardless of the priority level of the
current interrupt routine.
Bit 2 = N Negative.
This bit is set and cleared by hardware. It is
representative of the result sign of the last
arithmetic, logical or data manipulation. It is a copy
of the 7th bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL
instructions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs
between bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH
instruction. The H bit is useful in BCD arithmetic
subroutines.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit
indicates that the result of the last arithmetic,
logical or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 3 = I Interrupt mask.
This bit is set by hardware when entering in
interrupt or by software to disable all interrupts
except the TRAP software interrupt. This bit is
cleared by software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET
instructions and is tested by the JRM and JRNM
instructions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
because the I bit is set by hardware when you
16/144
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and
software. It indicates an overflow or an underflow
has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
ST72774/ST727754/ST72734
CPU REGISTERS (Cont’d)
Stack Pointer (SP)
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD
instruction.
Read/Write
Reset Value: 01 FFh
15
0
8
0
0
0
0
0
0
7
SP7
1
0
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is
always pointing to the next free location in the
stack. It is then decremented after data has been
pushed onto the stack and incremented before
data is popped from the stack (see Figure 6).
Since the stack is 256 bytes deep, the most
significant byte is forced by hardware. Following
an MCU Reset, or after a Reset Stack Pointer
instruction (RSP), the Stack Pointer contains its
reset value (the SP7 to SP0 bits are set) which is
the stack higher address.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit,
without indicating the stack overflow. The
previously stored information is then overwritten
and therefore lost. The stack also wraps in case of
an underflow.
The stack is used to save the return address
during a subroutine call and the CPU context
during an interrupt. The user may also directly
manipulate the stack by means of the PUSH and
POP instructions. In the case of an interrupt, the
PCL is stored at the first location pointed to by the
SP. Then the other registers are stored in the next
locations as shown in Figure 6.
– When an interrupt is received, the SP is decremented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an
interrupt five locations in the stack area.
Figure 6. Stack Manipulation Example
CALL
Subroutine
PUSH Y
Interrupt
event
POP Y
RET
or RSP
IRET
@ 0100h
SP
SP
CC
A
SP
CC
A
X
X
X
PCH
PCH
PCH
PCL
PCL
PCL
PCH
PCH
PCH
PCH
PCH
PCL
PCL
PCL
PCL
PCL
SP
@ 01FFh
Y
CC
A
SP
SP
Stack Higher Address = 01FFh
Stack Lower Address = 0100h
17/144
ST72774/ST727754/ST72734
3 CLOCKS, RESET, INTERRUPTS & LOW POWER MODES
3.1 CLOCK SYSTEM
3.1.1 General Description
The MCU accepts either a crystal or an external
clock signal to drive the internal oscillator. The
internal clock (CPU CLK running at fCPU) is
derived from the external oscillator frequency
(fOSC), which is divided by 3. Depending on the
external quartz or clock frequency, a division factor
of 2 is optionally added to generate the 12 MHz
clock for the Sync Processor (clamp function) as
shown in Figure 7 and a second divider by 2 for the
6MHz USB clock.
The CPU clock is used also as clock for the
ST727x4 peripherals.
Note: In the Sync processor, an additional divider
by two is added in fast mode (same external timing
for this peripheral).
Figure 7. Clock divider chain
%3
OSC
%2
12 MHz
or
24MHz
fCPU: 4 or 8 MHz
(CPU and peripherals)
12 MHz
(Sync processor Clampout signal)
FAST
%2
6 MHz
(USB)
12 MHz
or
24MHz
(TMU)
FAST=1 for 24MHZ oscillator
18/144
4
FAST=0 for 12 MHz oscillator
ST72774/ST727754/ST72734
CLOCK SYSTEM (Cont’d)
3.1.2 Crystal Resonator
The internal oscillator is designed to operate with
an AT-cut parallel resonant quartz crystal
resonator in the frequency range specified for fosc.
The circuit shown in Figure 8 is recommended
when using a crystal, and Table 4, “.
Recommended Crystal Values,” on page 19 lists
the recommended capacitance and feedback
resistance values. The crystal and associated
components should be mounted as close as
possible to the input pins in order to minimize
output distortion and start-up stabilization time.
Figure 8. Crystal/Ceramic Resonator
CRYSTAL CLOCK
Table 4. Recommended Crystal Values
24 Mhz
Unit
RSMAX
70
25
20
Ohms
CL1
22
47
56
pf
CL2
22
47
56
pf
Legend:
CL1, CL2 = Maximum total capacitance on pins
OSCIN and OSCOUT (the value includes the
external capacitance tied to the pin plus the
parasitic capacitance of the board and of the
device).
RSMAX = Maximum series parasitic resistance of
the quartz allowed.
Note: The tables are relative to the quartz crystal
only (not ceramic resonator).
OSCIN
CL1
OSCOUT
CL2
1M*
*Recommended for oscillator stability
3.1.3 External Clock
An external clock should be applied to the OSCIN
input with the OSCOUT pin not connected as
shown in Figure 9. The Crystal clock specifications
do not apply when using an external clock input.
The equivalent specification of the external clock
source should be used.
Figure 9. External Clock Source Connections
OSCIN
OSCOUT
NC
EXTERNAL
CLOCK
19/144
ST72774/ST727754/ST72734
3.2 RESET
The Reset procedure is used to provide an orderly
software start-up or to quit low power modes.
Five conditions generate a reset:
■
LVD,
■
watchdog,
■
external pulse at the RESET pin,
■
illegal address,
■
illegal opcode.
A reset causes the reset vector to be fetched from
addresses FFFEh and FFFFh in order to be loaded
into the PC and with program execution starting
from this point.
An internal circuitry provides a 4096 CPU clock
cycle delay from the time that the oscillator
becomes active.
3.2.1 LVD and Watchdog Reset
The Low Voltage Detector (LVD) generates a reset
when VDD is below V TRH when VDD is rising or VTRL
when VDD is falling (refer to Figure 11). This circuitry
is active only when VDD is above VTRM.
When a watchdog reset occurs, the RESET pin is
pulled low permitting the MCU to reset other
devices as when Power on/off (Figure 10).
3.2.2 External Reset
The external reset is an active low input signal
applied to the RESET pin of the MCU.
As shown in Figure 12, the RESET signal must
remain low for 1000ns.
An internal Schmitt trigger at the RESET pin is
provided to improve noise immunity.
3.2.3 Illegal Address Detection
An opcode fetch from an illegal address (refer to
Figure 3) generates an illegal address reset.
Program execution at those addresses is
forbidden (especially to protect page 0 registers
against spurious accesses).
3.2.4 Illegal Opcode Detection
Illegal instructions corresponding to no valid
opcode generate a reset. Refer to ST7
Programming Manual.
During LVD Reset, the RESET pin is held low, thus
permitting the MCU to reset other devices.
Table 5. List of sections affected by RESET and WAIT (Refer to 3.6 for Wait Mode)
Section
RESET
Fast bit of the miscellaneous register set to one (24 MHz as external clock)
X
Timer Prescaler reset to zero
X
Timer Counter set to FFFCh
X
All Timer enable bits set to 0 (disabled)
X
Data Direction Registers set to 0 (as Inputs)
X
Set Stack Pointer to 01FFh
X
Force Internal Address Bus to restart vector FFFEh, FFFFh
X
Set Interrupt Mask Bit (I-Bit, CC) to 1 (Interrupt disable)
X
Set Interrupt Mask Bit (I-Bit, CC) to 0 (Interrupt enable)
X
Reset WAIT latch
X
Disable Oscillator (for 4096 cycles)
X
Set Timer Clock to 0
X
Watchdog counter reset
X
Watchdog register reset
X
Port data registers reset
X
Other on-chip peripherals: registers reset
X
20/144
WAIT
ST72774/ST727754/ST72734
RESET (Cont’d)
Figure 10. Low Voltage Detector Functional Diagram
Figure 11. LVD Reset Signal Output
LVD
VDD
VTRH
RESPOF
FROM
WATCHDOG
RESET
VTRL
VTRM
RESET
INTERNAL
RESET
VTRM
VDD
RESET
Note: See electrical characteristics section for
values of VTRH, VTRL and VTRM
Figure 12. Reset Timing Diagram
tDDR
VDD
OSCIN
tOXOV
fCPU
PC
RESET
WATCHDOG RESET
FFFE
FFFF
tRL
4096 CPU
CLOCK
CYCLES
DELAY
Note: Refer to Electrical Characteristics for values of tDDR, tOXOV and tRL
21/144
ST72774/ST727754/ST72734
3.3 INTERRUPTS
The ST727x4 may be interrupted by one of two
different methods: maskable hardware interrupts
as listed in Table 6 and a non-maskable software
interrupt (TRAP). The Interrupt processing
flowchart is shown in Figure 13.
The maskable interrupts must be enabled in order
to be serviced. However, disabled interrupts can
be latched and processed when they are enabled.
When an interrupt has to be serviced, the PC, X, A
and CC registers are saved onto the stack and the
interrupt mask (I bit of the Condition Code
Register) is set to prevent additional interrupts.
The Y register is not automatically saved.
The PC is then loaded with the interrupt vector of
the interrupt to service and the interrupt service
routine runs (refer to Table 6, “Interrupt Mapping,”
on page 24 for vector addresses). The interrupt
service routine should finish with the IRET
instruction which causes the contents of the
registers to be recovered from the stack and
normal processing to resume. Note that the I bit is
then cleared if and only if the corresponding bit
stored in the stack is zero.
Though many interrupts can be simultaneously
pending, a priority order is defined (see Table 6,
“Interrupt Mapping,” on page 24). The RESET pin
has the highest priority.
If the I bit is set, only the TRAP interrupt is enabled.
All interrupts allow the processor to leave the
WAIT low power mode.
Software Interrupt. The software interrupt is the
executable instruction TRAP. The interrupt is
recognized when the TRAP instruction is
executed, regardless of the state of the I bit. When
the interrupt is recognized, it is serviced according
to the flowchart on Figure 13.
22/144
ITA, ITB interrupts. The ITA (PD3), ITB (PD4),
pins can generate an interrupt when a falling edge
occurs on these pins, if these interrupts are
enabled with the ITAITE, ITBITE bits respectively
in the miscellaneous register and the I bit of the CC
register is reset. When an enabled interrupt
occurs, normal processing is suspended at the
end of the current instruction execution. It is then
serviced according to the flowchart on Figure 13.
Software in the ITA or ITB service routine must
reset the cause of this interrupt by clearing the
ITALAT, ITBLAT or ITAITE, ITBITE bits in the
miscellaneous register.
Peripheral Interrupts. Different peripheral
interrupt flags are able to cause an interrupt when
they are active if both the I bit of the CC register is
reset and if the corresponding enable bit is set. If
either of these conditions is false, the interrupt is
latched and thus remains pending.
The interrupt flags are located in the status
register. The Enable bits are in the control register.
When an enabled interrupt occurs, normal
processing is suspended at the end of the current
instruction execution. It is then serviced according
to the flowchart on Figure 13.
The general sequence for clearing an interrupt is
an access to the status register while the flag is set
followed by a read or write of an associated
register. Note that the clearing sequence resets
the internal latch. A pending interrupt (i.e. waiting
for being enabled) will therefore be lost if the clear
sequence is executed.
ST72774/ST727754/ST72734
INTERRUPTS (Cont’d)
Figure 13. Interrupt Processing Flowchart
FROM RESET
Y
TRAP?
N
N
I BIT SET?
Y
N
INTERRUPT?
FETCH NEXT INSTRUCTION
Y
N
EXECUTE INSTRUCTION
IRET?
STACK PC, X, A, CC
SET I BIT
LOAD PC FROM INTERRUPT VECTOR
Y
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
VR01172D
23/144
ST72774/ST727754/ST72734
INTERRUPTS (Cont’d)
Table 6. Interrupt Mapping
Source
Block
RESET
TRAP
USB
Reset
Software
End Suspend Interrupt
DDC/CI
DDC/CI Interrupt
DDC1/2B
Port D bit 4
Port D bit 3
TIM
I2C
USB
Description
DDC1/2B Interrupt
External Interrupt ITB
External Interrupt ITA
Input Capture 1
Input Capture 2
Output Compare 1
Output Compare 2
Timer Overflow
I2C Peripheral Interrupts
USB Interrupt
Register
Label
N/A
N/A
USBISTR
DDCSR1
DDCSR2
DDCDCR
N/A
N/A
ESUSP
Maskable
by I-bit
no
no
yes
**
yes
FFF8h-FFF9h
EDF
ITBLAT
ITALAT
ICF1
ICF2
OCF1
OCF2
TOF
yes
yes
yes
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
yes
FFF0h-FFF1h
yes
FFEEh-FFEFh
yes
FFECh-FFEDh
I2CSR1
I2CSR2
**
yes
FFEAh-FFEBh
USBISTR
**
yes
FFE6h-FFE7h
MISCR
TIMSR
Flag
Vector Address
Priority
Order
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
Highest
Priority
** Many flags can cause an interrupt, see peripheral interrupt status register description.
24/144
Lowest
Priority
ST72774/ST727754/ST72734
3.4 POWER SAVING MODES
3.4.1 WAIT Mode
This mode is a low power consumption mode. The
WFI instruction places the MCU in WAIT mode:
The internal clock remains active but all CPU
processing is stopped; however, all other
peripherals are still running.
Figure 14. WAIT Flow Chart
WFI INSTRUCTION
Note: In WAIT mode, DMA accesses (DDC, USB)
are possible.
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
During WAIT mode, the I bit in the condition code
register is cleared to enable all interrupts, which
causes the MCU to exit WAIT mode, causes the
corresponding interrupt vector to be fetched, the
interrupt routine to be executed and normal
processing to resume. A reset causes the program
counter to fetch the reset vector and processing
starts as for a normal reset.
Table 5 gives a list of the different sections
affected by the low power modes. For detailed
information on a particular device, please refer to
the corresponding part.
I-BIT
ON
ON
OFF
CLEARED
N
RESET
N
Y
INTERRUPT
Y
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
3.4.2 HALT Mode
The HALT mode is the MCU lowest power
consumption mode. Meanwhile, the HALT mode
also stops the oscillator stage completely which is
the most critical condition in CRT monitors.
For this reason, the HALT mode has been disabled
and its associated HALT instruction is now
considered as illegal and will generate a reset.
ON
ON
ON
SET
IF RESET
4096 CPU CLOCK
CYCLES DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is
popped.
25/144
ST72774/ST727754/ST72734
3.5 MISCELLANEOUS REGISTER
Bit 4= FAST Fast Mode.
MISCELLANEOUS REGISTER (MISCR)
Address: 0009h — Read/Write
Reset Value: 0001 0000 (10h)
7
0
VSYNC FLY_S HSYNC
FAST ITBLAT ITALAT ITBITE ITAITE
SEL
YN
DIVEN
Bit 7= VSYNCSEL DDC1 VSYNC Selection.
This bit is set and cleared by software. It is used to
choose the VSYNC signal in DDC1 mode.
0: VSYNCI selected
1: VSYNCI2 selected
Note: VSYNCI 2 is only available for the DDC cell,
not for the SYNC processor cell.
This bit is set and cleared by software. It is used to
select the external clock frequency. If the external
clock frequency is 12 MHz, this bit must be at 0,
else if the external frequency is 24 MHz, this bit
must be at 1.
Bit 3= ITBLAT Falling Edge Detector Latch.
This bit is set by hardware when a falling edge
occurs on pin ITB/PD4 in Port D. An interrupt is
generated if ITBITE=1and the I bit in the CC
register = 0. It is cleared by software.
0: No falling edge detected on ITB
1: Falling edge detected on ITB
This bit is set and cleared by software. It is used to
choose the signals the Timing Measurement Unit
(TMU) will analyse.
Bit 2= ITALAT Falling Edge Detector Latch.
This bit is set by hardware when a falling edge
occurs on pin ITA/PD3 in Port D. An interrupt is
generated if ITAITE=1and the I bit in the CC
register = 0. It is cleared by software.
0: horizontal and vertical synchro outputs analysis
1: horizontal and vertical Flyback inputs analysis
0: No falling edge detected on ITA
1: Falling edge detected on ITA
Bit 5= HSYNCDIVEN HSYNCDIV Enable.
Bit 1= ITBITE ITB Interrupt Enable .
This bit is set and cleared by software.
Bit 6= FLY_SYN Flyback or Synchro Switch.
This bit is set and cleared by software. It is used to
enable the output of the HSYNCO output on PC0.
0: HSYNCDIV disabled
1:HSYNCDIV enabled
0: ITB interrupt disabled
1: ITB interrupt enabled
Bit 0= ITAITE ITA Interrupt Enable .
This bit is set and cleared by software.
0: ITA interrupt disabled
1: ITA interrupt enabled
26/144
ST72774/ST727754/ST72734
4 ON-CHIP PERIPHERALS
4.1 I/O PORTS
4.1.1 Introduction
The I/O ports allow the transfer of data through
digital inputs and outputs, and, for specific pins,
the input of analog signals or the Input/Output of
alternate signals for on-chip peripherals (DDC,
TIMER...).
Each pin can be programmed independently as
digital input or digital output. Each pin can be an
analog input when an analog switch is connected
to the Analog to Digital Converter (ADC).
Figure 15. I/O Pin Typical Circuit
Alternate enable
Alternate 1
output
VDD
0
P-BUFFER
(if required)
Data Bus
Common Analog Rail
DR
latch
PULL-UP (if required)
Alternate enable
DDR
latch
PAD
Analog Enable
(ADC)
Analog
Switch (if required)
DDR SEL
N-BUFFER
DR SEL
1
Alternate Enable
0
Digital Enable
VSS
Alternate Input
Note: This is the typical I/O pin configuration. For cost optimization, each port is customized with a specific configuration.
27/144
5
ST72774/ST727754/ST72734
I/O PORTS (Cont’d)
Table 7. I/O Pin Functions
DDR
MODE
0
Input
1
Output
4.1.2 Common Functional Description
Each port pin of the I/O Ports can be individually
configured under software control as either input
or output.
Each bit of a Data Direction Register (DDR)
corresponds to an I/O pin of the associated port.
This corresponding bit must be set to configure its
associated pin as output and must be cleared to
configure its associated pin as input (Table 7, “. I/O
Pin Functions,” on page 28). The Data Direction
Registers can be read and written.
The typical I/O circuit is shown on Figure 15. Any
write to an I/O port updates the port data register
even if it is configured as input. Any read of an I/O
port returns either the data latched in the port data
register (pins configured as output) or the value of
the I/O pins (pins configured as input).
Remark: when an I/O pin does not exist inside an
I/O port, the returned value is a logic one (pin
configured as input).
At reset, all DDR registers are cleared, which
configures all port’s I/Os as inputs with or without
pull-ups (see Table 8 to Table 12 I/O Ports
Register Map). The Data Registers (DR) are also
initialized at reset.
4.1.2.1 Input mode
When DDR=0, the corresponding I/O is configured
in Input mode.
In this case, the output buffer is switched off, the
state of the I/O is readable through the Data
Register address, but the I/O state comes directly
28/144
from the CMOS Schmitt Trigger output and not
from the Data Register output.
4.1.2.2 Output mode
When DDR=1, the corresponding I/O is configured
in Output mode.
In this case, the output buffer is activated
according to the Data Register’s content.
A read operation is directly performed from the
Data Register output.
4.1.2.3 Analog input
Each I/O can be used as analog input by adding an
analog switch driven by the ADC.
The I/O must be configured in Input before using it
as analog input.
The CMOS Schmitt trigger is OFF and the analog
value directly input through an analog switch to the
Analog to Digital Converter, when the analog
channel is selected by the ADC.
4.1.2.4 Alternate mode
A signal coming from a on-chip peripheral can be
output on the I/O.
In this case, the I/O is automatically configured in
output mode.
This must be controlled directly by the peripheral
with a signal coming from the peripheral which
enables the alternate signal to be output.
A signal coming from an I/O can be input in a onchip peripheral.
Before using an I/O as Alternate Input, it must be
configured in Input mode (DDR=0). So both
Alternate Input configuration and I/O Input
configuration are the same (with or without pullup). The signal to be input in the peripheral is taken
after the CMOS Schmitt trigger or TTL Schmitt
trigger for SYNC.
The I/O state is readable as in Input mode by
addressing the corresponding I/O Data Register.
ST72774/ST727754/ST72734
Figure 16. Input Structure for SYNC signals
PA [6:3] can be defined as Input lines (without pullup) or as Output Open drain lines.
PA7 and PA[2:0] can be defined as Input lines
(with pull-up) or as Push-pull Outputs.
TTL trigger
HSYNCI Input
VSYNCI Input
Pin
PA [6:3] can be defined as Input lines (without pullup) or as Output Open drain lines.
(no pull-up)
I/O logic (if existing)
VDD
pull-up
TTL trigger
Pin
CSYNCI Input
HFBACK Input
VFBACK Input
I/O logic (if existing)
4.1.3 Port A
PA7 and PA[2:0] can be defined as Input lines
(with pull-up) or as Push-pull Outputs.
Table 8. Port A Description
PORT A
I/O
Input*
Alternate Function
Output
Signal
Condition
PA0
With pull-up
push-pull
OCMP1
OC1E =1
(CR2[TIMER])
PA1
With pull-up
push-pull
-
-
PA2
With pull-up
push-pull
VSYNCI2
VSYNCSEL=1
(MISCR)
PA3
Without pull-up
open-drain
-
-
PA4
Without pull-up
open-drain
-
-
PA5
Without pull-up
open-drain
-
-
PA6
Without pull-up
open-drain
-
-
PA7
With pull-up
push-pull
BLANKOUT
BLKEN = 1
(ENR[SYNC])
*Reset State
29/144
ST72774/ST727754/ST72734
I/O PORTS (Cont’d)
Figure 17. PA0 to PA2, PA7
Alternate enable
Alternate
output
1
VDD
0
P-BUFFER
DR
latch
PULL-UP
DATA BUS
OC1E
DDR
latch
PAD
DDR SEL
N-BUFFER
1
DR SEL
OC1E
0
VSS
CMOS Schmitt Trigger
Figure 18. PA3 to PA6
Alternate enable
DR
latch
Alternate
output
1
0
DDR
latch
PAD
DATA BUS
DDR SEL
N-BUFFER
DR SEL
1
0
Alternate input
30/144
Alternate enable
VSS
CMOS Schmitt Trigger
ST72774/ST727754/ST72734
I/O PORTS (Cont’d)
4.1.4 Port B
The alternate functions are the I/O pins of the onchip DDC SCLD & SCDAD for PB0:1, the I/O pins
of the on-chip I2C SCLI & SCDAI for PB2:3, and 4
bits of port B bit can be used as the Analog source
to the Analog to Digital Converter.
Only one I/O line must be configured as an analog
input at any time. The user must avoid any
situation in which more than one I/O pin is selected
as an analog input simultaneously to avoid device
malfunction.
When the analog function is selected for an I/O pin,
the pull-up of the respective pin of Port B is
disconnected and the digital input is off.
All unused I/O lines should be tied to an
appropriate logic level (either VDD or VSS)
Since the ADC is on the same chip as the
microprocessor, the user should not switch heavily
loaded signals during conversion, if high precision
is required. Such switching will affect the supply
voltages used as analog references. the accuracy
of the conversion depends on the quality of the
power supplies (VDD and VSS). The user must take
special care to ensure that a well regulated
reference voltage is present on the VDD and VSS
pins (power supply variations must be less than
5V/ms). This implies, in particular, that a suitable
decoupling capacitor is used at the VDD pin.
Table 9. Port B Description
PORT B
I/O
Alternate Function
Input*
Output
Signal
Condition
PB0
Without pull-up
Open-drain
SCLD (input with CMOS schmitt trigger or
open drain output)
DDC enable
PB1
Without pull-up
Open-drain
SDAD (input with CMOS schmitt trigger or
open drain output)
DDC enable
PB2
Without pull-up
Open-drain
SCLI (input with CMOS schmitt trigger or
open drain output)
I2C enable
PB3
Without pull-up
Open-drain
SDAI (input with CMOS schmitt trigger or
open drain output)
I2C enable
PB4
With pull-up
Push-pull
Analog input (ADC) (without pull-up)
CH[2:0]=000 (ADCCSR)
PB5
With pull-up
Push-pull
Analog input (ADC) (without pull-up)
CH[2:0]=001 (ADCCSR)
PB6
With pull-up
Push-pull
Analog input (ADC) (without pull-up)
CH[2:0]=010 (ADCCSR)
10-bit output 1 (PWM)
OE0=1 (PWMOE)
PB7
With pull-up
Push-pull
Analog input (ADC) (without pull-up)
CH[2:0]=011 (ADCCSR)
10-bit output 2 (PWM)
OE1=1 (PWMOE)
*Reset state
31/144
ST72774/ST727754/ST72734
I/O PORTS (Cont’d)
Figure 19. PB0 to PB3
Alternate enable
DR
latch
Alternate
output
1
0
DDR
latch
PAD
DATA BUS
DDR SEL
N-BUFFER
DR SEL
1
Alternate enable
0
VSS
CMOS Schmitt Trigger
Alternate input
Figure 20. PB4 to PB7
VDD
P-BUFFER
DR
latch
PULL-UP
DATA BUS
Common Analog Rail
DDR
latch
Analog enable
(ADC)
PAD
Analog
switch
DDR SEL
N-BUFFER
DR SEL
1
VSS
0
CMOS Schmitt Trigger
32/144
ST72774/ST727754/ST72734
I/O PORTS (Cont’d)
4.1.5 Port C
The available port pins of port C may be used as
general purpose I/O.
The alternate functions are the PWM outputs for
PC2:7, HSYNCDIV (HSYNCO divided by 2) for
PC0 and the TMU input for PC1.
Table 10. Port C Description
I/O
PORT C
Input*
Alternate Function
Output
Signal
Condition
PC0
With pull-up
Push-pull
HSYNCDIV (push-pull)
HSYNCDIVEN
=1
(MISCR)
PC1
With pull-up
Push-pull
AV (active video) input (TMU)
-
PC2
With pull-up
Push-pull
10-bit output 3 (PWM)
OE2=1
(PWMOE)
PC3
With pull-up
Push-pull
10-bit output 4 (PWM)
OE3=1
(PWMOE)
PC4
With pull-up
Push-pull
10-bit output 5 (PWM)
OE4=1
(PWMOE)
PC5
With pull-up
Push-pull
10-bit output 6 (PWM)
OE5=1
(PWMOE)
PC6
With pull-up
Push-pull
10-bit output 7 (PWM)
OE6=1
(PWMOE)
PC7
With pull-up
Push-pull
10-bit output 8 (PWM)
OE7=1
(PWMOE)
* Reset State
33/144
ST72774/ST727754/ST72734
I/O PORTS (Cont’d)
Figure 21. PC0, PC2 to PC7
Alternate enable
Alternate
output
1
VDD
0
P-BUFFER
DR
latch
PULL-UP
OC1E
DDR
latch
PAD
DATA BUS
DDR SEL
N-BUFFER
DR SEL
1
0
OC1E
VSS
CMOS Schmitt Trigger
Figure 22. PC1
VDD
DR
latch
P-BUFFER
PULL-UP
DATA BUS
DDR
latch
PAD
DDR SEL
N-BUFFER
DR SEL
AV
1
0
VSS
CMOS Schmitt Trigger
34/144
ST72774/ST727754/ST72734
I/O PORTS (Cont’d)
4.1.6 Port D
The Port D I/O pins are normally used for the input
and output of video synchronization signals of the
Sync Processor, but are set to I/O Input with pullup upon reset. The I/O mode can be set
individually for each port bit to Input with pull-up
and output push-pull through the Port D DDR.
The configuration to support the Sync Processor
requires that the SYNOP (bit7) and CLMPEN (bit6)
of the ENR (Enable Register of SYNC) is reset.
SYNOP enables port D bits 0,1 and CLMPEN
enables Port D bit 6 to the sync outputs.
Port D, bit 4:3 are the alternate inputs ITA, ITB, (for
the interrupt falling edge detector).
When a falling edge occurs on these inputs, an
interrupt will be generated depending on the status
of the INTX (ITAITE & ITBITE) bits in the MISCR
Register.
Port D, bit 6 is switched to the alternate
(CLAMPOUT) by resetting the CLMPEN bit of the
ENR Register inside SYNC block.
If the SYNC function is selected, Port D bit 5 and 3
MUST be set as input to enable the HFBACK or
VFBACK timing inputs.
Note: As these inputs are switched from normal
I/O functionality, the video synchronization signals
may also be monitored directly through the Port D
Data Register for such tasks as checking for the
presence of video signals or checking the polarity of
Horizontal and Vertical synchronization signals
(when the Sync Inputs are switched directly to the
outputs using the multiplexers of the Sync Processor).
Table 11. Port D Description
PORT D
I/O
Input*
Alternate Function
Output
PD0
With pull-up
Push-pull
PD1
With pull-up
Push-pull
PD2
With pull-up
Push-pull
PD3
With pull-up
Push-pull
Signal
Condition
VSYNCO
SYNOP=0
(push pull output)
(ENR [SYNC])
HSYNCO
SYNOP=0
(push pull output)
(ENR [SYNC])
CSYNCI (input with TTL Schmitt
trigger & pull-up)
-
ITA (input with CMOS Schmitt
trigger & pull-up)
-
VFBACK (input with TTL Schmitt
trigger & pull-up)
-
PD4
With pull-up
Push-pull
ITB (input with CMOS Schmitt
trigger & pull-up)
-
PD5
With pull-up
Push-pull
HFBACK (input with TTL Schmitt
trigger & pull-up)
-
PD6
With pull-up
Push-pull
CLAMPOUT
CLMPEN=0
(push pull output)
(ENR [SYNC])
* Reset state
35/144
ST72774/ST727754/ST72734
I/O PORTS (Cont’d)
Figure 23. PD2 to PD5
DATA BUS
VDD
P-BUFFER
DR
latch
PULL-UP
DDR
latch
PAD
DDR SEL
N-BUFFER
1
DR SEL
VSS
0
CMOS Schmitt Trigger
alternate input
CSYNCI Input
HFBACK Input
VFBACK Input
TTL Schmitt Trigger
Figure 24. PD0 to PD1
Alternate enable
DATA BUS
Alternate
output
1
VDD
0
P-BUFFER
DR
latch
PULL-UP
Alternate enable
DDR
latch
PAD
DDR SEL
N-BUFFER
DR SEL
Alternate input
36/144
1
0
Alternate enable
VSS
CMOS Schmitt Trigger
ST72774/ST727754/ST72734
I/O PORTS (Cont’d)
Figure 25. PD6
Alternate enable
DATA BUS
Alternate
output
1
VDD
0
P-BUFFER
DR
latch
PULL-UP
Alternate enable
DDR
latch
PAD
DDR SEL
N-BUFFER
DR SEL
Alternate input
1
0
Alternate enable
VSS
CMOS Schmitt Trigger
VSYNCI2 input
TTL Schmitt Trigger
37/144
ST72774/ST727754/ST72734
I/O PORTS (Cont’d)
4.1.7 Register Description
Data Registers (PxDR)
Data Direction Registers (PxDDR)
Read /Write
Reset Value: 0000 0000 (00h)
Read/Write
Reset Value: 0000 0000 (00h) (as inputs)
7
0
MSB
LSB
7
0
MSB
LSB
Table 12. I/O Ports Register Map
Address
(Hex.)
Register
Name
7
00
PADR
MSB
LSB
01
PADDR
MSB
LSB
02
PBDR
MSB
LSB
03
PBDDR
MSB
LSB
04
PCDR
MSB
LSB
05
PCDDR
MSB
LSB
06
PDDR
MSB
LSB
07
PDDDR
MSB
LSB
38/144
6
5
4
3
2
1
0
ST72774/ST727754/ST72734
4.2 WATCHDOG TIMER (WDG)
4.2.1 Introduction
The Watchdog timer is used to detect the
occurrence of a software fault, usually generated
by external interference or by unforeseen logical
conditions, which causes the application program
to abandon its normal sequence. The Watchdog
circuit generates an MCU reset on expiry of a
programmed time period, unless the program
refreshes the counter’s contents before the T6 bit
becomes cleared.
4.2.2 Main Features
Programmable timer (64 increments of 49152
CPU cycles)
■ Programmable reset
■ Reset (if watchdog activated) when the T6 bit
reaches zero
■
Figure 26. Watchdog Block Diagram
RESET
WATCHDOG CONTROL REGISTER (CR)
WDGA
T6
T5
T4
T3
T2
T1
T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER
÷49152
4.2.3 Functional Description
The counter value stored in the CR register (bits
T6:T0), is decremented every 49,152 machine
cycles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T6:T0) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates a
reset cycle pulling low the reset pin for typically
500ns.
The application program must write in the CR
register at regular intervals during normal
operation to prevent an MCU reset. The value to
be stored in the CR register must be between FFh
and C0h (see Table 13 . Watchdog Timing (fCPU =
8 MHz)):
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an immediate reset
– The T5:T0 bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
39/144
ST72774/ST727754/ST72734
Table 13. Watchdog Timing (fCPU = 8 MHz)
CR Register
initial value
WDG timeout period
(ms)
Max
FFh
393.216
Min
C0h
6.144
4.2.5 Register Description
CONTROL REGISTER (CR)
Read /Write
Reset Value: 0111 1111 (7Fh)
7
Notes: Following a reset, the watchdog is
disabled. Once activated it cannot be disabled,
except by a reset.
The T6 bit can be used to generate a software
reset (the WDGA bit is set and the T6 bit is
cleared).
WDGA
0
T6
T5
T4
T3
T2
T1
T0
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
4.2.4 Interrupts
None.
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
Table 14. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
08
40/144
Register
Label
7
6
5
4
3
2
1
0
WDGCR
WDGA
T6
T5
T4
T3
T2
T1
T0
Reset Value
0
1
1
1
1
1
1
1
ST72774/ST727754/ST72734
4.3 16-BIT TIMER (TIM)
4.3.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input
signals ( input capture) or generation of up to two
output waveforms (output compare and PWM).
Pulse lengths and waveform periods can be
modulated from a few microseconds to several
milliseconds using the timer prescaler and the
CPU clock prescaler.
4.3.2 Main Features
■ Programmable prescaler: fcpu divided by 2, 4 or
8.
■ Overflow status flag and maskable interrupt
■ External clock input (must be at least 4 times
slower than the CPU clock speed) with the
choice of active edge
■ Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
4.3.3 Functional Description
4.3.3.1 Counter
The principal block of the Programmable Timer is a
16-bit free running counter and its associated 16bit registers:
Counter Registers
– Counter High Register (CHR) is the most significant byte (MSB).
– Counter Low Register (CLR) is the least significant byte (LSB).
Alternate Counter Registers
– Alternate Counter High Register (ACHR) is the
most significant byte (MSB).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LSB).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (overflow
flag), (see note page 43).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■
Input capture functions with
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 15 Clock
Control Bits. The value in the counter register
repeats every 131.072, 262.144 or 524.288
internal processor clock cycles depending on the
CC1 and CC0 bits.
– 1 dedicated maskable interrupt
■
■
■
Pulse width modulation mode (PWM)
One pulse mode
5 alternate functions on I/O ports*
The Block Diagram is shown in Figure 27.
Note: Some external pins are not available on all devices.
Refer to the device pin out description.
41/144
ST72774/ST727754/ST72734
16-BIT TIMER (Cont’d)
Figure 27. Timer Block Diagram
ST7 INTERNAL BUS
CPU CLOCK
MCU-PERIPHERAL INTERFACE
8 low
8
8
low
8
low
8
high
8
high
8
low
8
high
EXEDG
8
low
8-bit
buffer
high
8 high
16
1/2
1/4
1/8
16 BIT
FREE RUNNING
COUNTER
OUTPUT
COMPARE
REGISTER
2
OUTPUT
COMPARE
REGISTER
1
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
1
2
COUNTER
ALTERNATE
REGISTER
16
16
16
CC1 CC0
TIMER INTERNAL BUS
16
EXTCLK
OVERFLOW
DETECT
CIRCUIT
16
OUTPUT COMPARE
CIRCUIT
6
ICF1 OCF1 TOF ICF2 OCF2
0
0
EDGE DETECT
CIRCUIT1
ICAP1
EDGE DETECT
CIRCUIT2
ICAP2
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
CR1
42/144
OCMP1
LATCH2
OCMP2
0
SR
TIMER INTERRUPT
LATCH1
OC1E OC2E OPM PWM
CC1
CC0 IEDG2 EXEDG
CR2
ST72774/ST727754/ST72734
16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
Beginning of the sequence
At t0
Read MSB
LSB is buffered
Other
instructions
Returns the buffered
At t0 +Dt Read LSB
LSB value at t0
Clearing the overflow interrupt request is done by:
1. Reading the SR register while the TOF bit is
set.
2. An access (read or write) to the CLR register.
Notes: The TOF bit is not cleared by accesses to
ACLR register. This feature allows simultaneous
use of the overflow function and reads of the free
running counter at random times (for example, to
measure elapsed time) without the risk of clearing
the TOF bit erroneously.
The timer is not affected by WAIT mode.
Sequence completed
The user must read the MSB first, then the LSB
value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MSB several times.
After a complete reading sequence, if only the CLR
register or ACLR register are read, they return the
LSB of the count value at the time of the read.
An overflow occurs when the counter rolls over
from FFFFh to 0000h then:
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt
remains pending to be issued as soon as they are
both true.
4.3.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in CR2 register.
The status of the EXEDG bit determines the type
of level transition on the external clock pin
EXTCLK that will trigger the free running counter.
The counter is synchronised with the falling edge
of the internal CPU clock.
At least four falling edges of the CPU clock must
occur between two consecutive active edges of
the external clock; thus the external clock
frequency must be less than a quarter of the CPU
clock frequency.
43/144
ST72774/ST727754/ST72734
16-BIT TIMER (Cont’d)
Figure 28. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000
COUNTER REGISTER
0001
0002
0003
OVERFLOW FLAG TOF
Figure 29. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FFFC
FFFD
0000
0001
OVERFLOW FLAG TOF
Figure 30. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
OVERFLOW FLAG TOF
44/144
FFFC
FFFD
0000
ST72774/ST727754/ST72734
16-BIT TIMER (Cont’d)
4.3.3.3 Input Capture
In this section, the index, i, may be 1 or 2.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free
running counter after a transition detected by the
ICAP i pin (see figure 5).
ICiR
MS Byte
LS Byte
ICiHR
ICiLR
IC i Rregister is a read-only register.
The active transition is software programmable
through the IEDGi bit of the Control Register (CRi).
Timing resolution is one count of the free running
counter: (fCPU/(CC1.CC0)).
Procedure
To use the input capture function select the
following in the CR2 register:
– Select the timer clock (CC1-CC0) (see Table 15
Clock Control Bits).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit.
And select the following in the CR1 register:
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit.
When an input capture occurs:
– ICFi bit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 32).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both
conditions become true.
Clearing the Input Capture interrupt request is
done by:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
After reading the ICiHR register, transfer of input
capture data is inhibited until the ICiLR register is
also read.
The ICiR register always contains the free running
counter value which corresponds to the most
recent input capture.
– Set the ICIE bit to generate an interrupt after an
input capture.
45/144
ST72774/ST727754/ST72734
16-BIT TIMER (Cont’d)
Figure 31. Input Capture Block Diagram
ICAP1
ICAP2
(Control Register 1) CR1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
(Status Register) SR
ICF1
IC1R
IC2R
ICF2
0
16-BIT FREE RUNNING
CC1
CC0
COUNTER
Figure 32. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
ICAPi PIN
ICAPi FLAG
ICAPi REGISTER
Note: Active edge is rising edge.
46/144
0
(Control Register 2) CR2
16-BIT
COUNTER REGISTER
0
FF03
IEDG2
ST72774/ST727754/ST72734
16-BIT TIMER (Cont’d)
4.3.3.4 Output Compare
In this section, the index, i, may be 1 or 2.
This function can be used to control an output
waveform or indicating when a period of time has
elapsed.
When a match is found between the Output
Compare register and the free running counter, the
output compare function:
– A timer interrupt is generated if the OCIE bit is
set in the CR2 register and the I bit is cleared in
the CC register (CC).
Clearing the output compare interrupt request is
done by:
3. Reading the SR register while the OCFi bit is
set.
4. An access (read or write) to the OCiLR register.
– Assigns pins with a programmable value if the
OCIE bit is set
Note: After a processor write cycle to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
– Sets a flag in the status register
If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not appear
when match is found but an interrupt could be
generated if the OCIE bit is set.
– Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the free
running counter each timer clock cycle.
OCiR
MS Byte
LS Byte
OCiHR
OCiLR
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
Timing resolution is one count of the free running
counter: (fCPU/(CC1.CC0)).
Procedure
To use the output compare function, select the
following in the CR2 register:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
function.
– Select the timer clock (CC1-CC0) (see Table 15
Clock Control Bits).
And select the following in the CR1 register:
– Select the OLVLi bit to applied to the OCMP i pins
after the match occurs.
– Set the OCIE bit to generate an interrupt if it is
needed.
When match is found:
The value in the 16-bit OCiR register and the OLVi
bit should be changed after each successful
comparison in order to control an output waveform
or establish a new elapsed timeout.
The OCiR register value required for a specific
timing application can be calculated using the
following formula:
∆ OCiR =
∆t * fCPU
(CC1.CC0)
Where:
∆t
= Desired output compare period (in
seconds)
fCPU
= Internal clock frequency
CC1-CC0 = Timer clock prescaler
The following procedure is recommended to
prevent the OCFi bit from being set between the
time it is read and the write to the OCiR register:
– Write to the OCiHR register (further compares
are inhibited).
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset and stays low
until valid compares change it to a high level).
47/144
ST72774/ST727754/ST72734
16-BIT TIMER (Cont’d)
Figure 33. Output Compare Block Diagram
16 BIT FREE RUNNING
COUNTER
OC1E OC2E
CC1
CC0
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
16-bit
OC1R
OCIE
OLVL2
OLVL1
Latch
1
OCMP1
Latch
2
OCMP2
16-bit
OC2R
OCF1
OCF2
0
0
0
(Status Register) SR
Figure 34. Output Compare Timing Diagram, Internal Clock Divided by 2
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER
OUTPUT COMPARE REGISTER
COMPARE REGISTER LATCH
OCFi AND OCMPi PIN (OLVLi=1)
48/144
FFFC FFFD FFFD FFFE FFFF 0000
CPU writes FFFF
FFFF
ST72774/ST727754/ST72734
16-BIT TIMER (Cont’d)
4.3.3.5 Forced Compare Mode
In this section i may represent 1 or 2.
The following bits of the CR1 register are used:
FOLV2 FOLV1 OLVL2
– Set the OPM bit.
– Select the timer clock CC1-CC0 (see Table 15
Clock Control Bits).
Load the OC1R register with the value
corresponding to the length of the pulse (see the
formula in Section 4.3.3.7).
OLVL1
When the FOLVi bit is set, the OLVLi bit is copied
to the OCMPi pin. The FOLVi bit is not cleared by
software, only by a chip reset. The OLV i bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1).
One pulse mode cycle
When
event occurs
on ICAP1
OCMP1 = OLVL2
The OCFi bit is not set, and thus no interrupt
request is generated.
4.3.3.6 One Pulse Mode
One Pulse mode enables the generation of a pulse
when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure
To use one pulse mode, select the following in the
the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit.
And select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function.
Counter is
initialized
to FFFCh
When
Counter
= OC1R
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the
counter is initialized to FFFCh and OLVL2 bit is
loaded on the OCMP1 pin. When the value of the
counter is equal to the value of the contents of the
OC1R register, the OLVL1 bit is output on the
OCMP1 pin, (See Figure 35).
Note: The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an Output Compare interrupt.
The ICF1 bit is set when an active edge occurs and
can generate an interrupt if the ICIE bit is set.
When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
Figure 35. One Pulse Mode Timing
COUNTER
....
FFFC FFFD FFFE
2ED0 2ED1 2ED2
FFFC FFFD
2ED3
ICAP1
OCMP1
OLVL2
OLVL1
OLVL2
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
49/144
ST72774/ST727754/ST72734
16-BIT TIMER (Cont’d)
4.3.3.7 Pulse Width Modulation Mode
Pulse Width Modulation mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
The pulse width modulation mode uses the
complete Output Compare 1 function plus the
OC2R register.
Procedure
To use pulse width modulation mode select the
following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC1R register.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC2R register.
And select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicated
to the output compare 1 function.
– Set the PWM bit.
– Select the timer clock (CC1-CC0) (see Table 15
Clock Control Bits).
Load the OC2R register with the value
corresponding to the period of the signal.
Load the OC1R register with the value
corresponding to the length of the pulse if
(OLVL1=0 and OLVL2=1).
If OLVL1=1 and OLVL2=0 the length of the pulse is
the difference between the OC2R and OC1R
registers.
The OCiR register value required for a specific
timing application can be calculated using the
following formula:
OCiR Value =
t * fCPU
-5
(CC1.CC0)
Where:
– t = Desired output compare period (seconds)
– fCPU = Internal clock frequency (see Miscellaneous register)
– CC1-CC0 = Timer clock prescaler
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 36).
Pulse Width Modulation cycle
When
Counter
= OC1R
When
Counter
= OC2R
OCMP1 = OLVL1
OCMP1 = OLVL2
Counter is reset
to FFFCh
Note: After a write instruction to the OCiHR register, the
output compare function is inhibited until the OCiLR
register is also written.
The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited. The Input Capture
interrupts are available.
When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
Figure 36. Pulse Width Modulation Mode Timing
COUNTER
34E2
FFFC FFFD FFFE
2ED0 2ED1 2ED2
OLVL2
OCMP1
compare2
OLVL1
compare1
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
50/144
34E2
FFFC
OLVL2
compare2
ST72774/ST727754/ST72734
4.3.4 Register Description
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the
alternate counter.
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is not cleared by software, only by a chip
reset.
CONTROL REGISTER 1 (CR1)
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is not cleared by software, only by a chip
reset.
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0: No effect.
1:Forces the OLVL2 bit to be copied to the
OCMP2 pin.
0: No effect.
1: Forces OLVL1 to be copied to the OCMP1
pin.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R
register and OCxE is set in the CR2 register. This
value is copied to the OCMP1 pin in One Pulse
Mode and Pulse Width Modulation mode.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the
TOF bit of the SR register is set.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition on
the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin
whenever a successful comparison occurs with
the OC1R register and the OC1E bit is set in the
CR2 register.
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ST72774/ST727754/ST72734
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Bit 3, 2 = CC1-CC0 Clock Control.
Read/Write
The value of the timer clock depends on these bits:
Reset Value: 0000 0000 (00h)
Table 15. Clock Control Bits
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
CC1
CC0
Timer Clock
0
0
0
1
1
0
fCPU / 4
fCPU / 2
fCPU / 8
1
1
Bit 7 = OC1E Output Compare 1 Enable.
0: Output Compare 1 function is enabled, but
the OCMP1 pin is a general I/O.
1: Output Compare 1 function is enabled, the
OCMP1 pin is dedicated to the Output Compare 1 capability of the timer.
Bit 6 = OC2E Output Compare 2 Enable.
0: Output Compare 2 function is enabled, but
the OCMP2 pin is a general I/O.
1: Output Compare 2 function is enabled, the
OCMP2 pin is dedicated to the Output Compare 2 capability of the timer.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can
be used to trigger one pulse on the OCMP1
pin; the active transition is given by the
IEDG1 bit. The length of the generated pulse
depends on the contents of the OC1R register.
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs
a programmable cyclic signal; the length of
the pulse depends on the value of OC1R register; the period depends on the value of
OC2R register.
52/144
External Clock (where
available)
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition on
the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition on
the external clock pin EXTCLK will trigger the free
running counter.
0: A falling edge triggers the free running counter.
1: A rising edge triggers the free running counter.
ST72774/ST727754/ST72734
16-BIT TIMER (Cont’d)
STATUS REGISTER (SR)
Read Only
Bit 2-0 = Unused.
Reset Value: 0000 0000 (00h)
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
The three least significant bits are not used.
Read Only
Reset Value: Undefined
7
ICF1
0
OCF1
TOF
ICF2
OCF2
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred. To clear this
bit, first read the SR register, then read or
write the low byte of the IC1R (IC1LR) register.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then
read or write the low byte of the OC1R
(OC1LR) register.
Bit 5 = TOF Timer Overflow.
0: No timer overflow (reset value).
1:The free running counter rolled over from
FFFFh to 0000h. To clear this bit, first read
the SR register, then read or write the low
byte of the CR (CLR) register.
7
0
MSB
LSB
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the
input capture 1 event).
7
0
MSB
LSB
OUTPUT
(OC1HR)
COMPARE
1
HIGH
REGISTER
Note: Reading or writing the ACLR register does not clear
TOF.
Read/Write
Reset Value: 1000 0000 (80h)
Bit 4 = ICF2 Input Capture Flag 2.
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
0: No input capture (reset value).
1: An input capture has occurred.To clear this
bit, first read the SR register, then read or
write the low byte of the IC2R (IC2LR) register.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then
read or write the low byte of the OC2R
(OC2LR) register.
7
0
MSB
LSB
OUTPUT
(OC1LR)
COMPARE
1
LOW
REGISTER
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
53/144
ST72774/ST727754/ST72734
16-BIT TIMER (Cont’d)
OUTPUT COMPARE
(OC2HR)
2
HIGH
REGISTER
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
7
0
MSB
LSB
OUTPUT
(OC2LR)
COMPARE
2
LOW
7
0
MSB
LSB
ALTERNATE
(ACHR)
COUNTER
HIGH
REGISTER
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
7
0
MSB
LSB
REGISTER
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
MSB
LSB
COUNTER HIGH REGISTER (CHR)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
7
0
MSB
LSB
ALTERNATE
(ACLR)
COUNTER
LOW
REGISTER
Read/Write
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to SR register does not clear the TOF bit in SR
register.
7
0
MSB
LSB
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
COUNTER LOW REGISTER (CLR)
Read/Write
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the SR register clears the TOF bit.
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
7
0
MSB
LSB
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
54/144
ST72774/ST727754/ST72734
16-BIT TIMER (Cont’d)
Table 16. 16-Bit Timer Register Map
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
11
CR2
OC1E
OC2E
OPM
PWM
CC1
CC0
IEDG2
EXEDG
12
CR1
ICIE
OCIE
TOIE
FOLV2
FOLV1
OLVL2
IEDG1
OLVL1
13
SR
ICF1
OCF1
TOF
ICF2
OCF2
0
0
0
14
IC1HR
MSB
LSB
15
IC1LR
MSB
LSB
16
OC1HR
MSB
LSB
17
OC1LR
MSB
LSB
18
CHR
MSB
LSB
19
CLR
MSB
LSB
1A
ACHR
MSB
LSB
1B
ACLR
MSB
LSB
1C
IC2HR
MSB
LSB
1D
IC2LR
MSB
LSB
1E
OC2HR
MSB
LSB
1F
OC2LR
MSB
LSB
55/144
ST72774/ST727754/ST72734
4.4 SYNC PROCESSOR (SYNC)
4.4.1 Introduction
The Sync processor handles all the management
tasks of the video synchronization signals, and is
used with the timer and software to provide
information and status on the video standard and
timings. This block supports multiple video
standards such as: Separate Sync, Composite
Sync and (via an external extractor) Sync on
Green. The internal clock in the Sync processor is
4 MHz.
–
–
–
–
Analyzer Mode
– Measure the number of scan lines per frame to
simplify OSD vertical centering
– Detect HSYNCI reaching too high a frequency
– Detect pre/post equalization pulses
– Measure the low level of HSYNCO or HFBACK
■
4.4.2 Main Features
■ Input Processing
– Presence of incoming signals (edge detection)
– Read the HSYNCI / VSYNCI input signal levels
– Measure the signal periods
– Detect the sync polarities
– Detect the composite sync and extract VSYNCO
■
Control the sync output polarities
Generate free-running frequencies
Generate a video blanking signal
Generate a clamping signal or a Moire signal
Corrector Mode
– Inhibit Pre/Post equalization pulses
– Program VSYNCO pulse width extension
– Extend VSYNCO pulse widths during:
post-equalization pulse detection only
pre and post-equalization pulse detection
■
Note: Some external pins are not available on all devices.
Refer to the device pinout description.
Output Processing
Figure 37. Sync Processor Block Diagram
ICAP1 TIMER
Latch
Pulse Detect
1
VSYNCI1
V Sync O
Polarity
VSYNCI
LCV1
VSYNCI2
0
HVSEL
LD
Capture
Register
Vsync*
Control
Logic
VFBACK
LCV1
Sync
&
Edge
Detect
Up / Down
EN
5-Bit Counter
CLK
fINT
(see note)
LCV0
Prescaler
HSYNCI1
Latch
HVSEL
Pulse Detect
1
0
PSCD
0
1
Latch
Pulse Detect
HVGEN
0
SYNOP
V Sync
Correction 1
1
BLKEN
Blanking
Generator
0
FBSEL
V
S
Y HFBACK 0
N
C
1
O
Sync Generator
Sync Analyzer
Sync Corrector
Hardware Block
VSYNCO
BLANKOUT
VSYNC Generator
40 - 200 Hz
Typical Pulse Width
20 - 256 µs
HSYNC Generator
15 - 200 kHz
Duty cycle range
(Positive polarity)
3 - 40 %
FBSEL
ICAP2 TIMER
H-Inhibit
ON/OFF
HSYNCI / CSYNCI
HSYNCI2
CSYNCI
Latch Latch
00
1F
match match
Polarity
Detector
SYNOP
HSYNCO
H Sync O
Polarity
SCI0
1
H Sync O
Correction
Back Porch
Clamp
Generator
0
HVGEN
Note: CLK is fINT/2 in fast mode (see note in Clock System section)
HFBACK
Clamp
Polarity
CLPINV
Other
CLAMPOUT
00
CLMPEN
Pull-Up Resistor (if existing)
56/144
VFBACK
BP1, BP0
VR02071C
ST72774/ST727754/ST72734
SYNC PROCESSOR (SYNC) (Cont’d)
4.4.3 Input Signals
The Sync Processor has the following inputs (TTL
level):
– VSYNCI1 Vertical Sync input1
– HSYNCI1 Horizontal Sync input1 or Composite
sync
– VSYNCI2 Vertical Sync input2
– HSYNCI2 Horizontal Sync input2 or Composite
sync
Note: The above input pairs can be used for DSUB or
BNC connectors. To select these inputs use the
HVSEL bit in the POLR register.
– CSYNCI Sync on Green (external extractor)
Note: If the CSYNCI pin is needed for another I/O function, the composite sync signal can be connected to
HSYNCI using the SCI0 bit in the MCR register.
– HFBACK Horizontal Flyback input
– VFBACK Vertical Flyback input
4.4.4 Input Signal Waveforms
– The input signals must contain only synchronization pulses. In case of serration pulses on CSYNCI/HSYNCI, the pulse width should be less than
8µs.
– The VSYNCI signal is internally connected to
Timer Input Capture 1 (ICAP1).
– The HSYNCI or CSYNCI signal, prescaled by
256, is internally connected to Timer Input Capture 2 (ICAP2).
– Typical timing range: See Figure 38 and 39
– If the timer clock is 2 MHz (external oscillator frequency 24 MHz):
PV accuracy = +/- 1 Timer clock (500ns)
4.4.5 Output Signals
The Sync Processor has the following outputs:
HSYNCO Horizontal Sync Output
Enable: SYNOP bit in ENR register
Programmable polarity:
HS0/HS1 bits in MCR register
In case of composite sync signal, the signal can be
blanked by software during the vertical period
(HINH bit in ENR register).
In case of separate sync, no blanking is generated.
VSYNCO Vertical Sync Output
Enable: SYNOP bit in ENR register
Programmable polarity:
VOP bit in the MCR register
In case of composite sync the delay of the
extracted Vsync signal is:
minimum: 500ns + HSYNCO pulse width
maximum: 8750ns (max. threshold in extraction mode)
PH*256 accuracy = +/- 1 Timer clock (500ns)
(PV= Vertical pulse, PH = Horizontal pulse)
57/144
ST72774/ST727754/ST72734
SYNC PROCESSOR (SYNC) (Cont’d)
Figure 38. Typical Horizontal Sync Input Timing
or:
5µs < Typical Hor. Total time < 66.66µs
(200kHz)
(15kHz)
Maximum Sync. pulse width: 7µs
Note: Minimum HPeriod: 500ns + S/W interrupt servicing time
(1 Timer Clock)
VR01961
Figure 39. Vertical Sync Input Timing
or:
5ms < Typical Ver. Total time < 25ms
(200Hz)
(40Hz)
Typical Sync. pulse width: 0.0384ms - 0.600ms
Note: Minimum VPeriod: 500ns + S/W interrupt servicing time
(1 Timer Clock)
58/144
VR01961A
ST72774/ST727754/ST72734
SYNC PROCESSOR (SYNC) (Cont’d)
ClampOut and Moire Signal
Clamp Output signal
The clamping pulse generator can control the
pulse width and polarity signal and can be
configured as pseudo-front porch or back porch.
To use the ClampOut signal:
– Select the Clamping Pulse width:
BP0/BP1 bits in MCR register
– Program the Clamp polarity:
CLPINV bit in POLR register
– Select the ClampOut signal as back-porch (after
falling edge of HSYNCO) or pseudo-front porch
(after the rising edge of HSYNCO):
HS0/HS1 bits in MCR register.
– Enable the CLAMPOUT signal:
CLMPEN bit in ENR register
Moire Signal
The Moire output signal is available (instead of the
clamping signal) to reduce the screen Moire effect
and improve color transitions.
The CLAMPOUT pin is alternatively used to output
a Moire signal.
The output signal toggles at each HFBACK rising
edge. After each VFBACK falling edge, the value
of the Moire output is the opposite of the previous
one, independent of the number of HFBACK
pulses during the VFBACK low level.
To use the Moire signal:
– Select the Moire signal:
Reset the BP0/BP1 bits in MCR register
– Enable the output signal:
CLMPEN bit in ENR register
Figure 40. Clamping Pulse (CLAMPOUT) Delay
HSYNCO
Maximum delay:
(Fixed delay of 10 to 30ns) + (fOSC/2) = approx. 110ns.
CLAMPOUT
Programmable clamping width: 0, 167ns, 333ns, 666ns
59/144
ST72774/ST727754/ST72734
Figure 41. Moire Output (instead of Clamping Output)
VFBACK
HFBACK
Moire
4.4.5.1 Blanking output signal
The Video Blanking function uses VSYNCO,
HFBACK, VFBACK as input signals and
BLANKOUT output as Video Blanking Output. This
output pin is a 5V open-drain output and can be
AND-wired with any external video blanking signal.
To use the video blanking signal:
– Program the polarity:
BLKINV bit in POLR register
– Enable the BLANKOUT output:
BLKEN bit in ENR register
Note: HFBACK, VFBACK, VSYNCO signals must have
positive polarity.
Figure 42. Video Blanking Stage Simplified Schematic
HFBACK
To Edge detector (LATR)
To Edge detector (LATR)
BLKINV
VFBACK
R
S
VSYNCO
60/144
BLKEN
BLANKOUT
ST72774/ST727754/ST72734
SYNC PROCESSOR (SYNC) (Cont’d)
4.4.6 Input Processing
4.4.6.1 Detecting Signal Presence
The Sync Processor provides two ways of
checking input signal presence, by directly polling
the LATR Latch Register or using the Timer
interrupts.
Polling check
Use the Latch Register (LATR), to detect the
presence of HSYNCI, VSYNCI, CSYNCI,
HFBACK and VFBACK signals. These latched bits
are set when the falling edge of the corresponding
signal is detected. They are cleared by software.
Interrupts check
Due to the fact that VSYNCI is connected to Timer
Input Capture 1 and HSYNCI or CSYNCI is
connected to Timer Input Capture 2, the Timer
interrupts can be used to detect the presence of
input signals. Refer to the 16-bit Timer chapter for
the description of the Timer registers.
To use the interrupt method:
– Select Input Capture1 edge detection:
IEDG1 bit in the Timer CR1 register
– Select Input Capture 2 edge detection (must be
falling edge):
IEDG2 bit = 0 in the Timer CR2 register
– Enable Timer Input Capture interrupts:
ICIE bit in the Timer CR1 register.
– Select the Hsync and Vsync input signals:
HVSEL bit in the POLR register
– Enable the prescaler for HSYNCI or CSYNCI
signal:
PSCD bit in the CCR register.
– Select the normal mode:
LCV1/LCV0 bits in the CCR register.
Perform any of the following:
– Check for VSYNCI presence by monitoring interrupt requests from Timer ICAP1. When VSYNCI
is detected then either detect the VSYNCI polarity or check for HSYNCI presence.
– Check for HSYNCI presence by monitoring interrupt requests from Timer ICAP2. On detecting
HSYNCI, either detect its polarity or check if thecomposite sync on HSYNCI pin is detected or
check for CSYNCI presence.
– Check for CSYNCI presence by monitoring interrupt requests from Timer ICAP2.
4.4.6.2 Measuring Sync Period
To measure the sync period, the Sync processor
block uses the Timer Input Capture interrupts:
– ICAP1 connected to VSYNCI signal
– ICAP2 connected to HSYNCI/CSYNCI signal
with a 256 prescaler
Calculating
the
difference
between
two
subsequent Input Captures (16-bit value) gives the
period for 256xPH (horizontal period) and PV
(vertical period).
The period accuracy is one timer clock (500ns at 2
MHz), so that the tolerance is 500ns for PH and
256 * PH (PH accuracy =1.95ns).
Notes:
1) In case of composite sync, the HSYNCI period
measurement can be synchronized on the
VSYNCI pulse by setting and resetting the
prescaler PSCD bit in the CCR register (for this
function, the ICAP2 detection must be selected
as falling edge).
This avoids errors in the period measurement
due to the Vsync pulse.
2) The Timer Interrupt request should be masked
during a write access to any of the Sync
processor control registers.
Important Note:
Since the recognition of the video mode relies
on the accuracy of the measurements, it is
highly recommended to implement a counterstyle algorithm which performs several
consecutive measurements before switching
between modes.
The purpose of this algorithm is to filter out any
glitches occurring on the video signals.
61/144
ST72774/ST727754/ST72734
SYNC PROCESSOR (SYNC) (Cont’d)
4.4.6.3 Detecting Signal Polarity
The Sync Processor provides two ways for
checking input signal polarity by polling the latches
or using the 5-bit up/down counter.
Polling check
– HSYNCI polarity detection:
UPLAT/DWNLAT bits in LATR register
These bits are directly connected to the 5-bit
Up/Down counter.
UPLAT=1/ DOWNLAT=0 HSYNCI polarity<0
UPLAT=0/ DOWNLAT=1 HSYNCI polarity>0
– VSYNCI Polarity Detection
– VPOL bit (VSYNCO polarity) in POLR and
– VOP bit (VSYNCO polarity control) in MCR
The delay between VSYNCI polarity changes
and the VPOL bit typically toggles within 4
msecs. The polarity detector includes an
integrator to filter possible incoming VSYNCI
glitches.
5-bit Up/Down Counter Check
for HSYNCI Polarity
This method involves the internal 5-bit up/down
counter.
The counter value (CV4-CV0 bits) is updated with
the 5-bit counter value at every detected edge on
the signal monitored.
It is incremented when the signal is high, otherwise
it is decremented.
– Start the detection phase:
Initialize the 5-bit counter: write '00000' in the
CCR register (CV4-CV0 bits).
Select normal mode on falling edge:
LCV1/LCV0 = 0 in the CCR register.
– Software checks the counter value (CV4-CV0)
after an interrupt (with the signal internally connected or ICAP2) or by polling (timeout 150µs).
Positive polarity: The counter value < 1Fh.
Negative polarity: The counter value =1Fh on
the falling edge.
In case of a composite incoming signal, the
software just has to check that the VSYNCO
period and polarity are stable.
62/144
4.4.6.4 Extracting VSYNCO from CSYNCI
In case of composite sync, the Vertical sync output
signal is extracted with the 5-bit up/down counter.
Initially, the width of an Horizontal Sync
component pulse is automatically determined by
hardware which defines a threshold for the 5-bit
counter with a possible user-defined tolerance.
The circuit then monitors for any incoming period
greater than this previously captured value. This is
then processed as the VSYNCO signal.
To use the Vsync extractor, the following steps are
necessary:
– Detection of a composite sync signal:
When the UPLAT and DOWNLAT bits in LATR
register are set, a composite sync signal or a
HSYNCI polarity change is detected.
If these bits are stable during two subsequent
ICAP2 interrupt, the composite sync signal is
stable.
– Defining a threshold:
Select the normal mode (LCV1/LCV0=0 in the
CCR register).
Initialize the counter capture CV4-CV0 to 0.
This automatically measures the HSYNCI pulse
width. It defines a threshold in the CV4-CV0 bits
used by the 5-bit up/down counter.
It also allows to check the HSYNCI polarity
(refer to the “5-bit Up/Down Counter Check”
paragraph.
If a user-defined tolerance is to be added, then
an updated value should be written in the CCR
register (CV4-CV0 bits).
In a composite sync signal, Hsync and Vsync
always have the same polarity.
– Starting the VSYNCO hardware extraction
mode:
According to the Composite sync polarity, select
the extraction mode (LCV1/LCV0 in CCR
register) and rewrite the counter if necessary.
Negative polarity: minimum threshold (00h)
Positive polarity: maximum threshold (1Fh)
Note:
The extracted VSYNCO signal always has
negative polarity.
ST72774/ST727754/ST72734
SYNC PROCESSOR (SYNC) (Cont’d)
4.4.6.5 Example of VSYNCO extraction for a
negative composite sync with serration pulses
Refer to Figure 43.
In extraction mode, the 5-bit comparator checks
the counter value with respect to the threshold.
When the incoming signal is high, the counter is
increased, otherwise it is decreased.
When the counter reaches the threshold on its way
down, VSYNCO is asserted. During the vertical
blanking, the counter value is decreased down to a
programmable minimum, i.e. it does not underflow.
When the vertical period is finished, the counter
starts counting up and when the maximum is
reached, VSYNCO is negated. The extracted
signal may be validated by software since it is input
to Timer ICAP1.
Serration pulses during vertical blanking can be
filtered if the serration pulse widths are less than
8µs.
In the same way, positive composite sync signals
can be used by properly selecting the edge
sensitivity in HSYNCI width measurement mode
(LCV0 bit).
Figure 43. VSYNCO Extraction from a Composite Signal (negative polarity)
Serration pulses
Composite signal
Input
Max Pulse width: 8µs
1F-Threshold
Counter value:
1F=Max
8µs
Threshold
0=Min
VSYNCO
generated
VSYNCO Pulse
Max Delay: 8µs
or threshold
HSYNCO
VR01990
Figure 44. Obtaining the 11-bit Vertical Period (V11BITS)
7
7
0
0
CFGR
VGENR
10
V11BITS
Q’2 Q’1 Q’0
0
Example:
VGENR=CCh, CFGR = 3h
V11bits=663h
63/144
ST72774/ST727754/ST72734
SYNC PROCESSOR (SYNC) (Cont’d)
4.4.7 Output Processing
4.4.7.1 Generating Free-Running Frequencies
The free-running frequencies function is used to:
– Drive the monitor when no or bad sync signals
are received.
– Stabilize the OSD screen when the monitor is
unlocked.
– Perform fast alignment for maintenance purposes.
Note: When free-running mode is active, the analyzer
and corrector modes must be disabled.
– VCORDIS = 1, VEXT = 0 in CFGR and POLR
registers for vertical output measurement
– 2FHINH = 0 in CFGR register for horizontal
low level measurment
– Configure the following bits:
SYNOP = 0
HVGEN = 1
HACQ = 0
VACQ = 0
Horizontal Period
PH = Horizontal period = ((HGENR+1)/4) µs
Pulse width: 2 µs => HGENR min=8
Polarity: Positive
HGENR range: [8..255]
Vertical Period
PV = Vertical period = (PH * V11bits) µs
V11bits is a concatenation of VGENR and the Q'2
Q'1 Q'0 bits of the CFGR register.
Refer to Figure 44.
– VACQ, HACQ = 0, in CFGR register for analyzer mode
The Sync processor can generate any of the
following output sync signals HSYNCO, VSYNCO,
CLAMPOUT, BLANKOUT.
Pulse width: 4 * PH => min value= 8µs
Polarity: Positive
VGENR/CFGR range: [5..7FF]
To select the generation mode:
– Program the horizontal period using the HGENR
register.
– Program the vertical period using the VGENR (8
bits) and CFGR (3 bits) registers (2047 scan
lines per frame). Refer to Figure 44.
Table 17. Typical values for generated HSYNC signals
HGENR (hex value)
H Period
HFREQ
Pulse Width
Duty Cycle
13
5 µs
200 kHz
2 µs
40%
1F
8 µs
125 kHz
2 µs
25%
3F
16 µs
62.5 kHz
2 µs
12.5%
7F
32 µs
31.25 kHz
2 µs
6.2%
FF
64 µs
15.6 kHz
2 µs
3.1%
Table 18. Typical values for generated VSYNC signals
HGENR
(hex value)
13
13
1F
1F
3F
3F
7F
7F
64/144
H Period
H Freq
5 µs
5 µs
8 µs
8 µs
16 µs
16 µs
32 µs
32 µs
200 kHz
200 kHz
125 kHz
125 kHz
62.5 kHz
62.5 kHz
31.25 kHz
31.25 kHz
V11bits
(hex value)
7FF (2047)
400 (1024)
7FF (2047)
400 (1024)
7FF (2047)
400 (1024)
7FF (2047)
400 (1024)
V Period
V Freq
Pulse width
10.2 ms
5.1 ms
16.3 ms
8.2 ms
32.6 ms
16.4 ms
65.5 ms
32.8 ms
97.7 Hz
195 Hz
61 Hz
122 Hz
30.6 Hz
60.9 Hz
15 Hz
30 Hz
20 µs
20 µs
32 µs
32 µs
64 µs
64 µs
128 µs
128 µs
ST72774/ST727754/ST72734
SYNC PROCESSOR (SYNC) (Cont’d)
4.4.8 Analyzer Mode
The analyzer block is used for all extra
measurements on the sync signals to manage the
monitor functions:
– Measure the number of scan lines per frame
(VSYNCO or VFBACK) to simplify the OSD vertical centering.
– Measure the low level of HSYNCO or HFBACK.
This function can be used for VSYNCO pulse
extension or for a fast estimation of the incoming
Hsync signal period.
For maximum accuracy, it is possible to measure
the low level of HFBACK with the same technique
(FBSEL bit in the MCR register).
Figure 45. Horizontal Low Level Measurement
Measure HLow
Disable H correction Mode
2FHINH=0
– Detection of the pre/post equalization pulses.
Notes:
Disable H internal generation
HVGEN=0
1. Analyzer mode should be performed before
corrector mode.
2. When analyzer mode is active, the free-running
frequencies generator and corrector mode must
be disabled.
– HVGEN = 0 in ENR register
HSYNCO Positive polarity
Select H/VBACK or H/VSYNCO
FBSEL=0 or 1
– 2FHINH 0 in CFGR register for Horizontal low
level measurement
– VEXT = 0, VCORDIS = 1 in CFGR, POLR registers for Vertical output measurement
3. If H/VBACK are selected (FBSEL=0) corrector
mode must be disabled
4. For all measurements, HSYNCO and VSYNCO
must be POSITIVE.
Necessary if Signals
are H/VSYNCO
HACQ=1
Start measurement
No
HACQ=0?
Yes
HGENR=Result
4.4.8.1 Horizontal Low Level Measurement
The measurement starts in setting HACQ by
software. When this bit is cleared by hardware, the
HGENR register returns the result.
END
VR02118A
The algorithm is shown in Figure 45.
HLow = ((255-HGENR+1)/4) µs
Note: HLow maximum value = 64µs (even if real value is
greater)
65/144
ST72774/ST727754/ST72734
SYNC PROCESSOR (SYNC) (Cont’d)
4.4.8.2 Vertical Output Measurement
The function of vertical pulse measurement is to:
Figure 46. Vertical Output Measurement
Measure H Lines
– Capture the number of HSYNCO pulses during
a Low level of VSYNCO.
– Capture the number of HFBACK pulses during a
Low level of VFBACK (maximum accuracy).
Start the measurement by setting VACQ in the
CFGR. When the measurement is completed this
bit is cleared by hardware. The VGENR and CFGR
registers return the result.
Disable V correction Mode
VCORDIS=1, VEXT=0
Disable H internal generation
HVGEN=0
The algorithm is shown in Figure 46.
H & VSYNCO Positive polarity
HLine = 2048 - (V11bits)
Hline maximum value = 2048 (even if real value is
greater)
Necessary if Signals
are H/VSYNCO
Select H/VBACK or H/VSYNCO
FBSEL=0 or 1
V11bits = VGENR(8 MSB) and Q'2,Q'1,Q'0 (3
LSB). Refer to Figure 44.
VACQ=1
Start measurement
Note: In case of pre/post equalization pulses, set the
2FHINH bit in the CFGR register.
No
4.4.8.3 Detection of pre equalization pulses
This function uses two bits:
– 2FHDET in POLR register continuously updated
by hardware
– 2FHLAT in LATR register set by hardware when
a higher frequency is detected and reset by software
A measurement of the low level of HSYNCO is
necessary before reading this information.
Note: Reset the 2FHLAT bit in the LATR register on the
third Hsync pulse after the Vsync pulse.
66/144
VACQ=0?
Yes
VGENR & CFGR=Result
END
VR02118B
ST72774/ST727754/ST72734
SYNC PROCESSOR (SYNC) (Cont’d)
4.4.9 Corrector Mode
In this mode, you can perform the following
functions:
Procedure:
– Inhibit pre/post equalization pulses
This removes all pre/post equalization pulses
on the HSYNCO signal.
2. Set the 2FHINH bit in the CFGR register to
remove pre/post equalization pulses.
The inhibition starts on the falling edge of
HSYNCO and lasts for (((HGENR+1)/4)-2)
µs. The decrease of 2µs (one minimum pulse
width) avoids the removal of the next pulse of
HSYNCO.
1. HSYNCO and VSYNCO polarities must be
positive.
3. Measure the low level of HSYNCO.
4. Update HGENR =(FFh - (HGENR + 1)) + 4
to add tolerance
5. Write VGENR > 0.
Procedure:
6. Reset the VCORDIS bit in the POLR
register
1. HSYNCO and VSYNCO polarities must be
positive.
7. Set the VEXT bit in the CFGR register.
2. Measure the low level of HSYNCO.
3. Set the 2FHINH bit in the CFGR register.
– Extend VSYNCO pulse width by several scan
lines
This function can be also used to extend the
video blanking signal.
– Extend VSYNCO pulse width during pre and
post equalization pulses (for test only).
This function allows extending the VSYNCO
pulse width as long as equalization pulses are
detected. (VSYNCO = VSYNCO + 2FHDET).
Procedure:
Procedure:
1. HSYNCO and VSYNCO polarities must be
positive.
1. HSYNCO and VSYNCO polarities must be
positive.
2. Set the 2FHINH bit in the CFGR register to
remove pre/post equalization pulses.
2. Set the 2FHINH bit in the CFGR register
only if some pre/post equalizations pulses
are detected. (2FHLAT, 2FHDET flags).
3. Measure the low level of HSYNCO.
3. The extension will be the number of
HSYNCO periods set in the VGENR
register.
4. Reset the VCORDIS bit in the POLR
register.
– Extend VSYNCO width during all post equalization pulses.
This function extends the VSYNCO pulse
width when post equalization pulses are
detected (2FHDET bit in the POLR register
and 2FHLAT bit in the LATR register).
4. Update HGENR =(FFh - (HGENR + 1)) + 4.
5. Write VGENR > 0.
6. Reset the VCORDIS bit in the POLR register.
7. Set the VEXT bit in the CFGR register.
8. Set the 2FHEN bit in the ENR register.
Notes:
1. When corrector mode is active, the free-running
frequencies generator and analyzer mode must
be disabled.
(HVGEN=0 in ENR register, HACQ=0, VACQ=0
in the CFGR register).
2. If VGENR=0, all VSYNCO correction functions
are disabled except the 2FHEN bit which must
be cleared if VGENR = 0 or VCORDIS = 1.
67/144
ST72774/ST727754/ST72734
SYNC PROCESSOR (SYNC) (Cont’d)
4.4.10 Register Description
CONFIGURATION REGISTER (CFGR)
1: Start measuring the number of scan lines during VSYNCO/VFBACK low level.
Read/Write
Bit 5 = Reserved. Must be cleared.
Reset Value: 0000 0000 (00h)
7
HACQ VACQ
0
-
2FHINH VEXT
Q’2
Q’1
Q’0
Bit 7 = HACQ Horizontal Sync Analyzer Mode
Set by software, reset by hardware when the
measurement is done. The sync generator must
be disabled (HVGEN=0).
0 : Measurement is done, the result can be read
in HGENR.
1: Start measuring HSYNCO/HFBACK low level.
Bit 6 = VACQ Vertical Sync Analyzer Mode
Set by software, reset by hardware when the
measurement is done. The sync generator must
be disabled (HVGEN=0).
0: Measurement is done, and the result can be
read in VGENR.
68/144
Bit 4 = 2FHINH Inhibition of Pre/Post equalization
pulses.
This function removes pre/post equalization
pulses on HSYNCO signal. The sync generator
and the Horizontal sync analyzer must both be
disabled (HVGEN=HACQ=0).
0: Disable
1: Enable
Bit 3 = VEXT VSYNCO pulse width extension in
case of post-equalization pulses.
The sync generator and the Horizontal and
Vertical sync analyzer must be disabled (HVGEN
= 0, HACQ = 0, VACQ = 0, VCORDIS=0). Vertical
extension must be enabled (VGENR > 0).
0: Disable
1: Enable
Bits 2:0 = Q’2..Q’0
These are the read/write LSB of the VGENR 11-bit
counter. Refer to Figure 44.
ST72774/ST727754/ST72734
SYNC PROCESSOR (SYNC) (Cont’d)
MUX CONTROL REGISTER (MCR)
Read/Write
HS1
HS0
HSYNCI Selection Mode
0
0
CLAMPOUT after HSYNCO rising edge
HSYNC0 <- (HSYNCI, CSYNCI)
0
1
CLAMPOUT after HSYNCO rising edge
HSYNC0 <- (HSYNCI, CSYNCI)
1
0
CLAMPOUT after HSYNCO falling edge
HSYNC0 <- (HSYNCI, CSYNCI)
1
1
CLAMPOUT after HSYNCO falling edge
HSYNC0 <- (HSYNCI,CSYNCI)
Reset Value: 0010 0000 (20h)
7
BP1
0
BP0
FBSEL SCI0 HS1
HS0
VOP
-
Bit 7:6 = BP1, BP0 Back Porch Pulse control
BP1
BP0
Back Porch pulse width
0
0
No Back Porch, Moire output selected
0
1
167ns Back Porch ± 10 ns
1
0
333ns Back Porch ± 10 ns
1
1
666ns Back Porch ± 10 ns
Bit 5 = FBSEL VSYNCO/HSYNCO or VFBACK/
HFBACK analysis
0: HFBACK & VFBACK
1: HSYNCO & VSYNCO
Bit 4 = SCI0 HSYNCI/CSYNCI selection
0: HSYNCI
1: CSYNCI
Bit 3:2 = HS1, HS0 Horizontal Signal selection
These bits allow inversion of the HSYNCI/CSYNCI
Note: In case of composite sync, if HSYNCO blanking is
enabled (HINH=0 in the ENR register), HS1 must =
1 (CLAMPOUT after HSYNCO rising edge not allowed).
Bit 1 = VOP Vertical Polarity control
The VOP bit inverts the VSYNCO Sync signal.
0: No polarity inversion (VSYNC0 <- VSYNCI)
1: Inversion enabled (VSYNC0 <- VSYNCI)
Note: If at each vertical input capture the VPOL bit is copied by software on the VOP bit, the VSYNCO signal
will have a constant positive polarity.
Note: The internally extracted VSYNCO has ALWAYS
negative polarity.
Bit 0 = Reserved. Must always be cleared.
69/144
ST72774/ST727754/ST72734
SYNC PROCESSOR (SYNC) (Cont’d)
COUNTER CONTROL REGISTER (CCR)
Table 19. Sync On Green Window
Read/Write
WINDOW DELAY
min.
max.
dt
165 ns
250 ns
Reset Value: 0000 0000 (00h)
7
0
Bit 6 = Reserved, forced by hardware to 0.
Bit 5 = VPOL Vertical Sync polarity (read only)
PSCD
LCV1
LCV0 CV4 CV3 CV2 CV1
CV0
0: Positive polarity
1: Negative polarity
Bit 7 = PSCD Prescaler Enable bit.
0: Enable the Prescaler by 256
1: Disable the Prescaler and reset it to 7Fh. This
also disables the ICAP2 event.
Bit 6:5 = LCV1, LCV0 VSYNCO Extraction Control
LCV1
LCV0
VSYNC0 Control Bits
0
0
Normal mode
Counter capture on input falling edge
0
1
Normal mode
Counter capture on input rising edge
1
0
Extraction mode
CSYNCI/HSYNCI Negative polarity
CV4-0 = counter minimum threshold
1
1
Extraction mode
CSYNCI/HSYNCI Positive polarity
CV4-0 = counter maximum threshold
Bit 4:0 = CV4-CV0 Counter Captured Value.
These bits contain the counter captured value in
different modes.
In VSYNCO extraction mode, they contain the
HSYNCI pulse-width measurement.
POLARITY REGISTER (POLR)
Note: If the Vertical Sync polarity is changing, the VPOL
bit will be updated after a typical delay of 4 msec.
Bit 4 = 2FHDET Detection of Pre/Post Equalization
pulses (read only).
This bit is continuously updated by hardware. It is
valid when the sync generator and horizontal
analyzer are disabled (HVGEN = 0, HACQ = 0).
0: None detected
1: Pre/Post Equalization pulses detected
Bit 3 = HVSEL Alternate Sync Input Select.
This bit selects between the two sets of Horizontal
and Vertical Sync inputs
0: HSYNCI2 / VSYNCI2
1: HSYNCI1 / VSYNCI1
Bit 2 = VCORDIS Extension Disable Signal
(Extension with VGENR Register)
0: enable
1: disable
Bit 1 = CLPINV Programmable ClampOut pulse
polarity.
0: Positive
1: Negative
Bits 5-4 Read Only, other bits Read/Write
Reset Value: 0000 1000 (08h)
Bit 0 = BLKINV Programmable blanking polarity
7
SOG
0
0
VPOL 2FHDET HVSEL VCORDIS CLPINV BLKINV
Bit 7 = SOG Sync On Green Detector
SOG is set by hardware if CSYNCI pulse is not
included in the window between HSYNCI rising
edge and HSYNCI falling edge + dt .
Cleared by software.
70/144
0: Negative
1: Positive
ST72774/ST727754/ST72734
SYNC PROCESSOR (SYNC) (Cont’d)
LATCH REGISTER (LATR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
CSYN HSYN VSYN HFLY VFLY UPLAT DWNLAT 2FHLAT
Bit 7 = CSYN Detection of pulses on CSYNCI
Set on falling edge of CSYNCI
Cleared by software (by writing zero).
Bit 6 = HSYN Detection of pulses on HSYNCI
Set on falling edge of HSYNCI1 or HSYNCI2
Cleared by software (by writing zero).
Bit 5 = VSYN Detection of pulses on VSYNCI
Set on falling edge of VSYNCI1 or VSYNCI2
Cleared by software (by writing zero).
Bit 4 = HFLY Detection of pulses on HFBACK
Set on falling edge of HFBACK input
Cleared by software (by writing zero).
Bit 1 = DWNLAT Detection of minimum value of 5bit up/down counter.
Set when the 5 bit up/down counter reaches its
minimum value (00 or Threshold)
Cleared by software (by writing zero).
Note: DWNLAT and UPLAT may be used for HSYNCI polarity detection and Composite Sync detection as
follows:
UPLAT
DWNLAT
HSYNCI Characteristics
0
0
No Info
0
1
Positive Polarity
1
0
Negative Polarity
1
1
Composite Sync
Bit 0 = 2FHLAT equalization pulses latch.
This bit may be used to detect pre/
postequalization pulses or a too high horizontal
frequency.
Set by hardware when Pre/Post equalization
pulses are detected.
Must be reset by software.
It is valid when the sync generator and Horizontal
analyzer are disabled (HVGEN = 0, HACQ = 0)
Bit 3 = VFLY Detection of pulses on VFBACK
Set on falling edge of VFBACK input
Cleared by software (by writing zero).
Bit 2 = UPLAT Detection of the maximum value of
5-bit up/down counter.
Set when the 5 bit up/down counter reaches its
maximum value (1Fh or Threshold)
Cleared by software (by writing zero).
71/144
ST72774/ST727754/ST72734
SYNC PROCESSOR (SYNC) (Cont’d)
HORIZONTAL SYNC GENERATOR REGISTER
(HGENR)
VERTICAL SYNC GENERATOR REGISTER
(VGENR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
MSB
LSB
MSB
LSB
Case HVGEN = 1: Generation mode
In this mode, this register contains the Hsync freerunning frequency.
The generated signal is:
- Pulse width: 2 µs.
- Period PH = ((HGENR+1)/4) µs.
- Polarity: Positive
Note: The value in HGENR must be in the range [8..255].
Case HVGEN = 0: Analyzer/corrector Mode
Sub-case HACQ = 1: Analyzer Mode
By setting HACQ bit by software the Analyzer
mode starts. When HACQ is cleared by hardware,
HGENR returns the duration of HSYNCO/
HFBACK low level. The analysis should be done
before corrector mode.
Sub-case HACQ = 0: Corrector Mode
In this mode, the final HSYNCO signal on the pin
can be corrected in order to detect and inhibit pre/
post equalization pulses.
72/144
Case HVGEN = 1: Generation mode
In this mode, this register contains the Vsync freerunning frequency (11-bit value).
The generated signal is:
- Pulse width: 4 * PH µs (horizontal period).
- Period PV = PH * (V11bits) µs.
- Polarity: Positive
Note: The value in VGENR must be in the range [5..255]
The Vsync generation mode works as an 11-bit horizontal line counter (2047 scan lines per frame
max.). The 3 LSB are in the CFGR register. Refer
to Figure 44.
Case HVGEN = 0: Analyzer/Corrector Mode
Sub-case VACQ = 1: Analyzer Mode
Set the VACQ bit to start analyzer mode. When
VACQ is cleared by hardware, VGENR/CFGR
returns the number of scan lines during the
VSYNCO/VFBACK low level period.
Sub-case VACQ = 0: Corrector Mode
VSYNCO pulse width is extended by VGENR scan
lines. If VGENR = 0, all VSYNCO corrections are
disabled.
ST72774/ST727754/ST72734
SYNC PROCESSOR (SYNC) (Cont’d)
ENABLE REGISTER (ENR)
Read/Write
Reset Value: 1100 0011 (C3h)
7
0
SYNOP CLMPEN BLKEN HVGEN 2FHEN HINH HSIN1 VSIN1
Bit 7 = SYNOP HSYNCO, VSYNCO outputs
enable
0: Enabled
1: Disabled
Bit 6 = CLMPEN Clamping or Moire output enable
0: Clamping or Moire output (function of BP0,
BP1) enabled
1: Clamping or Moire output disabled
Bit 3 = 2FHEN VSYNCO Extension
VSYNCO is forced high when detecting pre- and
post-equalization pulses. It is valid when the sync
generator and analyzer are disabled (HVGEN = 0,
HACQ = 0, VACQ = 0). Refer to the procedure in
Section 4.4.9 Corrector Mode.
0: Disabled
1: Enabled
Bit 2 = HINH HSYNCO Blanking
HSYNCO is blanked during
VSYNCO pulse.
0: Enabled
1: Disabled
the
extracted
Bit 1 = HSIN1 (read only)
Returns the HSYNCI1 pin level
Bit 0 = VSIN1 (read only)
Returns the VSYNCI1 pin level
Bit 5 = BLKEN Blanking Output
0: Disabled
1: Enabled
Bit 4 = HVGEN Sync Generation function
0: Analyzer/Corrector Mode
1: Generation of HSYNCO and VSYNCO freerunning frequencies
Table 20. Summary of the Main Sync Processor Modes
Sync Processor Mode
SYNOP
HVSEL
HVGEN
HACQ
VACQ
DSUB Selected as Inputs
(HSYNCI1/VSYNCI1)
---
1
---
---
---
BNC Selected as Inputs
(HSYNCI2/VSYNCI2)
---
0
---
---
---
Don’t drive the monitor
with any Sync signals
1
---
---
---
---
Generate Sync Signals
to drive the Monitor hardware
0
---
1
0
0
Use the Sync Processor
to drive the monitor hardware
by incoming Sync signals
0
---
0
---
---
Analyse the number of Scan Lines
during one vertical frame
---
--
0
---
1
Analyse the HSYNC delay
between two pulses
---
---
0
1
---
73/144
ST72774/ST727754/ST72734
SYNC PROCESSOR (SYNC) (Cont’d)
Table 21. SYNC Register Map and Reset Values
Address
(Hex.)
40
41
42
43
44
45
46
47
74/144
Register
Name
CFGR
Reset Value
MCR
Reset Value
CCR
Reset Value
POLR
Reset Value
LATR
Reset Value
HGENR
Reset Value
VGENR
Reset Value
ENR
Reset Value
7
6
5
4
3
2
1
0
HACQ
VACQ
-
2FHINH
VEXT
Q’2
Q’1
Q’0
0
0
0
0
0
0
0
0
BP1
BP0
FBSEL
SCI0
HS1
HS0
VOP
-
0
0
1
0
0
0
0
0
PSCD
LCV1
LCV0
CV4
CV3
CV2
CV1
CV0
0
0
0
0
0
0
0
0
SOG
0
VPOL
2FHDET
HVSEL
VCORDIS
CLPINV
BLKINV
0
0
0
0
1
0
0
0
CSYN
HSYN
VSYN
HFLY
VFLY
UPLAT
DWNLAT
2FHLAT
0
0
0
0
0
0
0
0
MSB
0
LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SYNOP
CLMPEN
BLKEN
HVGEN
2FHEN
HINH
HSIN1
VSIN1
1
1
0
0
0
0
1
1
MSB
0
LSB
ST72774/ST727754/ST72734
4.5 TIMING MEASUREMENT UNIT (TMU)
4.5.1 Introduction
The timing measurement unit (TMU) allows the
analysis of the current video timing characteristics
in order to control display position and size.
It consists of measuring the timing between the
horizontal or vertical sync output signals and the
active video signal input (AV).
4.5.2 Main Features
■ Horizontal or vertical timing measurement
■ Oscillator clock fOSC (24 or 12 MHz) used for
horizontal measurement
■ Horizontal sync signal (HSYNCO or HFBACK)
and Vertical sync signal (VSYNCO or VFBACK)
used for all measurements
■ Measurements performed on positive signals
only
■ 11-bit counter
■ Overflow detection
4.5.3 Functional Description
The Timing Measurement Unit is centered around
an 11-bit counter. Depending on the H_V bit of the
control register, the TMU measures the horizontal
or vertical video characteristics.
For horizontal analysis (refer to Figure 48):
– Obtain the minimum number of oscillator clock
cycles (H1) between the falling edge of the
horizontal sync signal (HSYNCO or HFBACK)
and the first rising edge of the active video input (AV), for all lines, between 2 consecutive
vertical sync pulses.
– Obtain the minimum number of oscillator clock
cycles (H2) between the last falling edge of
the active video input (AV) and the rising edge
of the horizontal sync signal (HSYNCO or HFBACK) for all lines, between 2 consecutive
vertical sync pulses.
Note: Horizontal measurement is inhibited during the high
level of VSYNCO or VFLYBACK.
For vertical analysis (refer to Figure 49):
– Obtain the minimum number of horizontal
sync pulses (V1) between the falling edge of
the vertical sync signal (VSYNCO or VFBACK) and the first rising edge of the active
video input, during 2 consecutive frames.
Figure 47. TMU Block Diagram
ST7 INTERNAL BUS
TMUT1CR
T1[7:0]
8
TMUT2CR
T2[7:0]
TMUCSR
T2[10] T2[9] T2[8] T1[10] T1[9] T1[8] H_V START
3
3
8
COMPARATOR
SUP
11
11 bit COUNTER
Clock
Start
Stop
CONTROL
fOSC
(FROM SYNC PROCESSOR)
HSYNCO or HFBACK (1)
VSYNCO or VFBACK (1)
Note 1: Selection between Sync outputs or Flyback inputs is made in MISCR register (bit 6: FLY_SYN)
AV
75/144
ST72774/ST727754/ST72734
TIMING MEASUREMENT UNIT (Cont’d)
– Obtain the minimum number of horizontal
sync output pulses (V2) between the last falling edge of the active video input (AV) and the
rising edge of the vertical sync signal (VSYNCO or VFBACK) during two 2 consecutive
frames.
The H_V bit selects horizontal or vertical
measurement. This selection should be made prior
to starting the measurement by setting the START
bit. This bit is set by software but only cleared by
hardware at the end of the measurement.
When the measurement is finished (rising edge of
AV, horizontal or vertical sync signals), the results
(T1,T2) are transferred into the corresponding
registers (H1,H2) or (V1,V2).
Note: The values of the H1/H2 or V1/V2 registers are
available only at the end of a measurement (after
the START bit has been cleared).
4.5.3.1 Horizontal Measurement
When the H_V bit = 1, and when the START bit is
set by software, the measurement starts after the
next vertical sync pulse. The TMU searches the
minimum values of H1 and H2 until the rising edge
of the next following vertical sync pulse. The
START bit is then cleared by hardware.
The values of the H1 and H2 registers are
available only at the end of a measurement, in
other words when the START bit is at 0.
4.5.3.2 Vertical Measurement
When the H_V bit = 0 and, when the START bit is
set by software, the TMU measures the minimum
V1 and V2 values during 2 consecutive vertical
frames. The START bit is then cleared by
hardware.
4.5.3.3 Special cases
– If an overflow of the counter occurs during any of
the measurements, the measured T1 or T2 values will be 7FFh.
– If the AV signal is always low (no active video),
the measured T1 or T2 values will also be 7FFh.
– If T1 ≤ 0 (AV already high when the falling edge
of the sync signal occurs), the measured T1 value will be fixed to 1.
– If T2 ≤ 0 (AV still high when the rising edge of the
sync signal occurs), a specific T2 value will be returned.
Note: Refer to Application Note AN1183 for further details.
Figure 48. Horizontal Measurement
HSYNCO or
HFBACK
H1
H2
AV
H1 and H2 measured in oscillator clock periods
Note: HSYNCO or HFBACK must be positive.
Figure 49. Vertical Measurement
VSYNCO or
VFBACK
V1
AV
V1 and V2 measured in horizontal pulses
Note: VSYNCO or VFBACK must be positive.
76/144
V2
ST72774/ST727754/ST72734
TIMING MEASUREMENT UNIT (Cont’d)
4.5.4 Register Description
T1 COUNTER REGISTER (TMUT1CR)
Read Only
Reset Value: 1111 1111 (FFh)
CONTROL STATUS REGISTER (TMUCSR)
Bit 7:2 - Read only
Bit 1:0 - Read/Write
Reset Value: 1111 1100 (FCh)
7
T2[10] T2[9] T2[8] T1[10] T1[9] T1[8]
This is an 8-bit register that contains the low part of
the counter value.
7
0
T1[7]
T1[0]
0
H_V START
Bit 7:5 = T2[10:8] MSB of T2 Counter.
Most Significant Bits of the T2 counter value (see
T2 Counter register description).
When a T1 measurement is finished (rising edge
on AV input), the 11-bit counter value is transferred
to this register and to the T1[10:8] bits in the CSR
register.
T1 is H1 value if the H_V bit = 1.
Bit 4:2= T1[10:8] MSB T1 Counter.
Most Significant Bits of the T1 counter value (see
T1 Counter register description).
Bit 1 = H_V Horizontal or Vertical Measurement.
This bit is set and cleared by software to select the
type of measurement. It cannot be modified while
the START bit = 1 (measurement in progress).
0: Vertical measurement.
1: Horizontal measurement.
Bit 0 = START Start measurement.
This bit is set by software and cleared by hardware
when the measurements are completed. It can not
be cleared by software.
0: Measurement done.
1: Start measurement.
T1 is V1 value if the H_V bit = 0.
T2 COUNTER REGISTER (TMUT2CR)
Read Only
Reset Value: 1111 1111(FFh)
This is an 8-bit register that contains the low part of
the counter value.
7
0
T2[7]
T2[0]
When a T2 measurement is finished (rising edge
on the selected sync signal), the 11-bit counter
value is transferred to this register and to the
T2[10:8] bits in the CSR register.
T2 is H2 value if the H_V bit = 1.
T2 is V2 value if the H_V bit = 0.
77/144
ST72774/ST727754/ST72734
TIMING MEASUREMENT UNIT (Cont’d)
Table 22. TMU Register Map and Reset Values
Address
(Hex.)
0E
0F
10
78/144
Register
Name
CSR
Reset Value
T1CR
Reset Value
T2CR
Reset Value
7
6
5
4
3
2
1
0
T2[10]
T2[9]
T2[8]
T1[10]
T1[9]
T1[8]
H_V
START
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
T1[7]
1
T1[0]
T2[7]
1
1
T2[0]
1
ST72774/ST727754/ST72734
4.6 USB INTERFACE (USB)
4.6.1 Introduction
The USB Interface implements a low-speed
function interface between the USB and the ST7
microcontroller. It is a highly integrated circuit
which includes the transceiver, 3.3 voltage
regulator, SIE and DMA. No external components
are needed apart from the external pull-up on
USBDM for low speed recognition by the USB
host.
Serial Interface Engine
4.6.2 Main Features
■ USB Specification Version 1.0 Compliant
■ Supports Low-Speed USB Protocol
■ Two or Three Endpoints (including default one)
depending on the device (see device feature list
and register map)
■ CRC
generation/checking, NRZI encoding/
decoding and bit-stuffing
■ USB Suspend/Resume operations
■ DMA Data transfers
■ On-Chip 3.3V Regulator
■ On-Chip USB Transceiver
4.6.3 Functional Description
The block diagram in Figure 50, gives an overview
of the USB interface hardware.
Endpoints
The Endpoint registers indicate if the
microcontroller is ready to transmit/receive, and
how many bytes need to be transmitted.
For general information on the USB, refer to the
“Universal Serial Bus Specifications” document
available at http//:www.usb.org.
The SIE (Serial Interface Engine) interfaces with
the USB, via the transceiver.
The SIE processes tokens, handles data
transmission/reception, and handshaking as
required by the USB standard. It also performs
frame formatting, including CRC generation and
checking.
DMA
When a token for a valid Endpoint is recognized by
the USB interface, the related data transfer takes
place, using DMA. At the end of the transaction, an
interrupt is generated.
Interrupts
By reading the Interrupt Status register,
application software can know which USB event
has occurred.
Figure 50. USB block diagram
6 MHz
ENDPOINT
REGISTERS
USBDM
Transceiver
SIE
DMA
USBDP
CPU
Address,
data busses
and interrupts
USBVCC
3.3V
Voltage
Regulator
INTERRUPT
REGISTERS
MEMORY
USBGND
79/144
ST72774/ST727754/ST72734
USB INTERFACE (Cont’d)
4.6.4 Register Description
Bits 7:6 = DA[7:6] DMA address bits 7-6.
The software must write the start address of the
DMA memory area whose most significant bits are
given by DA15-DA6. The remaining 6 address bits
are set by hardware. See Figure 51.
DMA ADDRESS REGISTER (DMAR)
Read / Write
Reset Value: Undefined
7
DA15
Bits 5:4 = EP[1:0] Endpoint number (read-only).
These bits identify the endpoint which required
attention.
0
DA14
DA13
DA12
DA11
DA10
DA9
DA8
Bits 7:0=DA[15:8] DMA address bits 15-8.
See the description of bits DA7-6 in the next
register (IDR).
00: Endpoint 0
01: Endpoint 1
10: Endpoint 2
When a CTR interrupt occurs (see register ISTR)
the software should read the EP bits to identify the
endpoint which has sent or received a packet.
INTERRUPT/DMA REGISTER (IDR)
Bits 3:0 = CNT[3:0] Byte count (read only).
This field shows how many data bytes have been
received during the last data reception.
Read / Write
Reset Value: xxxx 0000 (x0h)
7
DA7
0
DA6
EP1
EP0
CNT3
CNT2
CNT1
Note: Not valid for data transmission.
CNT0
Figure 51. DMA buffers
101111
Endpoint 2 TX
101000
100111
Endpoint 2 RX
100000
011111
011000
010111
010000
001111
Endpoint 1 TX
Endpoint 1 RX
Endpoint 0 TX
001000
000111
Endpoint 0 RX
DA15-6,000000
80/144
000000
ST72774/ST727754/ST72734
USB INTERFACE (Cont’d)
PID REGISTER (PIDR)
Read only
Reset Value: xx00 0000 (x0h)
7
0
TP3
TP2
0
0
0
0
0
0
Bits 7:6 =TP3-TP2 Token PID bits 3 & 2.
USB token PIDs are encoded in four bits. TP3-TP2
correspond to the variable token PID bits 3 & 2.
Note: PID bits 1 & 0 have a fixed value of 01.
When a CTR interrupt occurs (see register ISTR)
the software should read the TP3 and TP2 bits to
retrieve the PID name of the token received.
TP2
PID Name
0
0
OUT
1
0
IN
1
1
SETUP
Bit 3 = IOVR Interrupt overrun.
This bit is set when hardware tries to set ERR,
ESUSP or SOF before they have been cleared by
software.
INTERRUPT STATUS REGISTER (ISTR)
Read / Write
Reset Value: 0000 0000 (00h)
0
0: No overrun detected
1: Overrun detected
0
DOVR
CTR
ERR
IOVR
ESUSP
RESET
Note:A transfer where the device sent a NAK or STALL
handshake is considered not correct (the host only
sends ACK handshakes). A transfer is considered
correct if there are no errors in the PID and CRC
fields, if the DATA0/DATA1 PID is sent as expected, if there were no data overruns, bit stuffing or
framing errors.
0: No error detected
1: Timeout, CRC, bit stuffing or nonstandard
framing error detected
Bit 5:0 Reserved. Forced by hardware to 0.
7
0: No Correct Transfer detected
1: Correct Transfer detected
Bit 4 = ERR Error.
This bit is set by hardware whenever one of the
errors listed below has occurred:
The USB standard defines TP bits as:
TP3
Bit 5 = CTR Correct Transfer. This bit is set by
hardware when a correct transfer operation is
performed. The type of transfer can be determined
by looking at bits TP3-TP2 in register PIDR. The
Endpoint on which the transfer was made is
identified by bits EP1-EP0 in register IDR.
SOF
When an interrupt occurs these bits are set by
hardware. Software must read them to determine
the interrupt type and clear them after servicing.
Bit 2 = ESUSP End suspend mode .
This bit is set by hardware when, during suspend
mode, activity is detected that wakes the USB
interface up from suspend mode.
This interrupt is serviced by a specific vector.
0: No End Suspend detected
1: End Suspend detected
Note: These bits cannot be set by software.
Bit 7 = Reserved. Forced by hardware to 0.
Bit 6 = DOVR DMA over/underrun.
This bit is set by hardware if the ST7 processor
can’t answer a DMA request in time.
0: No over/underrun detected
1: Over/underrun detected
Bit 1 = RESET USB reset.
This bit is set by hardware when the USB reset
sequence is detected on the bus.
0: No USB reset signal detected
1: USB reset signal detected
Note: The DADDR, EP0RA, EP0RB, EP1RA, EP1RB,
EP2RA and EP2RB registers are reset by a USB
reset.
81/144
ST72774/ST727754/ST72734
USB INTERFACE (Cont’d)
Bit 0 = SOF Start of frame.
This bit is set by hardware when a low-speed SOF
indication (keep-alive strobe) is seen on the USB
bus.
0: No SOF signal detected
1: SOF signal detected
Note: To avoid spurious clearing of some bits, it is recommended to clear them using a load instruction
where all bits which must not be altered are set, and
all bits to be cleared are reset. Avoid read-modifywrite instructions like AND , XOR..
Read / Write
7
0
CTR
M
ERR
M
IOVR
M
0: Voltage regulator on
1: Voltage regulator off
Note: After turning on the voltage regulator, software
should allow at least 3 µs for stabilisation of the
power supply before using the USB interface.
0: Suspend mode inactive
1: Suspend mode active
Reset Value: 0000 0000 (00h)
DOV
RM
Bit 2 = PDWN Power down.
This bit is set by software to turn off the 3.3V onchip voltage regulator that supplies the external
pull-up resistor and the transceiver.
Bit 1 = SUSP Suspend mode.
This bit is set by software to enter Suspend mode.
INTERRUPT MASK REGISTER (IMR)
0
Software should clear this bit after the appropriate
delay.
ESU
SPM
RES
ETM
SOF
M
When the hardware detects USB activity, it resets
this bit (it can also be reset by software).
Bit 0 = FRES Force reset.
This bit is set by software to force a reset of the
USB interface, just as if a RESET sequence came
from the USB.
Bit 7 = Reserved. Forced by hardware to 0.
Bits 6:0 = These bits are mask bits for all interrupt
condition bits included in the ISTR. Whenever one
of the IMR bits is set, if the corresponding ISTR bit
is set, and the I bit in the CC register is cleared, an
interrupt request is generated. For an explanation
of each bit, please refer to the corresponding bit
description in ISTR.
CONTROL REGISTER (CTLR)
0: Reset not forced
1: USB interface reset forced.
The USB is held in RESET state until software
clears this bit, at which point a “USB-RESET”
interrupt will be generated if enabled.
DEVICE ADDRESS REGISTER (DADDR)
Read / Write
Read / Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0110 (06h)
7
7
0
0
0
0
0
0
0
RESUME
PDWN
SUSP
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
FRES
Bit 7 = Reserved. Forced by hardware to 0.
Bits 7:4 = Reserved. Forced by hardware to 0.
Bits 6:0 = ADD[6:0] Device address, 7 bits.
Bit 3 = RESUME Resume.
This bit is set by software to wake-up the Host
when the ST7 is in suspend mode.
0: Resume signal not forced
1: Resume signal forced on the USB bus.
82/144
Software must write into this register the address
sent by the host during enumeration.
Note: This register is also reset when a USB reset is received from the USB bus or forced through bit
FRES in the CTLR register.
ST72774/ST727754/ST72734
USB INTERFACE (Cont’d)
ENDPOINT n REGISTER A (EPnRA)
Bits 5:4 = STAT_TX[1:0] Status bits, for
transmission transfers.
These bits contain the information about the
endpoint status, which are listed below:
Read / Write
Reset Value: 0000 xxxx (0xh)
7
ST_
OUT
0
DTOG
_TX
STAT
_TX1
STAT
_TX0
TBC
3
TBC
2
TBC
1
TBC
0
These registers (EP0RA, EP1RA and EP2RA) are
used for controlling data transmission. They are
also reset by the USB bus reset.
Note: Endpoint 2 and the EP2RA register are not available on some devices (see device feature list and
register map).
Bit 7 = ST_OUT Status out.
This bit is set by software to indicate that a status
out packet is expected: in this case, all nonzero
OUT data transfers on the endpoint are STALLed
instead of being ACKed. When ST_OUT is reset,
OUT transactions can have any number of bytes,
as needed.
Bit 6 = DTOG_TX Data Toggle, for transmission
transfers.
It contains the required value of the toggle bit
(0=DATA0, 1=DATA1) for the next transmitted
data packet. This bit is set by hardware at the
reception of a SETUP PID. DTOG_TX toggles only
when the transmitter has received the ACK signal
from the USB host. DTOG_TX and also
DTOG_RX (see EPnRB) are normally updated by
hardware, at the receipt of a relevant PID. They
can be also written by software.
STAT_TX1 STAT_TX0 Meaning
0
DISABLED: transmission
transfers cannot be executed.
1
STALL: the endpoint is
stalled and all transmission
requests result in a STALL
handshake.
1
0
NAK: the endpoint is naked
and all transmission requests result in a NAK handshake.
1
1
VALID: this endpoint is enabled for transmission.
0
0
These bits are written by software. Hardware sets
the STAT_TX bits to NAK when a correct transfer
has occurred (CTR=1) related to a IN or SETUP
transaction addressed to this endpoint; this allows
the software to prepare the next set of data to be
transmitted.
Bits 3:0 = TBC[3:0] Transmit byte count for
Endpoint n.
Before transmission, after filling the transmit
buffer, software must write in the TBC field the
transmit packet size expressed in bytes (in the
range 0-8).
83/144
ST72774/ST727754/ST72734
USB INTERFACE (Cont’d)
ENDPOINT n REGISTER B (EPnRB)
Read / Write
STAT_RX1 STAT_RX0 Meaning
Reset Value: 0000 xxxx (0xh)
0
DISABLED: reception
transfers
cannot
be
executed.
1
STALL: the endpoint is
stalled and all reception
requests result in a STALL
handshake.
1
0
NAK: the endpoint is naked and all reception requests result in a NAK
handshake.
1
1
VALID: this endpoint is
enabled for reception.
0
7
CTRL
0
DTOG
_RX
STAT
_RX1
STAT
_RX0
EA3
EA2
EA1
EA0
0
These registers (EP1RB and EP2RB) are used for
controlling data reception on Endpoints 1 and 2.
They are also reset by the USB bus reset.
Note: Endpoint 2 and the EP2RB register are not available on some devices (see device feature list and
register map).
Bit 7 = CTRL Control.
This bit should be 0.
Note: If this bit is 1, the Endpoint is a control endpoint.
(Endpoint 0 is always a control Endpoint, but it is
possible to have more than one control Endpoint).
Bit 6 = DTOG_RX Data toggle, for reception
transfers.
It contains the expected value of the toggle bit
(0=DATA0, 1=DATA1) for the next data packet.
This bit is cleared by hardware in the first stage
(Setup Stage) of a control transfer (SETUP
transactions start always with DATA0 PID). The
receiver toggles DTOG_RX only if it receives a
correct data packet and the packet’s data PID
matches the receiver sequence bit.
Bit 5:4 = STAT_RX [1:0] Status bits, for reception
transfers.
These bits contain the information about the
endpoint status, which are listed in the following
table:
These bits are written by software. Hardware sets
the STAT_RX bits to NAK when a correct transfer
has occurred (CTR=1) related to an OUT or
SETUP transaction addressed to this endpoint, so
the software has the time to elaborate the received
data before acknowledging a new transaction.
Bits 3:0 = EA[3:0] Endpoint address.
Software must write in this field the 4-bit address
used to identify the transactions directed to this
endpoint. Usually EP1RB contains “0001” and
EP2RB contains “0010”.
ENDPOINT 0 REGISTER B (EP0RB)
Read / Write
Reset Value: 1000 0000 (80h)
7
1
0
DTOG
RX
STAT
RX1
STAT
RX0
0
0
0
0
This register is used for controlling data reception
on Endpoint 0. It is also reset by the USB bus
reset.
Bit 7 = Forced by hardware to 1.
Bit 6:4 = Refer to the EPnRB register for a
description of these bits.
Bit 3:0 = Forced by hardware to 0.
84/144
ST72774/ST727754/ST72734
USB INTERFACE (Cont’d)
4.6.5 Programming Considerations
In the following, the interaction between the USB
interface and the application program is described.
Apart from system reset, action is always initiated
by the USB interface, driven by one of the USB
events associated with the Interrupt Status
Register (ISTR) bits.
4.6.5.1 Initializing the Registers
At system reset, the software must initialize all
registers to enable the USB interface to properly
generate interrupts and DMA requests.
1. Initialize the DMAR, IDR, and IMR registers
(choice of enabled interrupts, address of DMA
buffers). Refer the paragraph titled initializing
the DMA Buffers.
2. Initialize the EP0RA and EP0RB registers to
enable accesses to address 0 and endpoint 0
to support USB enumeration. Refer to the paragraph titled Endpoint Initialization.
3. When addresses are received through this
channel, update the content of the DADDR.
4. If needed, write the endpoint numbers in the EA
fields in the EP1RB and EP2RB register.
4.6.5.2 Initializing DMA buffers
The DMA buffers are a contiguous zone of
memory whose maximum size is 48 bytes. They
can be placed anywhere in the memory space,
typically in RAM, to enable the reception of
messages. The 10 most significant bits of the start
of this memory area are specified by bits DA15DA6 in registers DMAR and IDR, the remaining
bits are 0. The memory map is shown in Figure 51.
3. Enable the endpoint by setting the STAT_TX
bits to VALID (11b) in EPnRA.
Note: Once transmission and/or reception are enabled,
registers EPnRA and/or EPnRB (respectively) must
not be modified by software, as the hardware can
change their value on the fly.
When the operation is completed, they can be
accessed again to enable a new operation.
4.6.5.4 Interrupt Handling
Start of Frame (SOF)
The interrupt service routine must monitor the SOF
events and measure the interval between each
SOF event. If 3ms pass without a SOF event, the
software should set the USB interface to suspend
mode.
USB Reset (RESET)
When this event occurs, the DADDR register is
reset, and communication is disabled in all
endpoint registers (the USB interface will not
respond to any packet). Software is responsible for
reenabling endpoint 0 within 10 ms of the end of
reset. To do this you set the STAT_RX bits in the
EP0RB register to VALID.
End Suspend (ESUSP)
The CPU is alerted by activity on the USB, which
causes an ESUSP interrupt.
Correct Transfer (CTR)
1. When this event occurs, the hardware automatically sets the STAT_TX or STAT_RX to NAK.
Each buffer is filled starting from the bottom (last 3
address bits=000) up.
Note: Every valid endpoint is NAKed until software clears
the CTR bit in the ISTR register, independently of
the endpoint number addressed by the transfer
which generated the CTR interrupt.
4.6.5.3 Endpoint Initialization
To be ready to receive:
Note: If the event triggering the CTR interrupt is a SETUP
transaction, both STAT_TX and STAT_RX are set
to NAK.
Set STAT_RX to VALID (11b) in EP0RB to enable
reception.
2. Read the PIDR to obtain the token and the IDR
to get the endpoint number related to the last
transfer.
To be ready to transmit:
1. Write the data in the DMA transmit buffer.
2. In register EPnRA, specify the number of bytes
to be transmitted in the TBC field
Note: When a CTR interrupt occurs, the TP3-TP2 bits in
the PIDR register and EP1-EP0 bits in the IDR register stay unchanged until the CTR bit in the ISTR
register is cleared.
3. Clear the CTR bit in the ISTR register.
85/144
ST72774/ST727754/ST72734
USB INTERFACE (Cont’d)
Table 23. USB Register Map and Reset Values
Address
(Hex.)
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
86/144
Register
Name
PIDR
Reset Value
DMAR
Reset Value
IDR
Reset Value
ISTR
Reset Value
IMR
7
6
5
4
3
2
1
0
TP3
TP2
0
0
RX_SEZ
RXD
0
0
x
x
0
0
0
0
0
0
DA15
DA14
DA13
DA12
DA11
DA10
DA9
DA8
x
x
x
x
x
x
x
x
DA7
DA6
EP1
EP0
CNT3
CNT2
CNT1
CNT0
x
x
x
x
0
0
0
0
SUSP
DOVR
CTR
ERR
IOVR
ESUSP
RESET
SOF
0
0
0
0
0
0
0
0
SUSPM
DOVRM
CTRM
ERRM
IOVRM
Reset Value
0
0
0
0
0
0
0
0
CTLR
0
0
0
0
RESUME
PDWN
FSUSP
FRES
Reset Value
0
0
0
0
0
1
1
0
DADDR
0
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
Reset Value
0
0
0
0
0
0
0
0
TBC3
TBC2
TBC1
TBC0
x
x
x
x
0
0
0
0
0
0
0
0
TBC3
TBC2
TBC1
TBC0
x
x
x
x
EA3
EA2
EA1
EA0
x
x
x
x
TBC3
TBC2
TBC1
TBC0
x
x
x
x
EA3
EA2
EA1
EA0
x
x
x
x
EP0RA
ST_OUT
Reset Value
0
EP0RB
1
Reset Value
1
EP1RA
Reset Value
EP1RB
Reset Value
EP2RA
Reset Value
EP2RB
Reset Value
ST_OUT
0
CTRL
0
ST_OUT
0
CTRL
0
DTOG_TX STAT_TX1 STAT_TX0
0
0
0
DTOG_RX STAT_RX1 STAT_RX0
0
0
0
DTOG_TX STAT_TX1 STAT_TX0
0
0
0
DTOG_RX STAT_RX1 STAT_RX0
0
0
0
DTOG_TX STAT_TX1 STAT_TX0
0
0
0
DTOG_RX STAT_RX1 STAT_RX0
0
0
0
ESUSPM RESETM
SOFM
ST72774/ST727754/ST72734
4.7 I²C SINGLE MASTER BUS INTERFACE (I2C)
4.7.1 Introduction
The I2C Bus Interface serves as an interface
between the microcontroller and the serial I2C bus.
It provides single master functions, and controls all
I2C bus-specific sequencing, protocol and timing.
It supports fast I²C mode (400kHz).
Mode Selection
4.7.2 Main Features
– Parallel bus /I2C protocol converter
The interface automatically switches from idle to
master after it generates a START condition and
from master to idle after it generates a STOP
condition.
– Interrupt generation
– Standard I2C mode /Fast I2C mode
– Master transmitter/receiver
By default, it is idle.
Communication Flow
– 7-bit Addressing
■
The interface can operate in the two following
modes:
The interface initiates a data transfer and
generates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated by software.
I2C single Master Mode
– End of byte transmission flag
– Transmitter/Receiver flag
– Clock generation
4.7.3 General Description
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
handshake. The interrupts are enabled or disabled
by software. The interface is connected to the I2C
bus by a data pin (SDAI) and by a clock pin (SCLI).
It can be connected both with a standard I2C bus
and a Fast I2C bus. This selection is made by
software.
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte following the start
condition is the address byte.
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to
Figure 52.
Figure 52. I2C BUS Protocol
SDA
ACK
MSB
SCL
1
START
CONDITION
2
8
9
STOP
CONDITION
VR02119B
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I²C SINGLE MASTER BUS INTERFACE (Cont’d)
Acknowledge may be enabled and disabled by
software.
The speed of the I2C interface may be selected
between Standard (0-100KHz) and Fast I 2C (100400KHz).
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the
microcontroller to write the byte in the Data
Register.
The SCL frequency (Fscl) is controlled by a
programmable clock divider which depends on the
I2C bus mode.
When the I2C cell is enabled, the SDA and SCL
ports must be configured as floating open-drain
output or floating input. In this case, the value of
the external pull-up resistance used depends on
the application.
When the I2C cell is disabled, the SDA and SCL
ports revert to being standard I/O port pins.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
Figure 53. I2C Interface Block Diagram
DATA REGISTER (DR)
SDAI
DATA CONTROL
SDA
DATA SHIFT REGISTER
SCLI
SCL
CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR)
STATUS REGISTER 1 (SR1)
CONTROL LOGIC
STATUS REGISTER 2 (SR2)
INTERRUPT
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I²C SINGLE MASTER BUS INTERFACE (Cont’d)
4.7.4 Functional Description (Master Mode)
Refer to the CR, SR1 and SR2 registers in Section
4.7.5. for the bit definitions.
By default the I2C interface operates in idle mode
(M/IDL bit is cleared) except when it initiates a
transmit or receive sequence.
To switch from default idle mode to Master mode a
Start condition generation is needed.
Start condition and Transmit Slave address
Setting the START bit causes the interface to
switch to Master mode (M/IDL bit set) and
generates a Start condition.
Once the Start condition is sent:
– The EVF and SB bits are set by hardware with
an interrupt if the ITE bit is set.
Then the master waits for a read of the SR1
register followed by a write in the DR register with
the Slave address byte, holding the SCL line low
(see Figure 54 Transfer sequencing EV1).
Then the slave address byte is sent to the SDA line
via the internal shift register.
After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Then the master waits for a read of the SR1
register followed by a write in the CR register (for
example set PE bit), holding the SCL line low
(see Figure 54 Transfer sequencing EV2).
Next the master
Transmitter mode.
must
enter
Receiver
– Acknowledge pulse if if the ACK bit is set
– EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1
register followed by a read of the DR register,
holding the SCL line low (see Figure 54 Transfer
sequencing EV3).
To close the communication: before reading the
last byte from the DR register, set the STOP bit to
generate the Stop condition. The interface goes
automatically back to idle mode (M/IDL bit
cleared).
Note: In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be
cleared just before reading the second last data
byte.
Master Transmitter
Following the address transmission and after SR1
register has been read, the master sends bytes
from the DR register to the SDA line via the internal
shift register.
The master waits for a read of the SR1 register
followed by a write in the DR register, holding the
SCL line low (see Figure 54 Transfer sequencing
EV4).
When the acknowledge bit is received, the
interface sets:
– EVF and BTF bits with an interrupt if the ITE bit
is set.
To close the communication: after writing the last
byte to the DR register, set the STOP bit to
generate the Stop condition. The interface goes
automatically back to idle mode (M/IDL bit
cleared).
or
Error Case
Master Receiver
Following the address transmission and after SR1
and CR registers have been accessed, the master
receives bytes from the SDA line into the DR
register via the internal shift register. After each
byte the interface generates in sequence:
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the START or STOP bit.
Note: The SCL line is not held low.
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I²C SINGLE MASTER BUS INTERFACE (Cont’d)
Figure 54. Transfer Sequencing
Master receiver:
S
Address
A
EV1
Data1
A
EV2
Data2
A
EV3
EV3
.....
DataN
NA
P
EV3
Master transmitter:
S
Address
EV1
A
Data1
EV2 EV4
A
Data2
EV4
A
EV4
.....
DataN
A
P
EV4
Legend:
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV2: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV4: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
Figure 55. Event Flags and Interrupt Generation
ITE
BTF
SB
AF
*
* EVF *can also be set by EV2 or an error from the SR2 register.
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INTERRUPT
EVF
ST72774/ST727754/ST72734
I²C SINGLE MASTER BUS INTERFACE (Cont’d)
4.7.5 Register Description
I2C CONTROL REGISTER (CR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
0
PE
0
START
ACK
STOP
ITE
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = PE Peripheral enable.
This bit is set and cleared by software.
0: Peripheral disabled
1: Master capability
Note: When PE=0, all the bits of the CR register and the
SR register except the Stop bit are reset. All outputs
are released while PE=0
Note: When PE=1, the corresponding I/O pins are selected by hardware as alternate functions.
Note: To enable the I2C interface, write the CR register
TWICE with PE=1 as the first write only activates
the interface (only PE is set).
Bit 4 = Reserved. Forced to 0 by hardware.
Bit 3 = START Generation of a Start condition .
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disabled
(PE=0) or when the Start condition is sent (with
interrupt generation if ITE=1).
Bit 2 = ACK Acknowledge enable.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disabled
(PE=0).
0: No acknowledge returned
1: Acknowledge returned after a data byte is received
Bit 1 = STOP Generation of a Stop condition.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disabled
(PE=0) or when the Stop condition is sent.
In Master mode only:
0: No stop generation
1: Stop generation after the current byte transfer
or after the current Start condition is sent.
Bit 0 = ITE Interrupt enable.
This bit is set and cleared by software and cleared
by hardware when the interface is disabled
(PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to Figure 55 for the relationship between the
events and the interrupt.
SCL is held low when the SB or BTF flags or an
EV2 event (See Figure 54) is detected.
In master mode:
0: No start generation
1: Repeated start generation
In idle mode:
0: No start generation
1: Start generation when the bus is free
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I²C SINGLE MASTER BUS INTERFACE (Cont’d)
I2C STATUS REGISTER 1 (SR1)
Read Only
Reset Value: 0000 0000 (00h)
7
EVF
0
0
TRA
0
BTF
0
M/IDL
SB
Bit 7 = EVF Event flag.
This bit is set by hardware as soon as an event
occurs. It is cleared by software reading SR2
register in case of error event or as described in
Figure 54. It is also cleared by hardware when the
interface is disabled (PE=0).
0: No event
1: One of the following events has occurred:
– BTF=1 (Byte received or transmitted)
– SB=1 (Start condition generated)
– AF=1 (No acknowledge received after byte
transmission if ACK=1)
– Address byte successfully transmitted.
Bit 6 = Reserved. Forced to 0 by hardware.
Bit 5 = TRA Transmitter/Receiver.
When BTF is set, TRA=1 if a data byte has been
transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware when the
interface is disabled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
Bit 4 = Reserved. Forced to 0 by hardware.
Bit 3 = BTF Byte transfer finished.
This bit is set by hardware as soon as a byte is
correctly received or transmitted with interrupt
generation if ITE=1. It is cleared by software
reading SR1 register followed by a read or write of
DR register. It is also cleared by hardware when
the interface is disabled (PE=0).
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– Following a byte transmission, this bit is set after
reception of the acknowledge clock pulse. In
case an address byte is sent, this bit is set only
after the EV2 event (See Figure 54). BTF is
cleared by reading SR1 register followed by writing the next byte in DR register.
– Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared by reading SR1 register
followed by reading the byte from DR register.
The SCL line is held low while BTF=1.
0: Byte transfer not done
1: Byte transfer succeeded
Bit 2 = Reserved. Forced to 0 by hardware.
Bit 1 = M/IDL Master/Idle.
This bit is set by hardware as soon as the interface
is in Master mode (writing START=1). It is cleared
by hardware after generating a Stop condition on
the bus. It is also cleared when the interface is
disabled (PE=0).
0: Idle mode
1: Master mode
Bit 0 = SB Start bit generated.
This bit is set by hardware as soon as the Start
condition is generated (following a write
START=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR1 register followed
by writing the address byte in DR register. It is also
cleared by hardware when the interface is disabled
(PE=0).
0: No Start condition
1: Start condition generated
ST72774/ST727754/ST72734
I²C SINGLE MASTER BUS INTERFACE (Cont’d)
I2C STATUS REGISTER 2 (SR2)
Read Only
Reset Value: 0000 0000 (00h)
7
0
0
0
0
AF
0
0
0
0
0: Standard I2C mode
1: Fast I2C mode
Bit 6:0 = CC6-CC0 7-bit clock divider.
These bits select the speed of the bus (FSCL)
depending on the I2C mode. They are not cleared
when the interface is disabled (PE=0).
– Standard mode (FM/SM=0): FSCL <= 100kHz
FSCL = FCPU/(2x([CC6..CC0]+2))
Bit 7:5 = Reserved. Forced to 0 by hardware.
– Fast mode (FM/SM=1): FSCL > 100kHz
FSCL = FCPU/(3x([CC6..CC0]+2))
Bit 4 = AF Acknowledge failure.
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while AF=1.
0: No acknowledge failure
Note: The programmed FSCL assumes no load on SCL
and SDA lines.
I2C DATA REGISTER (DR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
1: Acknowledge failure
D7
D6
D5
D4
D3
D2
D1
D0
Bit 3:0 = Reserved. Forced to 0 by hardware.
Bit 7:0 = D7-D0 8-bit Data Register.
These bits contains the byte to be received or
transmitted on the bus.
2
I C CLOCK CONTROL REGISTER (CCR)
Read / Write
Reset Value: 0000 0000 (00h)
7
FM/SM
0
CC6
CC5
CC4
CC3
CC2
CC1
CC0
Bit 7 = FM/SM Fast/Standard I2C mode.
This bit is set and cleared by software. It is not
cleared when the interface is disabled (PE=0).
– Transmitter mode: Byte transmission start automatically when the software writes in the DR register.
– Receiver mode: the first data byte is received automatically in the DR register using the least significant bit of the address.
Then, the next data bytes are received one by
one after reading the DR register.
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I2C SINGLE MASTER BUS INTERFACE (Cont’d)
Table 24. I2C Register Map
Address
(Hex.)
5F
5E
5D
5C
59
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Register
Name
7
6
CR
Reset Value
SR1
Reset Value
5
PE
0
0
EVF
0
CCR
Reset Value
DR
Reset Value
0
TRA
3
2
1
0
START
ACK
STOP
ITE
0
0
0
0
M/IDL
SB
0
0
0
0
0
0
0
0
0
CC5
CC4
CC3
CC2
CC1
CC0
0
0
0
0
0
0
0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FM/SM
CC6
0
SR2
Reset Value
4
BTF
0
AF
ST72774/ST727754/ST72734
4.8 DDC INTERFACE (DDC)
4.8.1 Introduction
The DDC (Display Data Channel) Bus Interface is
mainly used by the monitor to identify itself to the
video controller, by the monitor manufacturer to
perform factory alignment, and by the user to
adjust the monitor’s parameters.
■
■
■
■
I2C byte, random and sequential read modes
DMA transfer from any memory location and to
RAM
Automatic memory address incrementation
End of data downloading flag and interrupt
capability
The DDC interface consists of two parts:
■
■
A fully hardware-implemented interface,
supporting DDC1 and DDC2B (VESA
specification 3.0 compliant). It accesses the
ST7 on-chip memory directly through a built-in
DMA engine.
A second interface, supporting the slave I2C
functions for handling DDC/CI mode (DDC2Bi),
factory alignment or Enhanced DDC (EDDC) by
software.
4.8.2.2 DDC/CI - Factory Interface Features
General I2C Features:
– Parallel bus /I2C protocol converter
– Interrupt generation
– Standard I2C mode/Fast I2C mode
– 7-bit Addressing
I2C Slave Features:
– I2C bus busy flag
4.8.2 DDC Interface Features
4.8.2.1 Hardware DDC1/2B Interface Features
■ Full
hardware
support
for
DDC1/2B
communications (VESA specification versions 2
and 3)
■ Hardware detection of DDC2B addresses A0h/
A1h and optionally A2h/A3h (P&D) or A6h/A7h
(FPDI-2)
■ Separate mapping of EDID version 1 (128
bytes) and EDID version 2 (256 bytes) when
both must coexist
■ Support for error recovery mechanism
■ Detection
of misplaced Start and Stop
conditions
– Start bit detection flag
– Detection of misplaced Start or Stop condition
– Transfer problem detection
– Address Matched detection
– Programmable Address detection and/or
Hardware detection of Enhanced DDC (EDDC) addresses (60h/61h)
– End of byte transmission flag
– Transmitter/Receiver flag
– Stop condition Detection
Figure 56. DDC Interface Overview
SDA
SDAD
I2C SLAVE
INTERFACE
(DDC/CI - Factory Alignment)
SCL
SCLD
HARDWARE DDC1/2B
VSYNC
VSYNCI
VSYNC2
VSYNCI2
INTERFACE
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Figure 57. DDC Interface Block Diagram
DDC1/2B CONTROL REGISTER (DCR)
DMA
CONTROLLER
ADDRESS LOW REGISTER (ALR)
ADDRESS/DATA
CONTROL LOGIC
ADDRESS HIGH REGISTER (AHR)
SDAD
DATA CONTROL
DATA SHIFT REGISTER
DDC1/2B
CONTROL LOGIC
SCLD
VSYNCI
VSYNCI2
HWDDC
INTERRUPT
DDC1/2B (for MONITOR IDENTIFICATION)
Bit in
MISCR
Register
DATA REGISTER (DR)
DATA CONTROL
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER (OAR)
DDC/CI-Factory CONTROL REGISTER (CR)
CONTROL LOGIC
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
(DDC/CI (for MONITOR ADJUSTMENT and CONTROL)
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DDC
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DDC INTERFACE (Cont’d)
4.8.3 Signal Description
Serial Data (SDA)
The SDA bidirectional pin is used to transfer data
in and out of the device. It is an open-drain output
that may be or-wired with other open-drain or
open-collector pins. An external pull-up resistor
must be connected to the SDA line. Its value
depends on the load of the line and the transfer
rate.
Transmit-only Clock (Vsync/Vsync2)
The Vsync input pins are used to synchronize all
data in and out of the device when in Transmit-only
mode.
These pins are ONLY used by the DDC1/2B
interface (when in DDC1 mode).
Serial Clock (SCL)
The SCL input pin is used to synchronize all data in
and out of the device when in I2C bidirectional
mode. An external pull-up resistor must be
connected to the SCL line. Its value depends on
the load of the line and the transfer rate.
Note:When the DDC1/2B and DDC/CI-Factory Interfaces
are disabled (HWPE bit=0 in the DCR register and
PE bit=0 in the CR register), SDA and SCL pins revert to standard I/O pins.
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4.8.4 I2C BUS Protocol
A standard I2C communication is normally based
on four parts: START condition, device slave
address transmission, data transfer and STOP
condition. They are described brielfly in the
following section and illustrated in Figure 58 (for
more details, refer to the I2C bus specification).
4.8.4.1 START condition
When the bus is free (both SCL and SDA lines are
at a high level), a master can initiate a
communication by sending a START signal. This
signal is defined as a high-to-low transition of SDA
while SCL is stable high. The bus is considered to
be busy after a START condition.
This START condition must
command for data transfer.
precede
any
4.8.4.2 Slave Address Transmission
The first byte following a START condition is the
slave address transmitted by the master. This
address is 7-bit long followed by an 8th bit (Least
significant bit: LSB) which is the data direction bit
(R/W bit).
– A “0” indicates a transmission (WRITE) from the
master to the slave.
– A “1” indicates a request for data (READ) from
the slave to the master.
If a slave device is present on the bus at the given
address, an Acknowledge will be generated on the
9th clock pulse.
4.8.4.3 Data Transfer
Once the slave address is acknowledged, the data
transfer can proceed in the direction given by the
R/W bit sent in the address.
Data is transferred with the most significant bit
(MSB) first. Data bits can be changed only when
SCL is low and must be held stable when SCL is
high.
One complete data byte transfer requires 9 clock
pulses: 8 bits + 1 acknowledge bit.
4.8.4.4 Acknowledge Bit (ACK / NACK)
Every byte put on the SDA line is 8-bit long
followed by an acknowledge bit.
This bit is used to indicate a successful data
transfer. The bus transmitter, either master or
slave, releases the SDA line during the 9th clock
period (after sending all 8 bits of data), then:
– To generate an Acknowledge (ACK) of the current byte, the receiver pulls the SDA line low.
– To generate a No-Acknowledge (NACK) of the
current byte, the receiver releases the SDA line
(hence at a high level).
4.8.4.5 STOP Condition
A STOP condition is defined by a low-to-high
transition of SDA while SCL is stable high. It ends
the communication between the Interface and the
bus master.
Figure 58. I2C Signal Diagram
SDA
SCL
Start
A0h
Ack
Device Slave Address
DataN(F0h) Ack STOP
00h
Ack
Data1(B0h) Ack
Data Address
WRITE DATA TO I2C DEVICE (Slave Address A0h)
SDA
SCL
Start
A1h
Ack
Device Slave Address
Data1(00h) Ack
Data2(B0h) Ack
DataN(F0h) Nack STOP
READ DATA FROM I2C DEVICE (Slave Address A1h)
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DDC INTERFACE (Cont’d)
4.8.5 DDC Standard
The DDC standard is divided in several data
transfer protocols: DDC1, DDC2B, DDC/CI.
For DDC1/2B, refer to the “VESA DDC Standard
v3.0” specification. For DDC/CI refer to the “VESA
DDC Commands Interface v1.0”
– DDC1 is a uni-directional transmission of EDID
v1 (128 bytes) from display to host clocked by
VSYNCI.
– DDC2B is a uni-directional channel from display
to host. The host computer uses base-level I2C
commands to read the EDID data from the display which is always in slave mode.
Specific types of display contain EDID at fixed
I2C device addresses within the device (refer to
Table 25).
– DDC/CI is a bi-directional channel between the
host computer and the display. The DDC/CI offers a display control interface based on I 2C bus.
It includes the DDC2Bi and DDC2AB standards.
Note: The DDC2AB standard is no longer handled by the
interface.
4.8.5.1 DDC1/2B Interface
4.8.5.1.1 Functionnal description
Refer to the DCR, AHR registers in Section 4.8.6.
for the bit definitions.
The DDC1/2B Interface acts as an I/O interface
between a DDC bus and the microcontroller
memory. In addition to receiving and transmitting
serial data, this interface directly transfers parallel
data to and from memory using a DMA engine,
only halting CPU activity for two clock cycles
during each byte transfer.
The interface supports by hardware:
– Two DDC communication protocols called DDC1
and DDC2B.
– Write operations into RAM.
– Read operations from RAM.
In DDC1, the interface reads sequential EDID v1
data bytes from the microcontroller memory, and
transmits them on SDA synchronized with Vsync.
In DDC2B mode, it operates in I2C slave mode.
The DDC1/2B Interface supports several DDC
versions configured using the CF[2:0] bits in the
DCR register which can only be changed while the
interface is disabled (HWPE bit=0 in the DCR
register). They define which EDID structure
version is used and which Device Addresses are
recognized.
Depending on the DDC version, one or two device
address pairs will be recognized and the
corresponding EDID structure will be validated
(refer to Table 25):
– DDC v2 (CF2=0,CF1=0,CF0=0): DDC1 is enabled and device addresses A0h/A1h are recognized. EDID v1 is used.
– DDC v2 (CF2=1,CF1=0,CF0=0): DDC1 is disabled and device addresses A0h/A1h are recognized. EDID v1 is used.
– Plug and Display (CF2=0,CF1=0,CF0=1):
DDC1 is disabled and device addresses A2h/
A3h are recognized. EDID v2 is used.
– Plug and Display + DDC v2 (CF2=0,CF1=1,
CF0=0): DDC1 is enabled and device addresses
A0h/A1h and A2h/A3h are recognized. Both
EDID structures v1 and v2 are used.
– Plug and Display + DDC v2 (CF2=1,CF1=1,
CF0=0): DDC1 is disabled and device addresses
A0h/A1h and A2h/A3h are recognized. Both
EDID structures v1 and v2 are used.
– FPDI (CF2=0,CF1=1, CF0=1): DDC1 is disabled
and device addresses A6h/A7h are recognized.
EDID v2 is used.
Table 25. Valid Device Addresses and EDID structure
Device Address
EDID v1:
A0h / A1h = 1010 000x
EDID v2:
A2h / A3h = 1010 001x
EDID v2:
A6h / A7h = 1010 011x
reserved
CF2 bit
CF1 bit
CF0 bit
Transfer Type
x
x
0
128-byte EDID structure write/read
0
0
1
0
1
1
1
0
0
256-byte EDID structure write/read
1
1
1
256-byte EDID structure write/read
1
x
1
reserved
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DDC INTERFACE (Cont’d)
The Write and Read operations allow the EDID
data to be downloaded during factory alignment
(for example).
Writes to the memory by the DMA engine can be
inhibited by means of the WP bit in the DCR
register.
A write of the last data structure byte sets a flag
and may be programmed to generate an interrupt
request.
The Data address (sub-address) is either the
second byte of write transfers or is pointed to by
the internal address counter automatically
incremented after each byte transfer.
Physical address mapping of the data structure
within the memory space is performed with a
dedicated register accessible by software.
register while the HWPE bit=0 and then set the
HWPE bit to enable the DDC1/2B Interface.
A proper initialization sequence (see Figure 59)
must supply nine clock pulses on the VSYNCI pin
in order to internally synchronize the device.
During this initialization sequence, the SDA pin is
in high impedance. On the rising edge of the 10th
pulse applied on VSYNCI, the device outputs on
SDA the most significant (MSB) bit of the byte
located at data address 00h.
A byte is clocked out by means of 9 clock pulses
on Vsync, 8 clock pulses for the data byte itself and
an extra pulse for a Don’t Care bit.
As long as SCL is not held low, each byte of the
memory array is transmitted serially on SDA.
The internal address counter is incremented
automatically until the last byte is transmitted.
Then, it rolls over to relative location 00h.
The physical mapping of the data structure
depends on the configuration and on the content of
the AHR register which can be set by software
(see Figure 60).
4.8.5.1.2 Mode description
DDC1 Mode: This mode is only enabled when the
DDC v2 or P&D-DDC v2 standards are validated. It
transmits only the EDID v1 data (128 bytes).
To switch the DDC1/2B Interface to DDC1 mode,
software must first clear the CF0 bit in the DCR
Figure 59. DDC1 Waveforms
PE
SCL
XX
ALR
00h
Vsync
Bit 6
Bit 7
SDA
1
2
8
9
10
11
PE
SCL
7Fh
ALR
SDA
Vsync
100/144
Bit 7
Bit 6
00h
Bit 0
Bit 7
Bit 6
ST72774/ST727754/ST72734
DDC INTERFACE (Cont’d)
Figure 60. Mapping of DDC1 data structure
DDC v2 mode: CF[1:0] bits = 00b
256 bytes
FFFFh
128-byte Data
Structure
15
ALR
Addr Pointer
AHR
8 7 6
0
0
ALR
256 * AHR
0000h
Note: MSB of ALR is always ‘0’
DDC v2 + P&D mode: CF[1:0] bits = 10b
128-byte Data
Structure
Reserved
ALR
256 bytes
256 bytes
FFFFh
15
Addr Pointer
512 * AHR[7:1]
0000h
DDC2B Transition Mode: This mode avoids the
display switching to DDC2B mode if spurious
noise is detected on SCL while the host is in DDC1
mode.
When the DDC1/2B interface is in DDC1 mode
and detects a falling edge on SCL, it enters the
transition state (see Figure 61).
If a valid I2C sequence (START followed by a valid
Device Address for CF0 =0 (see Table 25)) is not
AHR[7:1]
9 87
1
0
ALR
Notes:
- LSB of AHR is ignored and taken as ‘1’
- MSB of ALR is always ‘0’
received within either 128 Vsync pulses or a period
of approximately 2 seconds, then the interface will
revert to DDC1 mode at the EDID start address.
If the interface decodes a valid DDC2B Device
Address, it will lock into DDC2B mode and
subsequently disregard VSYNCI.
When in transition mode, the Vsync pulse counter
or the 2-sec. timeout counter is reset by any
activity on the SCL line.
Figure 61. Transition Mode Waveforms
DDC1 mode
Transition mode
SCL
ALR
00h
01h
SDA
Vsync
101/144
ST72774/ST727754/ST72734
DDC INTERFACE (Cont’d)
DDC2B Mode: The DDC1/2B Interface enters
DDC2B mode either from the transition state or
from the initial state if software sets the HWPE bit
while P&D only or FPDI-2 mode is selected.
Once in DDC2B mode, the Interface always acts
as a slave following the protocol described in
Figure 62.
The DDC1/2B Interface continuously monitors the
SDA and SCL lines for a START condition and will
not respond (no acknowledge) until one is found.
A STOP condition at the end of a Read command
(after a NACK) forces the stand-by state. A STOP
condition at the end of a Write command triggers
the internal DMA write cycle.
The Interface samples the SDA line on the rising
edge of SCL and outputs data on the falling edge
of SCL. In any case SDA can only change when
SCL is low.
Figure 62. DDC2B protocol (example)
SDA
SCL
Ack
Start A0h
Device Slave
Address
Legend:
102/144
Ack
Ack
Ack
Data1
DataN
00h
Stop Start A1h
Data Address
Device Slave
128 / 256 bytes EDID
Address
Bold = data / control signal from host
Italics = data / control signal from display
Nack
Stop
ST72774/ST727754/ST72734
Figure 63. DDC1/2B Operation Flowchart
Wait for HWPE = 1
HWPE bit = 0
CF0 = 0
and
CF2 = 0 ?
N
Y
Relative Address (ALR) = 0
DDC1 mode
Vsync
Y
Send Next Bit
N
SCL
N
Y
SDA Hi-Z
Vsync Counter = 0
Start 2-sec Timer
SCL
Vsync Counter = 0
Re-Start 2-sec Timer
Y
Transition mode
N
Received valid
Device Address?
Y
N
Vsync
N
Relative Address (ALR) = 0
Y
Received valid
Device Address?
Y
N
Counter = 128
or Timer expired ?
Send Acknowledge
N
DDC2B mode
Vsync Counter += 1
Respond to Command
Y
103/144
ST72774/ST727754/ST72734
DDC INTERFACE (Cont’d)
EDID Data structure mapping: An internal
address pointer defines the memory location being
addressed. It is made of two 8-bit registers AHR
and ALR.
AHR is initialized by software. It defines the 256byte block within the 64K address space
containing the data structure.
ALR is loaded with the data address sent by the
master after a write Device Address. It defines the
byte within the data structure currently addressed.
ALR is reset upon entry into the DDC2B mode.
One exception to this arrangement is when the
CF[1:0] bits = 10b. In this case the two EDID
versions must coexist at non-overlapping
addresses. The LSB of AHR is therefore ignored
and automatically set to 1 to address the 128-byte
EDID and set to 0 to address its 256-byte
counterpart (see Figure 64).
Figure 64. Mapping of DDC2B data structure
DDC v2 / P&D / FPDI-2 modes: CF[1:0] bits != 10b
Extended EDID v1 (if present)
128-byte Data
Structure
ALR :
00h -> 7Fh
256 bytes
256 bytes
FFFFh
EDID v2
FFFFh
128-byte Data
Structure
ALR :
80h -> FFh
256 bytes
Basic EDID v1
FFFFh
256-byte Data
Structure
ALR
256
*
AHR
0000h
0000h
A0h/A1h
0000h
A2h/A3h + A6h/A7h
A0h/A1h
15
87
Addr Pointer
0
AHR
ALR
DDC v2 + P&D mode: CF[1:0] bits = 10b
Basic EDID v1
Extended EDID v1 (if present)
FFFFh
ALR :
00h -> 7Fh
FFFFh
128-byte Data
Structure
ALR :
80h -> FFh
256 bytes
128-byte Data
Structure
256 bytes
256 bytes
FFFFh
EDID v2
0000h
0000h
A0h/A1h
15
Addr Pointer
104/144
0
1
ALR
A2h/A3h
15
Addr Pointer
ALR
512
*
AHR<7:1>
0000h
A0h/A1h
9 87
AHR<7:1>
256-byte Data
Structure
0
9 87
AHR<7:1>
0
ALR
ST72774/ST727754/ST72734
DDC INTERFACE (Cont’d)
■ Write Operation
Once the DDC1/2B Interface has acknowledged a
write transfer request, i.e. a Device Address with
RW=0, it waits for a data address. When the latter
is received, it is acknowledged and loaded into the
ALR.
Then, the master may send any number of data
bytes that are all acknowledged by the DDC1/2B
Interface. The data bytes are written in RAM if the
WP bit=0 in the DCR register, otherwise the RAM
location is not modified.
In any case, all write operations are performed
in RAM and therefore do not delay DDC
transfers, although concurrent software
execution is halted for 2 cycles.
After each byte is transferred, the internal address
counter is automatically incremented.
If the counter is pointing to the top of the structure,
it rolls over to the bottom since the incrementation
is performed only on the 7 or 8 LSB’s of the pointer
depending on the selected data structure size. In
other words, ALR rolls over from FFh to 00h for
Device Addresses A2h/A3h and A6h/A7h.
Otherwise, it rolls over from 7Fh to 00h or from FFh
to 80h depending on the MSB of the last data
address received.
Then after that last byte has been effectively
written in RAM, the EDF flag is set and an interrupt
is generated if EDE is set.
The transfer is terminated
generating a STOP condition.
by
the
master
Figure 65. Write sequence
Addr.
Pointer
XXXXh
ADDR
ADDR + 1
ADDR + n -1 ADDR + n
DATA IN 1
DATA IN 2
DATA IN n
■ Read Operations
All read operations consist of retrieving the data
pointed to by an internal address counter which is
initialized by a dummy write and incremented by
any read. The DDC1/2B Interface always waits for
an acknowledge during the 9th bit-time. If the
master does not pull the SDA line low during this
bit-time, the DDC1/2B Interface ends the transfer
and switches to a stand-by state.
– Current address read: After generating a
START condition the master sends a read device
address (RW = 1). The DDC1/2B Interface acknowledges this and outputs the data byte pointed to by the internal address pointer which is
subsequently incremented. The master must
NOT acknowledge this byte and must terminate
the transfer with a STOP condition.
ACK
STOP
ACK
R/W
ACK
START
DATA ADDR.
ACK
SDA
ACK
DEV ADDR
– Random address read: The master performs a
dummy write to load the data address into the
ALR. Then the master sends a RESTART condition followed by a read Device Address (RW=1).
– Sequential address read: This mode is similar
to the current and random address reads, except
that the master DOES acknowledge the data
byte for the DDC1/2B Interface to output the next
byte in sequence. To terminate the read operation the master must NOT acknowledge the last
data byte and must generate a STOP condition.
The data output are from consecutive memory
addresses. The internal address counter is incremented automatically after each byte. If the
counter is pointing to the top of the structure, it
rolls over to the bottom since the incrementation
is performed only on the 7 or 8 LSB’s of the
counter depending on the selected data structure
size.
105/144
ST72774/ST727754/ST72734
DDC INTERFACE (Cont’d)
Figure 66. Read sequences
CURRENT ADDRESS READ
Addr.
ADDR
Pointer
ADDR + 1
DEV ADDR
SDA
STOP
NO ACK
START
R/W
ACK
DATA OUT
RANDOM ADDRESS READ
Addr.
XXXXh
DEV ADDR
DEV ADDR
DATA OUT
R/W
ACK
ACK
RESTART
R/W
ACK
DATA ADDR.
STOP
SDA
START
ADDR + 1
ADDR
NO ACK
Pointer
SEQUENTIAL ADDRESS READ
Addr.
ADDR
Pointer
ADDR + 1
ADDR + n -1
DATA OUT 2
DATA OUT n
ADDR + n
106/144
STOP
ACK
R/W
ACK
START
DATA OUT 1
NO ACK
SDA
ACK
DEV ADDR
ST72774/ST727754/ST72734
DDC INTERFACE (Cont’d)
4.8.5.2 DDC/CI - Factory Alignment Interface
4.8.5.2.1 Functional Description
Refer to the CR, SR1 and SR2 registers in Section
4.8.6. for the bit definitions.
4.8.5.2.2 I2C Modes
■ General description
In I2C mode, the interface can operate in the
following modes:
The DDC/CI interface works as an I/O interface
between the microcontroller and the DDC2Bi,
EDDC or Factory alignment protocols. It receives
and transmits data in Slave I2C mode using an
interrupt or polled handshaking.
– Slave transmitter/receiver
Both start and stop conditions are generated by
the master. The I2C clock (SCL) is always
received by the interface from a master, but the
interface is able to stretch the clock line.
The interface is connected to the I 2C bus by a data
pin (SDAD) and a clock pin (SCLD) configured as
open drain.
The interface is capable of recognizing both its
own programmable address (7-bit) and its default
hardware address (Enhanced DDC address: 60h/
61h). The Enhanced DDC address detection may
be enabled or disabled by software. It never
recognizes the Start byte (01h) whatever its own
address is.
The DDC/CI interface has five internal register
locations.
Two of them are used for initialization of the
interface:
– Own Address Register OAR
– Control register CR
The following four registers are used during data
transmission/reception:
– Data Register DR
– Control Register CR
– Status Register 1 SR1
– Status Register 2 SR2
The interface decodes an I2C or DDC2Bi address
stored by software in the OAR register and/or the
EDDC address (60h/61h) as its default hardware
address.
After a reset, the interface is disabled.
■ Slave Mode
As soon as a start condition is detected, the
address is received from the SDA line and sent to
the shift register; then it is compared with the
programmable address of the interface or the
Enhanced DDC address (if selected by software).
Address not matched: the interface ignores it
and waits for another Start condition.
Address matched: the following events occur in
sequence:
– Acknowledge pulse is generated if the ACK bit is
set.
– EVF and ADSL bits are set.
– An interrupt is generated if the ITE bit is set.
Then the interface waits for a read of the SR1
register, holding the SCL line low (see Figure 67
Transfer sequencing EV1).
Next, the DR register must be read to determine
from the least significant bit if the slave must enter
Receiver or Transmitter mode.
107/144
ST72774/ST727754/ST72734
DDC INTERFACE (Cont’d)
Slave Receiver
Following the address reception and after SR1
register has been read, the slave receives bytes
from the SDA line into the DR register via the
internal shift register. After each byte, the following
events occur in sequence:
– Acknowledge pulse is generated if the ACK bit is
set.
– EVF and BTF bits are set.
– An interrupt is generated if the ITE bit is set.
Then the interface waits for a read of the SR1
register followed by a read of the DR register,
holding the SCL line low (see Figure 67 Transfer
sequencing EV2).
Slave Transmitter
Following the address reception and after SR1
register has been read, the slave sends bytes from
the DR register to the SDA line via the internal shift
register.
The slave waits for a read of the SR1 register
followed by a write in the DR register, holding the
SCL line low (see Figure 67 Transfer sequencing
EV3).
When the acknowledge pulse is received:
Then the interface waits for a read of the SR2
register (see Figure 67 Transfer sequencing EV4).
Error Cases
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
the BERR bits are set and an interrupt is generated if the ITE bit is set.
If it is a Stop then the interface discards the data,
releases the lines and waits for another Start
condition.
If it is a Start then the interface discards the data
and waits for the next slave address on the bus.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set and an interrupt is generated if the ITE bit is set.
Note:In both cases, SCL line is not held low; however,
SDA line can remain low due to possible «0» bits
transmitted last. It is then necessary to release both
lines by software.
How to release the SDA / SCL lines
Set and subsequently clear the STOP bit while
BTF is set. The SDA/SCL lines are released after
the transfer of the current byte.
Other Events
■
– EVF and BTF bits are set.
– An interrupt is generated if the ITE bit is set.
Closing slave communication
■
After the last data byte is transferred, a Stop
Condition is generated by the master. The
interface detects this condition and in this case:
– EVF and STOPF bits are set.
– An interrupt is generated if the ITE bit is set.
108/144
ADSL: Detection of a Start condition after an
acknowledge time-slot.
The state machine is reset and starts a new
process. The ADSL bit is set and an interrupt is
generated if the ITE bit is set. The SCL line is
stretched low.
STOPF: Detection of a Stop condition after an
acknowledge time-slot.
The state machine is reset. Then the STOPF
flag is set and an interrupt is generated if the ITE
bit is set.
ST72774/ST727754/ST72734
DDC INTERFACE (Cont’d)
Figure 67. Transfer Sequencing
Slave receiver:
S Address
A
Data1
A
EV1
Data2
A
EV2
.....
EV2
DataN
A
P
EV2
EV4
NA
P
Slave transmitter:
S Address
A
Data1
EV1 EV3
A
Data2
A
EV3
EV3
.....
DataN
EV3
EV4
Legend:
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
Figure 68. Event Flags and Interrupt Generation
ITE
BTF
ADSL
AF
STOPF
BERR
INTERRUPT
EVF
109/144
ST72774/ST727754/ST72734
DDC INTERFACE (Cont’d)
4.8.6 Register Description
DDC CONTROL REGISTER (CR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 3 = Reserved. Forced to 0 by hardware.
7
0
0
0
PE
EDDC
EN
0
ACK
STOP
ITE
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = PE Peripheral enable.
This bit is set and cleared by software.
0: Peripheral disabled
1: Slave capability
Notes:
– When PE=0, all the bits of the CR register and
the SR register are reset. All outputs are released while PE=0
– When PE=1, the corresponding I/O pins are selected by hardware as alternate functions.
– To enable the I2C interface, write the CR register
TWICE with PE=1 as the first write only activates
the interface (only PE is set).
Bit 4 = EDDCEN Enhanced DDC address
detection enabled.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disabled
(PE=0). The 60h/61h Enhanced DDC address is
acknowledged.
0: Enhanced DDC address detection disabled
1: Enhanced DDC address detection enabled
110/144
Bit 2 = ACK Acknowledge enable.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disabled
(PE=0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or
a data byte is received
Bit 1 = STOP Release I2C bus.
This bit is set and cleared by software or when the
interface is disabled (PE=0).
– Slave Mode:
0: Nothing
1: Release the SCL and SDA lines after the current byte transfer (BTF=1). The STOP bit has to
be cleared by software.
Bit 0 = ITE Interrupt enable.
This bit is set and cleared by software and cleared
by hardware when the interface is disabled
(PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to Figure 68 for the relationship between the
events and the interrupt.
SCL is held low when the BTF or ADSL is detected.
ST72774/ST727754/ST72734
DDC INTERFACE (Cont’d)
DDC STATUS REGISTER 1 (SR1)
Read Only
Reset Value: 0000 0000 (00h)
7
EVF
0
0
TRA
BUSY
BTF
ADSL
0
0
Bit 7 = EVF Event flag.
This bit is set by hardware as soon as an event
occurs. It is cleared by software reading SR2
register in case of error event or as described in
Figure 67. It is also cleared by hardware when the
interface is disabled (PE=0).
0: No event
1: One of the following events has occurred:
– BTF=1 (Byte received or transmitted)
– ADSL=1 (Address matched in Slave mode
while ACK=1)
– AF=1 (No acknowledge received after byte
transmission if ACK=1)
– STOPF=1 (Stop condition detected in Slave
mode)
– BERR=1 (Bus error, misplaced Start or Stop
condition detected)
Bit 6 = Reserved. Forced to 0 by hardware.
Bit 5 = TRA Transmitter/Receiver.
When BTF is set, TRA=1 if a data byte has been
transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware after
detection of Stop condition (STOPF=1) or when
the interface is disabled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
Bit 4 = BUSY Bus busy.
This bit is set by hardware on detection of a Start
condition and cleared by hardware on detection of
a Stop condition. It indicates a communication in
progress on the bus. This information is still
updated when the interface is disabled (PE=0).
0: No communication on the bus
1: Communication ongoing on the bus
Bit 3 = BTF Byte transfer finished.
This bit is set by hardware as soon as a byte is
correctly received or transmitted with interrupt
generation if ITE=1. It is cleared by software
reading SR1 register followed by a read or write of
DR register. It is also cleared by hardware when
the interface is disabled (PE=0).
– Following a byte transmission, this bit is set after
reception of the acknowledge clock pulse. . BTF
is cleared by reading SR1 register followed by
writing the next byte in DR register.
– Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared by reading SR1 register
followed by reading the byte from DR register.
The SCL line is held low while BTF=1.
0: Byte transfer not done
1: Byte transfer succeeded
Bit 2 = ADSL Address matched (Slave mode). This
bit is set by hardware as soon as the received
slave address matched with the OAR register
content or the Enhanced DDC address is
recognized. An interrupt is generated if ITE=1. It is
cleared by software reading SR1 register or by
hardware when the interface is disabled (PE=0).
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
Bit 1:0 = Reserved. Forced to 0 by hardware.
111/144
ST72774/ST727754/ST72734
DDC INTERFACE (Cont’d)
DDC STATUS REGISTER 2 (SR2)
Read Only
Reset Value: 0000 0000 (00h)
7
0
0
0
0
AF
STOPF
0
BERR
EDDC
F
Bit 7:5 = Reserved. Forced to 0 by hardware.
Bit 4 = AF Acknowledge failure.
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while AF=1.
0: No acknowledge failure
1: Acknowledge failure
Bit 3 = STOPF Stop detection.
This bit is set by hardware when a Stop condition is
detected on the bus after an acknowledge (if
ACK=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
Bit 2 = Reserved. Forced to 0 by hardware.
112/144
Bit 1 = BERR Bus error.
This bit is set by hardware when the interface
detects a misplaced Start or Stop condition. An
interrupt is generated if ITE=1. It is cleared by
software reading SR2 register or by hardware
when the interface is disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Bit 0 = EDDCF Enhanced DDC address detected.
This bit is set by hardware when the Enhanced
DDC address (60h/61h) is detected on the bus
while EDDCEN=1. It is cleared by hardware when
a Start or a Stop condition (STOPF=1) is detected,
or when the interface is disabled (PE=0).
0: No Enhanced DDC address detected on bus
1: Enhanced DDC address detected on bus
ST72774/ST727754/ST72734
DDC INTERFACE (Cont’d)
DDC DATA REGISTER (DR)
DDC OWN ADDRESS REGISTER (OAR)
Read / Write
Reset Value: 0000 0000 (00h)
Read / Write
Reset Value: 0000 0000 (00h)
7
D7
D6
D5
D4
D3
D2
D1
0
7
D0
ADD7
Bit 7:0 = D7-D0 8-bit Data Register.
These bits contain the byte to be received or
transmitted on the bus.
– Transmitter mode: Byte transmission start automatically when the software writes in the DR register.
– Receiver mode: the first data byte is received automatically in the DR register using the least significant bit of the address.
Then, the next data bytes are received one by
one after reading the DR register.
0
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
Bit 7:1 = ADD7-ADD1 Interface address.
These bits define the I2C bus programmable
address of the interface. They are not cleared
when the interface is disabled (PE=0).
Bit 0 = ADD0.
This bit is Don’t Care, the interface acknowledges
either 0 or 1. It is not cleared when the interface is
disabled (PE=0).
Note: Address 01h is always ignored.
113/144
ST72774/ST727754/ST72734
DDC INTERFACE (Cont’d)
DDC1/2B CONTROL REGISTER (DCR)
Read / Write
Reset Value: 0000 0000 (00h)
7
Bit 1 = WP Write Protect.
This bit is set and cleared by software.
0: Enable writes to the RAM.
1: Disable DMA write transfers and protect the
RAM content. CPU writes to the RAM are not
affected.
0
0
CF2
EDF
EDE
CF1
CF0
WP
HWPE
Bit 0= HWPE Peripheral Enable.
This bit is set and cleared by software.
Bit 7 = Reserved.
Forced by hardware to 0.
Bit 5 = EDF End of Download interrupt Flag.
This bit is set by hardware and cleared by
software.
0: Download not started or not completed yet.
1: Download completed. Last byte of data structure (relative address 7Fh or FFh) has been
stored in RAM.
Bit 4 = EDE End of Download interrupt Enable .
This bit is set and cleared by software.
0: Interrupt disabled.
1: A DDC1/2B interrupt is generated if EDF bit is
set.
Bits 6, 3:2 = CF[2:0] Configuration bits.
These bits are set and cleared by software only
when the peripheral is disabled (HWPE = 0). They
define which EDID structure version is used and
which Device Addresses are recognized as shown
in the following table:
0: Release the SDA port pin and ignore Vsync
and SCL port pins. The other bits of the DCR
and the content of the AHR are left unchanged.
1: Enable the DDC Interface and respond to the
DDC1/DDC2B protocol.
ADDRESS POINTER HIGH REGISTER (AHR)
Read / Write
Reset Value: see Register Map
7
0
MSB
LSB
AHR contains the 8 MSB’s of the 16-bit address
pointer. It therefore defines the location of the 256byte block containing the data structure within the
CPU address space.
Note: AHR0 is ignored when CF[1:0] = 10 (P&D+ v2
mode) to allow non-overlapping 128-byte and 256byte data structures.
CF[2:0] Bit
Values
EDID version used
DDC1 Mode support / Transition Mode support
000
DDC v2
Yes (128b EDID) / Yes
001
P&D
No
010
v2 + P&D
Yes (128b EDID) / Yes
011
FPDI-2
No
256b-EDID
@ A6h/A7h
100
DDC v2
No
128b-EDID
@A0h/A1h
111
114/144
128b-EDID
@A0h/A1h
256b-EDID
@ A2h/A3h
128b-EDID
@A0h/A1h
256b-EDID
@ A2h/A3h
Reserved d sd
101
110
DDC2B Addresses Recognized
v2 + P&D
No
Reserved d sd
128b-EDID
@A0h/A1h
256b-EDID
@ A2h/A3h
ST72774/ST727754/ST72734
DDC INTERFACE (Cont’d)
Table 26. DDC Register Map and Reset Values
Address
(Hex.)
50
51
52
54
56
0C
0D
Register
Name
7
6
CR
0
5
4
PE
EDDCEN
0
0
3
2
1
0
ACK
STOP
ITE
0
0
0
0
0
0
Reset Value
0
SR1
EVF
TRA
BUSY
BTF
ADSL
Reset Value
0
0
0
0
0
0
AF
STOPF
BERR
EDDCF
Reset Value
0
0
0
0
0
0
0
0
SR2
OAR
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
Reset Value
0
0
0
0
0
0
0
0
DR
D7
D6
D5
D4
D3
D2
D1
D0
Reset Value
0
0
0
0
0
0
0
0
CF2
EDF
EDE
CF1
CF0
WP
HWPE
DCR
Reset Value
0
0
0
0
0
0
0
0
AHR
AHR7
AHR6
AHR5
AHR4
AHR3
AHR2
AHR1
AHR0
Reset Value
0
0
0
0
0
0
0
0
115/144
ST72774/ST727754/ST72734
4.9 PWM/BRM GENERATOR (DAC)
4.9.1 Introduction
This PWM/BRM peripheral includes two types of
PWM/BRM outputs, with differing step resolutions
based on the Pulse Width Modulator (PWM) and
Binary Rate Multiplier (BRM) Generator technique
are available. It allows the digital to analog
conversion (DAC) when used with external
filtering.
4.9.2 Main Features
■ Fixed frequency: fCPU/64
■ Resolution: TCPU
■ 10-Bit PWM/BRM generator with a step of
VDD/210 (5mV if VDD=5V)
4.9.3 Functional Description
4.9.3.1 PWM/BRM
The 10 bits of the 10-bit PWM/BRM are distributed
as 6 PWM bits and 4 BRM bits. The generator
consists of a 12-bit counter (common for all
channels), a comparator and the PWM/BRM
generation logic.
PWM Generation
The counter increments continuously, clocked at
internal CPU clock. Whenever the 6 least
significant bits of the counter (defined as the PWM
counter) overflow, the output level for all active
channels is set.
The state of the PWM counter is continuously
compared to the PWM binary weight for each
channel, as defined in the relevant PWM register,
and when a match occurs the output level for that
channel is reset.
This Pulse Width modulated signal must be
filtered, using an external RC network placed as
close as possible to the associated pin. This
provides an analog voltage proportional to the
average charge passed to the external capacitor.
Thus for a higher mark/space ratio (High time
much greater than Low time) the average output
voltage is higher. The external components of the
RC network should be selected for the filtering
level required for control of the system variable.
Each output may individually have its polarity
inverted by software, and can also be used as a
logical output.
Figure 69. PWM Generation
COUNTER
63
OVERFLOW
OVERFLOW
OVERFLOW
COMPARE
VALUE
000
t
PWM OUTPUT
t
TCPU x 64
116/144
ST72774/ST727754/ST72734
PWM/BRM Outputs (Cont’d)
PWM/BRM Outputs
The PWM/BRM outputs are assigned to dedicated
pins.
The RC filter time must be higher than TCPUx64.
Table 27. 6-Bit PWM Ripple After Filtering
Figure 70. Typical PWM Output Filter
OUTPUT
VOLTAGE
OUTPUT
STAGE
Rext
Cext
Cext (µF)
V RIPPLE (mV)
0.128
78
1.28
7.8
12.8
0.78
With RC filter (R=1KΩ),
fCPU = 8 MHz
VDD = 5V
PWM Duty Cycle 50%
R=Rext.
Figure 71. PWM Simplified Voltage Output After Filtering
V DD
PWMOUT
0V
Vripple (mV)
V DD
OUTPUT
VOLTAGE
V OUTAVG
0V
"CHARGE"
V
"DISCHARGE"
"CHARGE"
"DISCHARGE"
DD
PWMOUT
0V
V DD
V ripple (mV)
OUTPUT
VOLTAGE
0V
V OUTAVG
"CHARGE"
"DISCHARGE"
"CHARGE"
"DISCHARGE"
VR01956
117/144
ST72774/ST727754/ST72734
PWM/BRM GENERATOR (Cont’d)
BRM Generation
The BRM bits allow the addition of a pulse to widen
a standard PWM pulse for specific PWM cycles.
This has the effect of “fine-tuning” the PWM Duty
cycle (without modifying the base duty cycle), thus,
with the external filtering, providing additional fine
voltage steps.
The incremental pulses (with duration of T CPU) are
added to the beginning of the original PWM pulse.
The PWM intervals which are added to are
specified in the 4-bit BRM register and are
encoded as shown in the following table. The BRM
values shown may be combined together to
provide a summation of the incremental pulse
intervals specified.
The pulse increment corresponds to the PWM
resolution.
For example,if
Then 3.0 µs-long pulse will be output at 8 µs
intervals,
except
for
cycles
numbered
2,4,6,10,12,14, where the pulse is broadened to
3.125 µs.
Note: If 00h is written to both PWM and BRM registers,
the generator output will remain at “0”. Conversely,
if both registers hold data 3Fh and 0Fh, respectively, the output will remain at “1” for all intervals #1 to
#15, but it will return to zero at interval #0 for an
amount of time corresponding to the PWM resolution (TCPU).
An output can be set to a continuous “1” level by
clearing the PWM and BRM values and setting
POL = “1” (inverted polarity) in the PWM register.
This allows a PWM/BRM channel to be used as an
additional I/O pin if the DAC function is not
required.
Table 28. Bit BRM Added Pulse Intervals
(Interval #0 not selected).
BRM 4 - Bit Data
– Data 18h is written to the PWM register
– Data 06h (00000110b) is written to the BRM register
– with a 8MHz internal clock (125ns resolution)
Incremental Pulse Intervals
0000
none
0001
i=8
0010
i = 4,12
0100
i = 2,6,10,14
1000
i = 1,3,5,7,9,11,13,15
Figure 72. BRM pulse addition (PWM > 0)
m=0
TCPU x 64
m=1
TCPU x 64
m=2
TCPU x 64
TCPU x 64 increment
118/144
m = 15
TCPU x 64
ST72774/ST727754/ST72734
PWM/BRM GENERATOR (Cont’d)
Figure 73. Simplified Filtered Voltage Output Schematic with BRM added
=
=
VDD
PWMOUT
0V
VDD
BRM = 1
OUTPUT
BRM = 0
VOLTAGE
0V
TCPU
BRM
EXTENDED PULSE
Figure 74. Graphical Representation of 4-Bit BRM Added Pulse Positions
PWM Pulse Number (0-15)
BRM VALUE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0001 bit0=1
0001 bit0=1
0100 bit2=1
0100 bit2=1
Examples
0110
1111
119/144
ST72774/ST727754/ST72734
PWM/BRM GENERATOR (Cont’d)
4.9.3.2 PWM/BRM OUTPUTS
The PWM/BRM outputs are assigned to dedicated
pins.
If necessary, these pins can be used in push-pull
or open-drain modes under software control.
In these pins, the PWM/BRM outputs are
connected to a serial resistor which must be taken
into account to calculate the RC filter.
Figure 75. Precision for PWM/BRM Tuning for VOUTEFF (After filtering)
0
6 - Bit
PWM
VDD
1
4 - Bit
BRM
or
6 - Bit
BRM
120/144
2
1
1
3
4
5
10
20
60
10
40
61
15
50
63
62
63
64 STEPS
VDD
0F
each
64
16 sub steps of VDD each
1024
V
64 sub steps of DD each
4096
ST72774/ST727754/ST72734
PWM/BRM GENERATOR (Cont’d)
4.9.4 Register Description
4.9.4.1 PWM/BRM REGISTERS
On a channel basis, the 10 bits are separated into
two data registers:
BRM REGISTERS
BRM21 (Channels 2 + 1)
BRM43 (Channels 4 + 3)
BRM65 (Channels 6 + 5)
– A 6-bit PWM register corresponding to the binary
weight of the PWM pulse.
– A 4-bit BRM register defining the intervals where
an incremental pulse is added to the beginning of
the original PWM pulse. Two BRM channel values share the same register.
BRM87 (Channels 8 + 7)
Read/Write
Reset Value: 0000 0000 (00h)
7
Note: The number of PWM and BRM channels available
depends on the device. Refer to the device pin description and register map.
0
B7
B6
B5
B4
B3
B2
B1
B0
Bits 7:4 = B[7:4] BRM Bits (channel i+1)
PWM[1:8] REGISTERS
Bits 3:0 = B[3:0] BRM Bits (channel i)
Read/Write
Reset Value 1000 0000 (80h)
4.9.4.2 OUTPUT ENABLE REGISTER
Read/Write
Reset Value 1000 0000 (80h)
7
0
7
1
POL
P5
P4
P3
P2
P1
0
P0
OE7
OE6
OE5
OE4
OE3
OE2
OE1
OE0
Bit 7 = Reserved (read as “1”)
Bit 7:0 = OE[7:0] Output Enable Bit.
When OEi is set, PWM output function is enabled.
Bit 6 = POL Polarity Bit.
When POL is set, output signal polarity is inverse;
otherwise, no change occurs.
0: PWM output is disabled
1: PWM output is enabled
Bits 5:0 = P[5:0] PWM Pulse Binary Weight for
channel i .
Note: From the programmer’s point of view, the PWM and
BRM registers can be regarded as being combined
to give one data value.
For example (10-bit)
0
POL
P
P
P
P
P
P
+
B
B
B
B
Effective (with external RC filtering) DAC value
0
POL
P
P
P
P
P
P
B
B
B
B
121/144
ST72774/ST727754/ST72734
Table 29. PWM Register Map
Address
(Hex.)
Register
Name
7
6
5
4
3
2
32
PWM1
POL
33
BRM21
BRM Channel 2
34
PWM2
POL
P5 ..P0
35
PWM3
POL
P5 ..P0
36
BRM43
BRM Channel 4
37
PWM4
POL
P5 ..P0
38
PWM5
POL
P5 ..P0
39
BRM65
BRM Channel 6
3A
PWM6
POL
P5 ..P0
3B
PWM7
POL
P5 ..P0
3C
BRM87
BRM Channel 8
3D
PWM8
POL
3E
PWMCR
122/144
1
P5 ..P0
BRM Channel 1
BRM Channel 3
BRM Channel 5
BRM Channel 7
P5 ..P0
OE7 ..OE0
0
ST72774/ST727754/ST72734
4.10 8-BIT A/D CONVERTER (ADC)
4.10.3 Functional Description
4.10.3.1 Analog Power Supply
VDDA and VSSA are the high and low level
reference voltage pins. In some devices (refer to
device pin out description) they are internally
connected to the VDD and VSS pins.
4.10.1 Introduction
The on-chip Analog to Digital Converter (ADC)
peripheral is a 8-bit, successive approximation
converter with internal sample and hold circuitry.
This peripheral has up to 16 multiplexed analog
input channels (refer to device pin out description)
that allow the peripheral to convert the analog
voltage levels from up to 16 different sources.
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
The result of the conversion is stored in a 8-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
See electrical characteristics section for more
details.
4.10.2 Main Features
■ 8-bit conversion
■ Up to 16 channels with multiplexed input
■ Linear successive approximation
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 76.
Figure 76. ADC Block Diagram
fCPU
COCO
0
ADON
0
fADC
DIV 4
CH3
CH2
CH1
CH0
ADCCSR
4
AIN0
HOLD CONTROL
AIN1
ANALOG
MUX
RADC
ANALOG TO DIGITAL
CONVERTER
CADC
AINx
ADCDR
D7
D6
D5
D4
D3
D2
D1
D0
123/144
ST72774/ST727754/ST72734
4.10.3.2 Digital A/D Conversion Result
The conversion is monotonic, meaning that the
result never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (VAIN) is greater than or equal
to V DDA (high-level voltage reference) then the
conversion result in the DR register is FFh (full
scale) without overflow indication.
ADC Configuration
The total duration of the A/D conversion is 12 ADC
clock periods (1/fADC=4/fCPU).
The analog input ports must be configured as
input, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
If input voltage (VAIN) is lower than or equal to
VSSA (low-level voltage reference) then the
conversion result in the DR register is 00h.
In the CSR register:
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the
parametric section.
ADC Conversion
In the CSR register:
RAIN is the maximum recommended impedance
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
4.10.3.3 A/D Conversion Phases
The A/D conversion is based on two conversion
phases as shown in Figure 77:
Sample capacitor loading [duration: tLOAD]
During this phase, the VAIN input voltage to be
measured is loaded into the CADC sample
capacitor.
■ A/D conversion [duration: tCONV]
During this phase, the A/D conversion is
computed (8 successive approximations cycles)
and the CADC sample capacitor is disconnected
from the analog input pin to get the optimum
analog to digital conversion accuracy.
While the ADC is on, these two phases are
continuously repeated.
■
At the end of each conversion, the sample
capacitor is kept loaded with the previous
measurement load. The advantage of this
behaviour is that it minimizes the current
consumption on the analog pin in case of single
input channel measurement.
4.10.3.4 Software Procedure
Refer to the control/status register (CSR) and data
register (DR) in Section 4.10.6 for the bit
definitions and to Figure 77 for the timings.
124/144
– Select the CH[3:0] bits to assign the analog
channel to be converted.
– Set the ADON bit to enable the A/D converter
and to start the first conversion. From this time
on, the ADC performs a continuous conversion of the selected channel.
When a conversion is complete
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register and remains
valid until the next conversion has ended.
A write to the CSR register (with ADON set) aborts
the current conversion, resets the COCO bit and
starts a new conversion.
Figure 77. ADC Conversion Timings
ADON
ADCCSR WRITE
OPERATION
tCONV
HOLD
CONTROL
tLOAD
COCO BIT SET
4.10.4 Low Power Mode
Mode
WAIT
Description
No effect on A/D Converter
Note: The A/D converter is disabled by resetting the
ADON bit. With this feature, power consumption is
reduced when no conversion is needed and between single shot conversions.
4.10.5 Interrupts
None
ST72774/ST727754/ST72734
8-BIT A/D CONVERTER (ADC) (Cont’d)
4.10.6 Register Description
CONTROL/STATUS REGISTER (CSR)
Read /Write
Channel Pin*
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
Reset Value: 0000 0000 (00h)
7
0
COCO
0
ADON
0
CH3
CH2
CH1
CH0
Bit 7 = COCO Conversion Complete
This bit is set by hardware. It is cleared by software
reading the result in the DR register or writing to
the CSR register.
0: Conversion is not complete
1: Conversion can be read from the DR register
Bit 6 = Reserved. must always be cleared.
CH3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CH2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CH1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CH0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DATA REGISTER (DR)
Read Only
Bit 5 = ADON A/D Converter On
This bit is set and cleared by software.
Reset Value: 0000 0000 (00h)
0: A/D converter is switched off
1: A/D converter is switched on
7
Bit 4 = Reserved. must always be cleared.
0
D7
Bit 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
Note: The number of pins AND the channel selection varies according to the device. Refer to the device
pinout.
D6
D5
D4
D3
D2
D1
D0
Bit 7:0 = D[7:0] Analog Converted Value
This register contains the converted analog value
in the range 00h to FFh.
Note: Reading this register reset the COCO flag.
Table 30. ADC Register Map
Address
Register
Name
7
6
5
4
3
2
1
0
0A
ADCDR
Reset Value
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
0B
ADCCSR
Reset Value
COCO
-
ADON
-
CH3
CH2
CH1
CH0
0
0
0
0
0
0
0
0
(Hex.)
125/144
ST72774/ST727754/ST72734
5 INSTRUCTION SET
5.1 ST7 ADDRESSING MODES
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups:
Addressing Mode
Example
Inherent
nop
Immediate
ld A,#$55
Direct
ld A,$55
Indexed
ld A,($55,X)
Indirect
ld A,([$55],X)
Relative
jrne loop
Bit operation
bset
byte,#5
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
so, most of the addressing modes may be
subdivided in two sub-modes called long and
short:
– Long addressing mode is more powerful because it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cycles.
– Short addressing mode is less powerful because
it can generally only access page zero (0000h 00FFh range), but the instruction size is more
compact, and faster. All memory to memory instructions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and
short addressing modes.
Table 31. ST7 Addressing Mode Overview
Mode
Syntax
Pointer
Address
(Hex.)
Destination/
Source
Pointer
Size
(Hex.)
Length
(Bytes)
Inherent
nop
+0
Immediate
ld A,#$55
+1
Short
Direct
ld A,$10
00..FF
+1
Long
Direct
ld A,$1000
0000..FFFF
+2
No Offset
Direct
Indexed
ld A,(X)
00..FF
+ 0 (with X register)
+ 1 (with Y register)
Short
Direct
Indexed
ld A,($10,X)
00..1FE
+1
Long
Direct
Indexed
ld A,($1000,X)
0000..FFFF
Short
Indirect
ld A,[$10]
00..FF
00..FF
byte
+2
Long
Indirect
ld A,[$10.w]
0000..FFFF
00..FF
word
+2
Short
Indirect
Indexed
ld A,([$10],X)
00..1FE
00..FF
byte
+2
Long
Indirect
Indexed
ld A,([$10.w],X)
0000..FFFF
00..FF
word
+2
00..FF
byte
+2
1)
Relative
Direct
jrne loop
PC-128/PC+127
Relative
Indirect
jrne [$10]
PC-128/PC+1271)
Bit
Direct
bset $10,#7
00..FF
Bit
Indirect
bset [$10],#7
00..FF
Bit
Direct
Relative
btjt $10,#7,skip
00..FF
Bit
Indirect
Relative
btjt [$10],#7,skip 00..FF
+1
+2
+1
00..FF
byte
+2
+2
00..FF
byte
+3
Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following
JRxx.
126/144
6
ST72774/ST727754/ST72734
ST7 ADDRESSING MODES (Cont’d)
5.1.1 Inherent
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required
information for the CPU to process the operation.
Inherent Instruction
Function
NOP
No operation
TRAP
S/W Interrupt
WFI
Wait For Interrupt (Low Power
Mode)
HALT
Disabled, forces a RESET
RET
Sub-routine Return
IRET
Interrupt Sub-routine Return
SIM
Set Interrupt Mask
RIM
Reset Interrupt Mask
SCF
Set Carry Flag
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
LD
Load
CLR
Clear
The direct addressing mode consists of two submodes:
Direct (short)
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF
addressing space.
Direct (long)
The address is a word, thus allowing 64 Kbyte
addressing space, but requires 2 bytes after the
opcode.
5.1.4 Indexed (No Offset, Short, Long)
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three
sub-modes:
PUSH/POP
Push/Pop to/from the stack
INC/DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
MUL
Byte Multiplication
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
5.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte
contains the operand value.
Immediate Instruction
5.1.3 Direct
In Direct instructions, the operands are referenced
by their memory address.
Function
LD
Load
CP
Compare
BCP
Bit Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Operations
Indexed (No Offset)
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
The offset is a byte, thus requires only one byte
after the opcode and allows 00 - 1FE addressing
space.
Indexed (long)
The offset is a word, thus allowing 64 Kbyte
addressing space and requires 2 bytes after the
opcode.
5.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory
(pointer).
The pointer address follows the opcode. The
indirect addressing mode consists of two submodes:
Indirect (short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
127/144
ST72774/ST727754/ST72734
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
5.1.6 Indirect Indexed (Short, Long)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the
unsigned addition of an index register value (X or
Y) with a pointer value located in memory. The
pointer address follows the opcode.
The indirect indexed addressing mode consists of
two sub-modes:
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
Table 32. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Instructions
Function
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Addition/subtraction operations
BCP
Bit Compare
128/144
Short Instructions Only
Function
CLR
Clear
INC, DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
BSET, BRES
Bit Operations
BTJT, BTJF
Bit Test and Jump Operations
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
5.1.7 Relative mode (Direct, Indirect)
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to it.
Available Relative Direct/
Indirect Instructions
Function
JRxx
Conditional Jump
CALLR
Call Relative
The relative addressing mode consists of two submodes:
Relative (Direct)
The offset follows the opcode.
Relative (Indirect)
The offset is defined in memory, of which the address follows the opcode.
ST72774/ST727754/ST72734
5.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
Stack operation
PUSH
POP
Increment/Decrement
INC
DEC
Compare and Tests
CP
TNZ
BCP
Logical operations
AND
OR
XOR
CPL
NEG
Bit Operation
BSET
BRES
Conditional Bit Test and Branch
BTJT
BTJF
Arithmetic operations
ADC
ADD
SUB
SBC
MUL
Shift and Rotates
SLL
SRL
SRA
RLC
RRC
SWAP
SLA
Unconditional Jump or Call
JRA
JRT
JRF
JP
CALL
CALLR
NOP
Conditional Branch
JRxx
Interruption management
TRAP
WFI
IRET
Code Condition Flag modification
SIM
RIM
SCF
RSP
RET
RCF
Using a pre-byte
The instructions are described with one to four
bytes.
In order to extend the number of available opcodes
for an 8-bit CPU (256 opcodes), three different
prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they
precede.
The whole instruction becomes:
PC-2
End of previous instruction
PC-1
Prebyte
PC
opcode
PC+1
Additional word (0 to 2) according
to the number of bytes required to compute the effective address
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
PDY 90
Replace an X based instruction
using immediate, direct, indexed, or inherent addressing mode by a Y one.
PIX 92
Replace an instruction using direct, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode.
PIY 91
Replace an instruction using X indirect indexed addressing mode by a Y one.
129/144
ST72774/ST727754/ST72734
INSTRUCTION GROUPS (Cont’d)
Mnemo
Description
Function/Example
Dst
Src
H
I
N
Z
C
ADC
Add with Carry
A=A+M+C
A
M
H
N
Z
C
ADD
Addition
A=A+M
A
M
H
N
Z
C
AND
Logical And
A=A.M
A
M
N
Z
BCP
Bit compare A, Memory
tst (A . M)
A
M
N
Z
BRES
Bit Reset
bres Byte, #3
M
BSET
Bit Set
bset Byte, #3
M
BTJF
Jump if bit is false (0)
btjf Byte, #3, Jmp1
M
C
BTJT
Jump if bit is true (1)
btjt Byte, #3, Jmp1
M
C
CALL
Call subroutine
CALLR
Call subroutine relative
CLR
Clear
CP
Arithmetic Compare
tst(Reg - M)
reg
reg, M
CPL
One Complement
A = FFH-A
DEC
Decrement
dec Y
IRET
Interrupt routine return
Pop CC, A, X, PC
INC
Increment
inc X
JP
Absolute Jump
jp [TBL.w]
JRA
Jump relative always
JRT
Jump relative
JRF
Never jump
JRIH
Jump if ext. interrupt = 1
JRIL
Jump if ext. interrupt = 0
JRH
Jump if H = 1
H=1?
JRNH
Jump if H = 0
H=0?
JRM
Jump if I = 1
I=1?
JRNM
Jump if I = 0
I=0?
JRMI
Jump if N = 1 (minus)
N=1?
JRPL
Jump if N = 0 (plus)
N=0?
JREQ
Jump if Z = 1 (equal)
Z=1?
JRNE
Jump if Z = 0 (not equal)
Z=0?
JRC
Jump if C = 1
C=1?
JRNC
Jump if C = 0
C=0?
JRULT
Jump if C = 1
Unsigned <
JRUGE
Jump if C = 0
Jmp if unsigned >=
JRUGT
Jump if (C + Z = 0)
Unsigned >
130/144
jrf *
0
1
N
Z
C
reg, M
N
Z
1
reg, M
N
Z
M
H
reg, M
I
N
Z
N
Z
C
ST72774/ST727754/ST72734
INSTRUCTION GROUPS (Cont’d)
Mnemo
Description
Function/Example
Dst
Src
JRULE
Jump if (C + Z = 1)
Unsigned <=
LD
Load
dst <= src
reg, M
M, reg
MUL
Multiply
X,A = X * A
A, X, Y
X, Y, A
NEG
Negate (2’s compl)
neg $10
reg, M
NOP
No Operation
OR
OR operation
A=A+M
A
M
POP
Pop from the Stack
pop reg
reg
M
pop CC
CC
M
M
reg, CC
H
I
N
Z
N
Z
0
H
C
0
I
N
Z
N
Z
N
Z
C
C
PUSH
Push onto the Stack
push Y
RCF
Reset carry flag
C=0
RET
Subroutine Return
RIM
Enable Interrupts
I=0
RLC
Rotate left true C
C <= Dst <= C
reg, M
N
Z
C
RRC
Rotate right true C
C => Dst => C
reg, M
N
Z
C
RSP
Reset Stack Pointer
S = Max allowed
SBC
Subtract with Carry
A=A-M-C
N
Z
C
SCF
Set carry flag
C=1
SIM
Disable Interrupts
I=1
SLA
Shift left Arithmetic
C <= Dst <= 0
reg, M
N
Z
C
SLL
Shift left Logic
C <= Dst <= 0
reg, M
N
Z
C
SRL
Shift right Logic
0 => Dst => C
reg, M
0
Z
C
SRA
Shift right Arithmetic
Dst7 => Dst => C
reg, M
N
Z
C
SUB
Subtraction
A=A-M
A
N
Z
C
SWAP
SWAP nibbles
Dst[7..4] <=> Dst[3..0] reg, M
N
Z
TNZ
Test for Neg & Zero
tnz lbl1
N
Z
TRAP
S/W trap
S/W interrupt
WFI
Wait for Interrupt
XOR
Exclusive OR
N
Z
0
0
A
M
1
1
M
1
0
A = A XOR M
A
M
131/144
ST72774/ST727754/ST72734
6 ELECTRICAL CHARACTERISTICS
The ST727x4 device contains circuitry to protect
the inputs against damage due to high static
voltage or electric field. Nevertheless it is advised
to take normal precautions and to avoid applying to
this high impedance voltage circuit any voltage
higher than the maximum rated voltages. It is
recommended for proper operation that VIN and
VOUT be constrained to the range:
To enhance reliability of operation, it is
recommended to connect unused inputs to an
appropriate logic voltage level such as VSS or VDD.
All the voltages in the following table, are
referenced to VSS.
VSS ≤ (VIN or VOUT) ≤ VDD
Table 33. Absolute Maximum Ratings
Symbol
VDD
Recommended Supply Voltage
Value
Unit
-0.3 to +6.0
V
VIN
Input Voltage
VSS -0.3 to VDD + 0.3
V
VAIN
Analog Input Voltage (A/D Converter)
VSS -0.3 to VDD + 0.3
V
VOUT
Output Voltage
VSS -0.3 to VDD + 0.3
-10......+10
V
mA
-10......+10
mA
40
mA
0 to +70
°C
IIN
Input Current
IOUT
Output Current
IINJ
Accumulated injected current of all I/O pins (VDD,
VSS)
TA
Operating Temperature Range
TSTG
-65 to +150
°C
TJ
Junction Temperature
150
°C
PD
Power Dissipation
TBD
mW
ESD
ESD susceptibility
2000
V
132/144
7
Ratings
Storage Temperature Range
ST72774/ST727754/ST72734
6.1 POWER CONSIDERATIONS
The average chip-junction temperature, T J, in
degrees Celsius, may be calculated using the
following equation:
An approximate relationship between PD and TJ
(if PI/O is neglected) is given by:
PD = K÷ (TJ + 273°C) (2)
TJ = TA + (PD x θJA) (1)
Therefore:
Where:
– TA is the Ambient Temperature in °C,
– θJA is the Package Junction-to-Ambient Thermal
Resistance, in °C/W,
– P D is the sum of PINT and P I/O,
– PINT is the product of IDD and VDD, expressed in
Watts. This is the Chip Internal Power
– PI/O represents the Power Dissipation on Input
and Output Pins; User Determined.
For most applications PI/O <PINT and may be
neglected. P I/O may be significant if the device is
configured to drive Darlington bases or sink LED
Loads.
K = PD x (TA + 273°C) + θJA x P D2 (3)
Where:
– K is a constant for the particular part, which may
be determined from equation (3) by measuring
PD (at equilibrium) for a known TA. Using this
value of K, the values of PD and TJ may be obtained by solving equations (1) and (2) iteratively
for any value of TA.
Table 34. Thermal Characteristics
Symbol
Package
Value
Unit
θJA
θJA
PSDIP42
95
°C/W
TQFP44
95
°C/W
133/144
ST72774/ST727754/ST72734
6.2 AC/DC ELECTRICAL CHARACTERISTICS
(TA = 0 to +70°C unless otherwise specified)
GENERAL
Symbol
Parameter
VDD
Operating Supply Voltage
IDD
Conditions
RUN & WAIT mode
Min
Typ.
Max
Unit
4.0
5
5.5
V
CPU RUN mode
I/O in input mode
14
18
mA
CPU WAIT mode
VDD = 5V
12
18
mA
CPU HALT mode (see Note 1)
fCPU = 8 MHz,
N/A
USB Suspend mode (see Note 2)
TA = 20° C
N/A
Note 1: HALT mode no longer exists.
Note 2: The USB cell must be put in suspend mode as well as the MCU in HALT mode. Since the latter no longer exists
for enhanced arcing protection, the measurement of the USB suspend consumption parameter is no longer relevant.
CONTROL TIMING
Symbol
Parameter
Conditions
Value
Min
Typ.
Max
Unit
Frequency of Operation:
fOSC
external frequency
fCPU
internal frequency
internal frequency
tBU
tRL
tPORL
tPOWL
Startup Time Built-Up Time
Internal Power Reset Duration
Watchdog RESET
Output Pulse Width
tILIL
Interrupt Pulse Period
tDDR
fOSC=12MHz
Input pulse Width
Watchdog Time-out
8
fCPU = 8 MHz
8
20
ns
4096
tCPU
500
ns
49152
3145728
6
384
(1)
VDD min
ms
1000
Crystal Oscillator
Start-up Time
Power up rise time
MHz
4
Crystal Resonator
External RESET
tDOG
tOXOV
24
fOSC= 24MHz
1
tCPU
ms
tCPU
50
ms
100
ms
Note: : The minimum period tILIL should not be less than the number of cycle times it takes to execute the interrupt service
routine plus 21 cycles.
134/144
ST72774/ST727754/ST72734
AC/DC ELECTRICAL CHARACTERISTICS (Cont’d)
STANDARD I/O PORT PINS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOL
Output Low Level Voltage
Port A[7,2:0], Port B[7:4],
Port C[7:0], Port D[6:0]
Push Pull
IOL = -1.6mA VDD=5V
-
-
0.4
V
VOL
Output Low Level Voltage Port A[6:3]
Open Drain
IOL = -1.6mA VDD=5V
-
-
0.4
V
VOL
Output Low Level Voltage
Port A and Port C
IOL = -10mA VDD=5V
-
-
1.5
V
VOL
Output Low Level Voltage Port B[3:0]
Open Drain
IOL = -3mA VDD=5V
-
-
0.4
V
IOH = 1.6mA
VDD-0.8
-
-
V
VDD
V
Output High Level Voltage
VOH
Port A[7, 2:0], Port B[7:4],
Port C [7:0], Port D [6:0]
Push Pull
VIH
Input High Level Voltage Port A [7:0],
Port B [7:0], Port C [7:0], Port D[6:0],
RESET
Leading Edge
0.7xVDD
VIH
HSYNC,VSYNCI, CSYNCI, HFBACK,
VFBACK
VDD= 5V
2.0
VIL
HSYNC,VSYNCI, CSYNCI, HFBACK,
VFBACK
VDD= 5V
V
0.8
V
0.3xVDD
V
Input Low Voltage Port A [7:0],
VIL
Port B[7:0], Port C[7:0], Port D [6:0],
RESET
IIL
Port A [7:0], Port B[7:0], Port C[7:0],
Trailing Edge
VSS
I/O Ports Hi-Z Leakage Current
10
µA
Port D [6:0], RESET
COUT
CIN
Capacitance: Ports (as Input or
Output), RESET
IRPU
Pull-up resistor current
VDD=5V VIN=VSS T=25°C
12
pF
8
pF
280
µA
Note: Note: All voltages are referred to VSS unless otherwise specified.
POWER ON/OFF Electrical Specifications
Symbol
VTRH
VTRL
Parameter
Power ON/OFF Reset Trigger
VDD rising edge
Power ON/OFF Reset Trigger
VDD falling edge
Conditions
Min
Typ
Max
Unit
VDD Variation 50mV/mS
3.35
3.65
3.9
V
VDD Variation 50mV/mS
3.1
3.4
3.7
V
2.2
VTRM
VDD minimum for Power ON/OFF Reset
active
VDD Variation 50mV/mS
2.0
VTRHyst
Power ON/OFF LVD Hysteresis
VDD Variation 50mV/mS
250
V
mV
135/144
ST72774/ST727754/ST72734
AC/DC ELECTRICAL CHARACTERISTICS (Cont’d)
8-bit A/D Converter
Symbol
Parameter
fADC
Analog control frequency
|TUE|
Total unadjusted error
OE
Offset error
GE
Gain error
|DLE|
Differential linearity error
Conditions
-1
fCPU=8MHz, fADC=2MHz
VDD=5V
Integral linearity error
Conversion range voltage
IADC
A/D conversion supply current
tSTAB
Stabilization time after enable ADC
Sample capacitor loading time
tCONV
Conversion time
Internal input resistor
CSAMPLE
Sample capacitor
Unit
2
MHz
1
-1
1
LSB
0.5
0.5
tLOAD
External input resistor
Max
2
VAIN
RAIN
Typ
VDD=5V
|ILE|
RADC
Min
VSS
VDD
1
mA
1
fCPU=8MHz, fADC=2MHz
VDD=5V
V
µs
1
4
µs
1/fADC
2
8
µs
1/fADC
15
kΩ
1.5
kΩ
6
pF
PWM/BRM Electrical and Timings
Symbol
F
Parameter
Repetition rate
Conditions
Typ
Max
Unit
125
kHz
125
ns
5
mV
Res
Resolution
TCPU=125ns
s
Output step
VDD=5V, 10 bits
136/144
Min
TCPU =125ns
ST72774/ST727754/ST72734
AC/DC ELECTRICAL CHARACTERISTICS (Cont’d)
I2C/DDC-Bus Electrical specifications
Parameter
Symbol
Unit
VHYS
V
Standard mode I2C
Min
Fast mode I2C
Max
Min
Max
Hysteresis of Schmitt trigger inputs
Fixed input levels
VDD-related input levels
Pulse width of spikes which must be suppressed by the input filter
TSP
ns
TOF
ns
na
na
0.2
na
na
0,05 VDD
na
na
0 ns
50 ns
250
20+0.1C
b
250
Output fall time from VIH min to VIL max with
a bus capacitance from 10 pF to 400 pF
with up to 3 mA sink current at VOL1
with up to 6 mA sink current at VOL2
Input current each I/O pin with an input voltage
between 0.4V and 0.9 VDD max
I
µA
Capacitance for each I/O pin
C
pF
na
na
20+0.1C
b
250
- 10
10
-10
10
10
10
na = not applicable
Cb = capacitance of one bus in pF
I2C/DDC-Bus Timings
Parameter
Bus free time between a STOP and START condition
Standard I2C
Min
Fast I2C
Max
Min
Max
Symbol
Unit
4.7
1.3
TBUF
ms
4.0
0.6
THD:STA
µs
LOW period of the SCL clock
4.7
1.3
TLOW
µs
HIGH period of the SCL clock
4.0
0.6
THIGH
µs
Hold time START condition. After this period,
the first clock pulse is generated
Set-up time for a repeated START condition
4.7
0.6
Data hold time
0 (1)
0 (1)
Data set-up time
250
Rise time of both SDA and SCL signals
Set-up time for STOP condition
Capacitive load for each bus line
100
1000
Fall time of both SDA and SCL signals
0.9(2)
300
4.0
20+0.1Cb
300
20+0.1Cb
300
0.6
400
400
TSU:STA
µs
THD:DAT
ns
TSU:DAT
ns
TR
ns
TF
ns
TSU:STO
ns
Cb
pF
1)The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL
2)The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal
Cb = total capacitance of one bus line in pF
137/144
ST72774/ST727754/ST72734
USB DC Electrical Characteristics
Parameter
Symbol
Conditions
Min.
Max.
Unit
Inputs Levels:
Differential Input Sensitivity
VDI
AbsI((D+) - (D-))
0.2
Differential Common Mode Range
VCM
Includes VDI range
0.8
2.5
V
V
Single Ended Receiver Threshold
VSE
0.8
2.0
V
0.3
V
Output Levels
Static Output Low
VOL
RL of 1.5K ohms to
3.6V
Static Output High
VOH
RL of 15K ohms to
USBGND
2.8
3.6
V
USBVCC: voltage level
USBV
VDD=5V
3
3.6
V
Notes:
– RL is the load connected on the USB drivers.
– All the voltages are measured from the local ground potential (USBGND).
Figure 78. USB: Data signal Rise and fall time
Differential
Datas Lines
Crossover
points
VCRS
USBGND
tr
tf
USB: Low speed electrical characteristics
Parameter
Symbol
Conditions
Min
Note 1, CL=50 pF
75
Max
Unit
Driver characteristics:
Rise time
tr
Note 1, CL=600 pF
Fall Time
tf
Note 1, CL=50 pF
75
Note 1, CL=600 pF
Rise/ Fall Time matching
trfm
Output signal Crossover
Voltage
VCRS
Note1: Measured from 10% to 90% of the data signal
138/144
tr/tf
ns
300
ns
ns
300
ns
80
120
%
1.3
2.0
V
ST72774/ST727754/ST72734
7 GENERAL INFORMATION
7.1 PACKAGE MECHANICAL DATA
Figure 79. 42-Pin Shrink Plastic Dual In-Line Package, 600-mil Width
Dim.
mm
Min
Typ
A
Min
Typ
5.08
Max
0.200
A1
0.51
0.020
A2
3.05
3.81 4.57 0.120 0.150 0.180
b
0.46 0.56
0.018 0.022
b2
1.02 1.14
0.040 0.045
C
0.23
0.25 0.38 0.009 0.010 0.015
D
36.58 36.83 37.08 1.440 1.450 1.460
E
15.24
E1
12.70 13.72 14.48 0.500 0.540 0.570
16.00 0.600
0.630
e
1.78
0.070
eA
15.24
0.600
eB
PDIP42S
inches
Max
eC
0.00
L
2.54
18.54
0.730
1.52 0.000
0.060
3.30 3.56 0.100 0.130 0.140
Number of Pins
N
42
Figure 80. 42-Pin Shrink Ceramic Dual In-Line Package, 600-mil Width
Dim.
mm
Min
Typ
A
Min
Typ
4.01
Max
0.158
A1
0.76
0.030
B
0.38
0.46 0.56 0.015 0.018 0.022
B1
0.76
0.89 1.02 0.030 0.035 0.040
C
0.23
0.25 0.38 0.009 0.010 0.015
D
36.68 37.34 38.00 1.444 1.470 1.496
D1
E1
35.56
1.400
14.48 14.99 15.49 0.570 0.590 0.610
e
1.78
0.070
G
14.12 14.38 14.63 0.556 0.566 0.576
G1
18.69 18.95 19.20 0.736 0.746 0.756
G2
CDIP42SW
inches
Max
1.14
0.045
G3
11.05 11.30 11.56 0.435 0.445 0.455
G4
15.11 15.37 15.62 0.595 0.605 0.615
L
S
2.92
5.08 0.115
0.89
0.200
0.035
Number of Pins
N
42
139/144
8
ST72774/ST727754/ST72734
Figure 81. 44-Pin Thin Quad Flat Package
0.10mm
.004
seating plane
Dim
mm
Min
Typ
A
b
c
Typ
0.063
0.15 0.002
0.006
0.05
1.35 1.40 1.45 0.053 0.055 0.057
b
0.30 0.37 0.45 0.012 0.015 0.018
c
0.09
0.20 0.004
0.008
D
12.00
0.472
D1
10.00
0.394
D3
8.00
0.315
E
12.00
0.472
E1
10.00
0.394
E3
8.00
0.315
e
0.80
L
0°
3.5°
0.031
7°
0.45 0.60 0.75 0.018 0.024 0.030
1.00
0.039
Number of Pins
K
140/144
Max
1.60
A2
L1
L
Min
A1
K
L1
inches
Max
N
44
ST72774/ST727754/ST72734
8 ORDERING INFORMATION
The following section deals with the procedure for
transfer of customer codes to STMicroelectronics.
unused bytes must be set to 9Dh (opcode for
NOP).
8.1 Transfer of Customer Code
The selected mask options are communicated to
STMicroelectronics using the correctly completed
OPTION LIST appended.
Customer code is made up of the ROM contents
and the list of the selected mask options (if any).
The ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file in .S19
format generated by the development tool. All
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on
contractual points.
Figure 82. Sales Type Coding Rules
Family
Version Code
Subfamily (with x=subset index)
Number of pins
ROM size
Package
Temperature Range
ROM Code (three letters)
ST72
T
7x4 J 7 B 1 / xxx
0 = 25° C
B = Plastic DIP
9 = 60K
J = 42 pins
No letter = ROM
1 = Standard (0 to +70°C)
D = Ceramic DIP
7 = 48K
S = 44 pins
E = EPROM
T = Plastic QFP
6 = 32K
T = OTP
Table 35. Development Tools
Development Tool
Sales Type
Real time Emulator
ST727x4-EMU2B
EPROM Programmer Board
ST727x4-EPB/xx1
Remarks
220V Power Supply EU
110V Power Supply US
ST72E774-GP/D42
DIL42
ST72E774-GP/Q44
PQFP44
1
xx stands for the power supply code assigned by ST Microelectronics: EU=220V; US=110V
Gang Programmer
141/144
ST72774/ST727754/ST72734
Table 36. Ordering Information
Sales Type
ROM/EPROM (bytes)
RAM
(bytes)
TMU
USB
Package
ST72X774 (1)
ST72E774J9D0
60K EPROM
ST72T774J9B1
60K OTP
ST72774J9B1/xxx
60K ROM
ST72774J7B1/xxx
48K ROM
ST72774S7T1/xxx
48K ROM
ST72T774S9T1
60K OTP
ST72774S9T1/xxx
60K ROM
CSDIP42
PSDIP42
1K
Yes
Yes
TQFP44
ST72X754 (1)
ST72E754J9D0
60K EPROM
ST72T754J9B1
60K OTP
ST72754J9B1/xxx
60K ROM
ST72754J7B1/xxx
48K ROM
ST72T754S9T1
60K OTP
ST72754S9T1
60K ROM
ST72754S7T1/xxx
48K ROM
CSDIP42
PSDIP42
1K
Yes
No
TQFP44
ST72X734 (2)
ST72E734J6D0
32K EPROM
ST72T734J6B1/xxx
32K OTP
ST72734J6B1/xxx
32K ROM
CSDIP42
512
No
No
PSDIP42
(1) 8 bit ±2 LSB A/D converter
(2) 8 bit ±4 LSB A/D converter
142/144
ST72774/ST727754/ST72734
STMicroelectronics OPTION LIST
ST727x4 MICROCONTROLLER FAMILY
Customer:
Address:
.............................
.............................
.............................
Contact:
.............................
Phone No: . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference/ROM Code* : . . . . . . . . . . . . . . . . . . .
*The ROM code name assigned by ST.
STMicroelectronics reference:
Device (SDIP42):
Device (TQFP44):
Device (CSDIP42):
Software Development:
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
ST72774J9B1 (60K ROM)
ST72774J7B1 (48K ROM)
ST72754J9B1 (60K ROM)
ST72754J7B1 (48K ROM)
ST72734J6B1 (32K ROM)
ST72774S9T1 (60K ROM)
ST72774S7T1 (48K ROM)
ST72754S9T1 (60K ROM)
ST72754S7T1 (48K ROM)
ST72E774J9D0 (60K EPROM)
ST72E754J9D0 (60K EPROM)
ST72E734J6D0 (32K EPROM)
STMicroelectronics
Customer
External laboratory
Special Marking:
[ ] No
[ ] Yes "_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _"
For marking, one line is possible with maximum 16 characters for SDIP42 and 10 characters for
TQFP44.
Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only.
Mask Options:
None.
We have checked the ROM code verification file returned to us by STMicroelectronics. It conforms exactly
with the ROM code file orginally supplied. We therefore authorize STMicroelectronics to proceed with
device manufacture.
Signature
Date
.............................
.............................
143/144
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2003 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
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9