ST8004 SMARTCARD INTERFACE ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 3 OR 5 V SUPPLY FOR THE IC STEP-UP CONVERTER FOR VCC GENERATION 3 SPECIFIC PROTECTED HALF DUPLEX BI-DIRECTIONAL BUFFERED I/O LINES AUTOMATIC ACTIVATION AND DEACTIVATION SEQUENCES THERMAL AND SHORT-CIRCUIT PROTECTIONS ON ALL CARD CONTACTS 26 MHz INTEGRATED CRYSTAL OSCILLATOR CLOCK GENERATION FOR THE CARD UP TO 20MHz WITH SYNCHRONOUS FREQUENCY CHANGES ISO7816-3 COMPATIBLE ENHANCED ESD PROTECTION ON CARD SIDE SO-28 PACKAGE UNDER VOLTAGE LOCKOUT PROTECTION SELECTABLE TO 3V OR 2.2V SUPPLY SUPERVISOR INTEGRATED SOP DESCRIPTION The ST8004 is a complete low cost analog interface for asynchronous 3V and 5V smart cards. It can be placed between the card and the microcontroller with few external components to perform all supply protection and control functions. Main applications are: smartcard readers for Set Top Box, IC card readers for banking, identification. ORDERING CODES Type Temperature Range Package Comments ST8004CD ST8004CDR 0 to 85 °C 0 to 85 °C SO-28 (Tube) SO-28 (Tape & Reel) 27 parts per tube / 12 tube per box 1000 parts per reel March 2004 1/19 ST8004 BLOCK DIAGRAM 2/19 ST8004 PIN CONFIGURATION PIN DESCRIPTION PlN N° SYMBOL 1 2 CLKDIV1 CLKDIV2 NAME AND FUNCTION 3 5V/3V Control of CLK Frequency Control of CLK Frequency VCC selection pin. 4 5 PGND C1+ VDDP Power Ground for Step-Up converter External Cap. for Step-Up converter Power Supply for Step-Up converter 6 7 8 9 10 C1VUP PRES PRES 11 I/O 12 AUX2 External Cap. Step-Up converter Output of Step-Up converter Card Presence Input (Active Low) Card Presence Input (Active High) Data Line to and from card (C7) (internal 10kΩ pull-up resistor connected to VCC) 13 AUX1 Auxiliary line to and from card (C8) (internal 10kΩ pull-up resistor connected to VCC) Auxiliary line to and from card (C4) (internal 10kΩ pull-up resistor connected to VCC) 14 15 16 17 CGND CLK RST VCC Ground for card signal (C5) Clock to card (C3) Card Reset (C2) Supply Voltage for the card (C1) 18 VTHSEL Deactivation threshold selector pin (under voltage lock-out) 19 CMDVCC 20 21 RSTIN VDD Card Reset Input from MCU Supply Voltage 22 23 24 25 GND OFF XTAL1 XTAL2 26 I/OUC Start activation sequence input (Active Low) 27 AUX1UC Ground Interrupt to MCU (active Low) Crystal or external clock input Crystal connection (leave this pin open if external clock is used) Data Line to and from MCU (internal 10kΩ pull-up resistor connected to VDD) Auxiliary line to and from MCU (internal 10kΩ pull-up resistor connected to VDD) 28 AUX2UC Auxiliary line to and from MCU (internal 10kΩ pull-up resistor connected to VDD) 3/19 ST8004 ABSOLUTE MAXIMUM RATINGS Symbol Parameter VDD, VDDP Supply Voltage Vn2 Voltage on pins XTAL1, XTAL2, 5V/3V, RSTIN, AUX2UC, AUX1UC, I/OUC, CLKDIV1, CLKDIV2, VTHSEL, CMDVCC, PRES, PRES and OFF Voltage on card contact pins I/O, RST, AUX1, AUX2 and CLK Vn3 Voltage on pins VUP, S1 and S2 Vn1 MIL-STD-883 class 3 on card contact pins, PRES and PRES (Note 1, 2) MIL-STD-883 class 2 on µC contact pins and RSTIN (Note 1, 2) ESD1 ESD2 Min Max Unit -0.3 7 V -0.3 VDD + 0.3 V -0.3 VCC + 0.3 V 9 V -6 6 KV -2 2 KV Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Note 1: All card contacts are protected against any short with any other card contact. Note 2: Method 3015 (HBM, 1500 Ω, 100 pF) 3 positive pulses and 3 negative pulses on each pin referenced to ground. THERMAL DATA Symbol Rthj-amb Parameter Thermal Resistance Junction-ambient Temperature Condition Value Unit In free air 70 °K/W RECOMMENDED OPERATING CONDITIONS Symbol TA Parameter Test Conditions Min. Temperature Range Typ. -25 Max. Unit 85 °C ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) Symbol Parameter VDD Supply Voltage VDDP Supply Voltage for the voltage doubler VO(VUP) VI(VUP) IDD IP Vth3 Threshold Voltage on VDD VHYS(th2) Hysteresis on Vth2 VHYS(th3) Hysteresis on Vth3 4/19 VTHSEL = VDD or floating VTHSEL = GND VTHSEL = VDD or floating VTHSEL = GND Pulse width of the internal Alarm pulse Delay of Internal filter VTHSEL = GND Typ. 2.7 3.150 To comply with VI(RIPPLE)(P-P) specifications Supply Current for Step-Up Inactive mode converter Active mode; fCLK = fXTAL; CL = 30pF Threshold Voltage on VDD ∆THFIL Min. Output Voltage on pin VUP from step-up converter Input Voltage to be applied on VUP in order to block the step-up converter Supply Current Inactive mode Active mode; fCLK = fXTAL; CL = 30pF Vth2 tW Test Conditions VTHSEL = VDD or floating VTHSEL = GND 4.5 4.75 Max. Unit 6.5 V 6.5 5 6.5 5.25 5.5 7 ICC = 0 ICC = 65 mA V V 9 V 1.2 1.5 mA 0.1 18 mA 150 2.2 2.4 2.95 3.05 V 50 150 mV 0 V mV 6 20 ms 5 50 µs ST8004 CARD SUPPLY VOLTAGE CHARACTERISTICS (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) (Note 1) Symbol VCC Parameter Output Voltage including ripple Test Conditions SR Typ. Max. Unit V Inactive Mode Inactive Mode; ICC = 1 mA -0.1 -0.1 0.1 0.4 Active Mode; VDDP = 5V ± 5% 5 V card |ICC| < 65 mA DC 3 V card 4.75 2.85 5.25 3.15 Active Mode; single current pulse of 100 mA; 2 µs 4.65 2.85 4.65 2.76 5.25 3.15 5.25 3.15 Active Mode; current pulse of 40 nAs with |ICC|<200mA t < 400 ns VI(RIPPLE) Peak to Peak ripple voltage 20 KHz to 200 MHz on VCC VDDP = 5V ± 5% (P-P) |ICC| Min. Output Current From 0 to 5V or to 3V VCC short circuit to GND Slew Rate Up to down 5V 3V 5V 3V card card card card 0.11 350 mV 65 150 mA 0.22 V/µs CRYSTAL CONNECTION (PINS XTAL1 AND XTAL2) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) Symbol Parameter CEXT External capacitors on pins XTAIL1, XTAIL2 Crystal Input Frequency fI(XTAL) Test Conditions Min. Typ. Max. Unit 15 pF 2 26 MHz 0.7 VDD VDD V 0 0.3 VDD V Depending on specification of crystal or resonator used VIH(XTAL) High level input voltage on XTAIL1 VIL(XTAL) Low level input voltage on XTAIL1 DATA LINES (PINS I/O, AUX1, AUX2, AUX1UC AND AUX2UC) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) Symbol Parameter tD(EDGE) Delay between falling edge on pin I/O and I/OUC and width of active pull-up pulse fI/O(MAX) Maximum frequency of data lines CI Input capacitance on data lines Test Conditions Min. Typ. Max. 200 Unit ns 1 MHz 10 pF 5/19 ST8004 DATA LINES (PINS I/O, AUX1 AND AUX2 WITH 10 kΩ PULL-UP RESISTOR CONNECTED TO VCC INTERNALLY (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) Symbol VOH Parameter Test Conditions High Level Output Voltage on IOH = - 40µA data lines No Load Low Level Output Voltage on IOL = 1 mA data lines VIH High Level Input Voltage on data lines VIL Low Level Input Voltage on data lines VINACTIVE Voltage on data lines when No Load inactive II/O = 1 mA Min. Typ. Max. Unit 0.75 VCC VCC V 0.9 VCC VCC+0.3 300 mV 1.8 VCC V -0.3 0.8 V 0.1 0.3 V VOL IEDGE |IIH| IIL RPU(INT) Current from data lines when VOH = 0.7 x VCC; CO = 80 pF active pull-up is active Input Leakage Current when VIH = VCC high Low Level Input Current VIL = 0 -1 Internal pull-up resistance to VCC 9 tT(DI) Input transition times tT(DO) Output transition times CI mA 10 From VIL max to VIH min CO = 80 pF, no DC load; 0.4 V to 70% from 0 to VCC Input capacitance µA 600 µA 13 KΩ 1 µs 0.1 µs 10 pF DATA LINES (PINS I/OUC, AUX1UC AND AUX2UC WITH 10 kΩ PULL-UP RESISTOR CONNECTED TO VDD INTERNALLY (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD V 300 mV VOH High Level Output Voltage VOL Low Level Output Voltage VIH High Level Input Voltage 0.7 VDD VDD V VIL Low Level Input Voltage 0 0.3 VDD V 10 µA 600 µA 13 KΩ |ILIH| IIL RPU(INT) IOH = - 40µA 0.75 VDD No Load 0.9 VDD IOL = 1 mA Input Leakage Current when VIH = VDD high Input Leakage Current when VIL = 0 low Internal pull-up resistance to VDD tT(DI) Input transition times From VIL max to VIH min tT(DO) Output transition times CO = 30 pF, no DC load; 10% to 90% from 0 to VDD CI 6/19 Input capacitance 0 9 11 1 µs 0.1 µs 10 pF ST8004 INTERNAL OSCILLATOR (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) Symbol Parameter Test Conditions Min. fOSC(INT) Frequency of internal oscillator Typ. 2.2 Max. Unit 3.2 MHz RESET OUTPUT TO THE CARD (PIN RST) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) Symbol Parameter VO(INACTIVE) Output Voltage in Inactive Mode tD(RSTIN-RST) Delay between pins RSTN and RST VOL Low Level Output Voltage Test Conditions Min. Typ. Max. Unit IO = 1 mA 0 0.3 V No Load RST Enable 0 0.1 2 µs IOL = 200 µA 0 0.2 V VOH High Level Output Voltage IOH = -200 µA 0.9 VCC VCC V tR, tF Rise and fall time (10% to 90% of VCC) CO = 250 pF 0.1 µs CLOCK OUTPUT TO THE CARD (PIN CLK) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) Symbol Parameter VO(INACTIVE) Output Voltage in Inactive Mode Test Conditions Min. Typ. Max. Unit IO = 1 mA 0 0.3 V VOL Low Level Output Voltage No Load IOL = 200 µA 0 0 0.1 0.3 V VOH High Level Output Voltage IOH = -200 µA 0.9 VCC VCC V tR, tF Rise and fall time (10% to 90% of VCC) CO = 35 pF (Note 2) 8 ns Duty cycle factor (except for fXTALS) (See Note 4) CO = 35 pF (Note 2) 55 % δ SR Slew Rate (rise and fall edge) CO = 35 pF 45 0.2 V/ns LOGIC INPUTS (PINS CLKDIV1, CLKDIV2, PRES, PRES, CMDVCC, RSTIN AND 5V/3V, VTHSEL (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) (Note 3) Symbol Parameter Test Conditions Min. Typ. Max. Unit VIL Low Level Input Voltage 0 0.3 VDD V VIH High Level Input Voltage 0.7 VDD VDD V |ILIH| Input Leakage Current when VIL = 0 to VDD high Input Leakage Current when VIH = 0 to VDD low 5 µA 5 µA |ILIL| 7/19 ST8004 OFF OUTPUTS (PIN OFF IS AN OPEN DRAIN WITH AN INTERNAL 20 kΩ PULL-UP RESISTOR TO VDD); (see note 5) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) Symbol Parameter Test Conditions VOL Low Level Output Voltage IOL = 2 mA VOH High Level Output Voltage IOH = -15 µA Min. Typ. Max. Unit 0.4 V 0.75 VDD V PROTECTION (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) Symbol TSD ICC(SD) Parameter Test Conditions Min. Shut down temperature Typ. Max. 135 Shut down current at VCC Unit °C 150 mA TIMING (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) Symbol Parameter Test Conditions tACT Activation sequence duration (See Fig. 3) tDE Deactivation sequence duration Start of the windows to send CLK to card End of the windows to send CLK to card t3 t5 (See Fig. 4) Min. 60 (See Fig. 3) (See Fig. 3) 140 Typ. Max. Unit 180 220 µs 80 100 µs 130 µs µs Note 1: To meet these specifications VCC should be decoupled to CGND using two ceramic multiplier capacitors of low ESR with values of 100nF. Note 2: The transition time and duty cycle factor are shown in figure 7; d = t1/(t1+t2). Note 3: PRES and CMDVCC are active Low; RSTIN and PRES are active High Note 4: Referred to the paragraph "CLOCK CIRCUITRY" Note 5: See paragraph "FAULT DETECTION". Figure 1 : Alarm as a function of VDD (tW = 10 ms), VTHSEL = VDD or floating 8/19 ST8004 Figure 2 : Alarm as a function of VDD (tW = 10 ms), VTHSEL = GND Figure 3 : Activation sequence 9/19 ST8004 Figure 4 : Deactivation sequence Figure 5 : Behavior of OFF, CMDVCC, PRES and VCC 10/19 ST8004 Figure 6 : Emergency deactivation sequence Figure 7 : Definition of output transition times FUNCTIONAL DESCRIPTION Throughout this document it is assumed that the reader is familiar with iso7816 norm terminology POWER SUPPLY The supply pins for the IC are VDD and GND. VDD should be in the range of 2.7 to 6.5 V. All interface signals with the microcontroller are referenced to VDD; therefore be sure the supply voltage of the microcontroller is also at VDD. All card contacts remain inactive during powering up or powering down. The sequencer is not activated until VDD reaches Vth2 +Vhys(th2) or Vth3 + Vhys(th3) when VTHSEL = GND. When VDD falls below Vth2 or Vth3, an automatic deactivation of the contacts is performed. To generate a 5 V ±5% VCC supply to the card, an integrated voltage doubler is incorporated. This step-up converter should be separately supplied by VDDP and PGND (from 4.5 to 6.5 V). In order to satisfy the VI(RIPPLE)(P-P) specifications, VDDP should be from 4.75V to 5.25V. Due to large transient currents, the 2x100 nF capacitors of the step-up converter should have an ESR of less than 100 mΩ, and be located as near as possible to the IC. The supply voltages VDD and VDDP may be applied to the IC in any time sequence. To get the correct deactivation of the card VDDP is allowed to turn-off only when VDD is below the undervoltage threshold. If a voltage between 7 and 9 V is available within the application, this voltage may 11/19 ST8004 be tied to pin VUP, thus blocking the step-up converter. In this case, VDDP must be tied to VDD and the capacitor between pins S1 and S2 may be omitted. VOLTAGE SUPERVISOR (FOR VTHSEL = VDD OR FLOATING) This block surveys the VDD supply. A defined reset pulse of approximately 10 ms (tW) is used internally for maintaining the IC in the inactive mode during powering up or powering down of VDD (see Fig.1). As long as VDD is less than Vth2 +Vhys(th2), the IC will remain inactive whatever the levels on the command lines. This also lasts for the duration of tW after VDD has reached a level higher than Vth2 +Vhys(th2).The system controller should not attempt to start an activation sequence during this time. When VDD falls below Vth2, a deactivation sequence of the contacts is performed. VOLTAGE SUPERVISOR (FOR VTHSEL = GND) This block surveys the VDD supply. A defined reset pulse of approximately 10 ms (tW) is used internally for maintaining the IC in the inactive mode during powering up or powering down of VDD (see Fig.2). If VDD is less than Vth3 during a time, longer than ∆THFIL (max 150µs), the IC will remain inactive whatever the levels on the command lines. The IC remain inactive also for the duration of tw after VDD has reached a level higher than Vth3. The system controller should not attempt to start an activation sequence during this time. When VDD falls below Vth3 during time more than ∆THFIL, a deactivation sequence of the contacts is performed. CLOCK CIRCUITRY The clock signal (CLK) to the card is either derived from a clock signal input on the pin XTAL1 or from a crystal up to 26 MHz connected between pins XTAL1 and XTAL2. The frequency may be chosen at fXTAL,1/2 fXTAL,1/4 fXTAL or 1/8 fXTAL via pins CLKDIV1 and CLKDIV2 (see Table 1). The frequency change is synchronous, which means that during transition, no pulse is shorter than 45% of the smallest period and that the first and last clock pulse around the change has the correct width. In the case of fXTAL, the duty factors depend on the signal at XTAL1. In order to reach a 45% to 55% duty factor on the pin CLK the input signal on XTAL1 should have a duty factor of 48% to 52% and transition times of less than 5% of the input signal period.If a crystal is used with fXTAL, the duty factor on pin CLK may be 45% to 55% depending on the layout and on the crystal characteristics and frequency. In the other cases, it is guaranteed between 45% and 55% of the period. The crystal oscillator runs as soon as the IC is powered-up. If the crystal oscillator is used, or if the clock pulse on XTAL1 is permanent, then the clock pulse will be applied to the card according to the timing diagram of the activation sequence. If the signal applied to XTAL1 is controlled by the micro-controller, then the clock pulse will be applied to the card by the microcontroller after completion of the activation sequence. TABLE 1 CLKDIV1 CLKDIV2 CLK 0 0 1/8 fXTAL 0 1 1/4 fXTAL 1 1 1/2 fXTAL 1 0 fXTAL I/O CIRCUITRY The three data lines I/O, AUX1 and AUX2 are identical. The Idle state is realized by data lines I/O and I/ OUC being pulled HIGH via a 10k resistor (I/O to VCC and I/OUC to VDD ). I/O is referenced to VCC, and I/OUC to VDD, thus allowing operation with VCC ≠ VDD. The first line on which a falling edge occurs becomes the master. An anti-latch circuit disables the detection of falling edges on the other line, which then becomes the slave. After a time delay td (edge) (approximately 200 ns), the N transistor on the slave line is turned on, thus transmitting the logic 0 present on the master line.When the master line returns to logic 1, the P transistor on the slave line is turned on during the time delay td (edge) and then both lines return to their idle state. This active pull-up feature ensures fast LOW-to-HIGH transitions; it is able to deliver more than 1 mA up to an output voltage of 0.9 VCC on a 80pF load. At the end of the active pull-up 12/19 ST8004 pulse, the output voltage only depends on the internal pull-up resistor, and on the load current. The maximum frequency on these lines is 1MHz. INACTIVE STATE After power-on reset, the circuit enters the inactive state. A minimum number of circuits are active while waiting for the microcontroller to start a session. • All card contacts are inactive (approximately 200Ω to GND); I/OUC, AUX1UC and AUX2UC are high impedance (10 kΩ pull-up resistor connected to VDD) • Voltage generators are stopped • XTAL oscillator is running • Voltage supervisor is active. ACTIVATION SEQUENCE After power-on and, after the internal pulse width delay, the microcontroller may check the presence of the card with the signal OFF (OFF = HIGH while CMDVCC is High means that the card is present; OFF = LOW while CMDVCC is HIGH means that no card is present). If the card is in the reader (which is the case if PRES or PRES is true), the microcontroller may start a card session by pulling CMDVCC LOW. The following sequence then occurs (see Fig.3): • CMDVCC is pulled LOW (t0) • The voltage doubler is started (t1~t0) • VCC rises from 0 to 5 or 3V with a controlled slope (t2 = t1 +½3T)(I/O, AUX1 and AUX2 follow VCC with a slight delay); T is 64 times the period of the internal oscillator, approximately 25µs • I/O, AUX1 and AUX2 are enabled (t3 = t1 +4T) • CLK is applied to the C3 contact (t4) • RST is enabled (t5 = t1 +7T). The clock may be applied to the card in the following way: set RSTIN High before setting CMDVCC Low, and reset it Low between t3 and t5; CLK will start at this moment. RST will remain LOW until t5, where RST is enabled to be the copy of RSTIN. After t5, RSTIN has no further action on CLK. This is to allow a precise count of CLK pulses before toggling RST. If this feature is not needed, then CMDVCC may be set LOW with RSTIN Low. In this case, CLK will start at t3, and after t5, RSTIN may be set High in order to get the Answer To Request (ATR) from the card. ACTIVE STATE When the activation sequence is completed, the ST8004 will be in the active state. Data are exchanged between the card and the microcontroller via the I/O lines. The ST8004 is designed for cards without VPP (this is the voltage required to program or erase the internal non-volatile memory). Depending on the layout and on the application test conditions (for example with an additional 1pF cross capacitance between C2/C3 and C2/C7) it is possible that C2 is polluted with high frequency noise from C3. In this case, it will be necessary to connect a 220pF capacitor between C2 and CGND. It is recommended to: 1. Keep track C3 as far as possible from other tracks 2. Have straight connection between CGND and C5 (the 2 capacitors on C1 should be connected to this ground track) 3. Avoid ground loops between CGND,PGND and GND 4. Decoupled VDDP and VDD separately; if the 2 supplies are the same in the application, then they should be connected in star on the main track. With all these layout precautions, noise should be at an acceptable level, and jitter on C3 should be less than 100ps. DEACTIVATION SEQUENCE When a session is completed, the microcontroller sets the CMDVCC line to the HIGH state. The circuit then executes an automatic deactivation sequence by counting the sequencer back and ends in the inactive state (see Fig.4): • RST goes LOW → (t11 = t10) • CLK is stopped LOW → (t12 = t11 +½T) where T is approximately 25 µs • I/O, AUX1 and AUX2 are output into high-impedance state → (t13 = t11 +T)(10 kΩ pull-up resistor connected to VCC) 13/19 ST8004 • VCC falls to zero → (t14 = t11 +½3T); the deactivation sequence is completed when VCC reaches its inactive state • VUP falls to zero → (t15 = t11 +5T) and all card contacts become low-impedance to GND; • I/OUC, AUX1UC and AUX2UC remain pulled up to VDD via a 10 kΩ resistor. FAULT DETECTION The following fault conditions are monitored by the circuit: Short-circuit or high current on VCC Removing card during transaction VDD dropping Overheating. There are two different cases (Fig. 5) 1. CMDVCC HIGH: (outside a card session) then, OFF is LOW if the card is not in the reader, and HIGH if the card is in the reader. A supply voltage drop on VDD is detected by the supply supervisor, which generates an internal power-on reset pulse, but does not act upon OFF. The card is not powered-up, so no short-circuit or overheating is detected. 2. CMDVCC LOW: (within a card session) then, OFF falls LOW if the card is extracted, or if a short-circuit has occurred on VCC, or if the temperature on the IC has become too high. As soon as the fault is detected, an emergency deactivation is automatically performed (see Fig.6). When the system controller sets CMDVCC back to HIGH, it may sense OFF again in order to distinguish between a hardware problem or a card extraction. If a supply voltage drop on VDD is detected while the card is activated, then an emergency deactivation will be performed and OFF goes LOW. When OFF level falls low, the system controller must wait not less than 160µs before setting high again the CMDVCC command. Depending on the type of card presence switch within the connector (normally closed or normal open), and on the mechanical characteristics of the switch, a bouncing may occur on presence signals at card insertion or withdrawal. There is no debounce feature in the device, so the software has to take it into account; however, the detection of card take off during active phase, which initiates an automatic deactivation sequence is done on the first True/False transition on PRES or PRES, and is memorized until the system controller sets CMDVCC High. So, the software may take some time waiting for presence switches to be stabilized without causing any delay on the necessary fast and normalized deactivation sequence. 14/19 ST8004 ST8004 SEQUENCER 15/19 ST8004 CARD CONTROL SEQUENCER CARD CONTROL nS n Se tio que iva nce CM act De DV OFF = PRES or (not PRES_NEG) ctiv atio nS equ enc e Dea Ac tiv LOCK_OFF_HIGH LOCK_OFF_LOW OFF=1 OFF=0 CMDVCC=0 OFF_temp = 0 OFF_temp = PRES or (not PRES_NEG) ce en atio u eq d an er ad low re he lled n t pu ’t i is isn CC V rd Ca CMD CMDVCC=0 OFF_temp = 0 CMDVCC=0 OFF_temp = 1 Removing Card after the Activation Sequence 16/19 =1 CC DV CM CC =1 CHANGE_OFF ST8004 SO-28 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. 2.65 MAX. 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 C 0.5 0.020 c1 45˚ (typ.) D 17.70 18.10 0.697 0.713 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 16.51 0.650 F 7.40 7.60 0.291 0.300 L 0.50 1.27 0.020 0.050 S 8 ˚ (max.) 0016023 17/19 ST8004 Tape & Reel SO-28 MECHANICAL DATA mm. inch DIM. MIN. A MAX. MIN. 330 13.2 TYP. MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 18/19 TYP 0.504 30.4 0.519 1.197 Ao 10.8 11.0 0.425 0.433 Bo 18.2 18.4 0.716 0.724 Ko 2.9 3.1 0.114 0.122 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 ST8004 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 19/19