ST92R195B
ROMLESS HCMOS MCU WITH
ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER
DATA BRIEFING
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Register File based 8/16 bit Core Architecture
with RUN, WFI, SLOW and HALT modes
0°C to +70°C Operating Temperature Range
available
Up to 24 MHz Operation @ 5V±10%
Minimum instruction cycle time: 375ns at
16 MHz internal clock
4 Mbytes address space
256 Bytes RAM of Register file (accumulators or
index registers)
1024 Bytes of on-chip static RAM
8K Bytes of TDSRAM (Teletext and Display
Storage RAM)
80-lead QFP package
23 fully programmable I/O pins
Serial Peripheral Interface
Flexible Clock controller for OSD, Data Slicer
and Core clocks running from one single low
frequency external crystal.
Enhanced Display Controller with 26 rows of
40/80 characters
– Serial and Parallel attributes
– 10x10 dot Matrix, 512 ROM characters, definable by user
– 4/3 and 16/9 supported in 50/60Hz and 100/
120 Hz mode
– Rounding, fringe, double width, double height,
scrolling, cursor, full background color, halfintensity color, translucency and half-tone
modes
Teletext unit, including Data slicer, Acquisition
Unit and 8 Kbytes TDSRAM for Data Storage
VPS and Wide Screen Signalling slicer
Integrated Sync Extractor and Sync Controller
14-bit Voltage Synthesis for tuning reference
voltage
Up to 8 External Interrupts plus 1 non-maskable
interrupt
QFP80
8 x 8-bit programmable PWM outputs with 5V
open-drain or push-pull capability
■ 16-bit Watchdog timer with 8-bit prescaler
■ One 16-bit standard timer with 8-bit prescaler
■ 4-channel
Analog-to-Digital converter; 5-bit
guaranteed
■ Rich instruction set and 14-Addressing modes
Versatile Development Tools, including Assembler, Linker, C-compiler, Archiver, Source Level
Debugger and Hardware Emulators with RealTime Operating System available from third parties
■
Device Summary
Device
Program
Memory
ST92R195B9
ROMLESS
TDS VPS/
RAM WSS
8K
Yes
Package
PQFP80
Rev. 2.2
January 2000
1/18
1
ST92R195B - GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST92R195B microcontroller is developed and
manufactured by STMicroelectronics using a proprietary n-well HCMOS process. Its performance
derives from the use of a flexible 256-register programming model for ultra-fast context switching
and real-time event response. The intelligent onchip peripherals offload the ST9 core from I/O and
data management processing tasks allowing critical application tasks to get the maximum use of
core resources. The ST92R195B MCU supports
low power consumption and low voltage operation
for power-efficient and low-cost embedded systems.
1.1.1 ST9+ Core
The advanced Core consists of the Central
Processing Unit (CPU), the Register File and the
Interrupt controller.
The general-purpose registers can be used as accumulators, index registers, or address pointers.
Adjacent register pairs make up 16-bit registers for
addressing or 16-bit processing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, loads/stores, and memory/register and memory/memory exchanges.
Two basic addressable spaces are available: the
Memory space and the Register File, which includes the control and status registers of the onchip peripherals.
1.1.2 Power Saving Modes
To optimize performance versus power consumption, a range of operating modes can be dynamically selected.
Run Mode. This is the full speed execution mode
with CPU and peripherals running at the maximum
clock speed delivered by the Phase Locked Loop
(PLL) of the Clock Control Unit (CCU).
Wait For Interrupt Mode. The Wait For Interrupt
(WFI) instruction suspends program execution until an interrupt request is acknowledged. During
WFI, the CPU clock is halted while the peripheral
and interrupt controller keep running at a frequen-
2/18
cy programmable via the CCU. In this mode, the
power consumption of the device can be reduced
by more than 95% (LP WFI).
Halt Mode. When executing the HALT instruction,
and if the Watchdog is not enabled, the CPU and
its peripherals stop operating and the status of the
machine remains frozen (the clock is also
stopped). A reset is necessary to exit from Halt
mode.
1.1.3 I/O Ports
Up to 23 I/O lines are dedicated to digital Input/
Output. These lines are grouped into up to five I/O
Ports and can be configured on a bit basis under
software control to provide timing, status signals,
timer and output, analog inputs, external interrupts
and serial or parallel I/O.
1.1.4 TV Peripherals
A set of on-chip peripherals form a complete system for TV set and VCR applications:
– Voltage Synthesis
– VPS/WSS Slicer
– Teletext Slicer
– Teletext Display RAM
– OSD
1.1.5 On Screen Display
The human interface is provided by the On Screen
Display module, this can produce up to 26 lines of
up to 80 characters from a ROM defined 512 character set. The character resolution is 10x10 dots.
Four character sizes are supported. Serial attributes allow the user to select foreground and
background colours, character size and fringe
background. Parallel attributes can be used to select additional foreground and background colors
and underline on a character by character basis.
1.1.6 Teletext and Display RAM
The internal 8k Teletext and Display storage RAM
can be used to store Teletext pages as well as Display parameters.
ST92R195B - GENERAL DESCRIPTION
INTRODUCTION (Cont’d)
1.1.7 Teletext, VPS and WSS Data Slicers
The three on-board data slicers using a single external crystal are used to extract the Teletext, VPS
and WSS information from the video signal. Hardware Hamming decoding is provided.
1.1.8 Voltage Synthesis Tuning Control
14-bit Voltage Synthesis using the PWM (Pulse
Width Modulation)/BRM (Bit Rate Modulation)
technique can be used to generate tuning voltages
for TV set applications. The tuning voltage is output on one of two separate output pins.
1.1.9 PWM Output
Control of TV settings is able to be made with up to
eight 8-bit PWM outputs, with a frequency maximum of 23,437Hz at 8-bit resolution (INTCLK = 12
MHz). Low resolutions with higher frequency operation can be programmed.
1.1.10 Serial Peripheral Interface (SPI)
The SPI bus is used to communicate with external
devices via the SPI, or I C bus communication
standards. The SPI uses a single line for data input and output. A second line is used for a synchronous clock signal.
1.1.11 Standard Timer (STIM)
The ST92R195B has one Standard Timer that includes a programmable 16-bit down counter and
an associated 8-bit prescaler with Single and Continuous counting modes.
1.1.12 Analog/Digital Converter (ADC)
In addition there is a 4 channel Analog to Digital
Converter with integral sample and hold, fast
5.75µs conversion time and 6-bit guaranteed resolution.
3/18
ST92R195B - GENERAL DESCRIPTION
Figure 1. ST92R195B Block Diagram
ADDR[15:0]
DAT[7:0]
ASN
RWN
DSN
MMU[5:0]
External
Memory I/F
1 Kbyte
RAM
256 bytes
Register File
8/16-bit
CPU
MEMORY BUS
8 Kbytes
TDSRAM TRI
I/O
PORT 0
3
P0[2:0]
I/O
PORT 2
6
P2[5:0]
I/O
PORT 3
4
P3[7:4]
I/O
PORT 4
8
P4[7:0]
I/O
PORT 5
2
P5[1:0]
MMU
NMI
INT[7:0]
DATA
SLICER
& ACQUISITIO N
UNIT
Interrupt
Management
ST9+ CORE
SDO/SDI
SCK
RCCU
SYNC.
EXTRACTION
16-BIT
TIMER/
WATCHDOG
VPS/WSS
DATA
SLICER
SPI
REGISTER BUS
OSCIN
OSCOUT
RESET
RESETO
TXCF
CVBS1
WSCR
WSCF
CVBS2
AIN[4:1]
EXTRG
ADC
MCFM
TIMING AND
CLOCK CTRL
SYNC
CONTROL
STOUT
STANDARD
TIMER
ON
SCREEN
DISPLAY
VSO[2:1]
VOLTAGE
SYNTHESIS
PWM
D/A CONVERTER
VSYNC
HSYNC/CSYNC
CSO
FREQ.
PXFM
MULTIP.
R/G/B/FB
TSLU
HT
All alternate functions (Italic characters) are mapped on Ports 0, 2, 3, 4 and 5
4/18
PWM[7:0]
ST92R195B - GENERAL DESCRIPTION
1.2 PIN DESCRIPTION
ADDR[15:0] External memory interface address
bus.
CVBS1 Composite video input signal for the Teletext slicer and sync extraction.
CVBS2 Composite video input signal for the VPS/
WSS slicer. Pin AC coupled.
CVBSO, JTDO, JTCK Test pins: leave floating.
DAT[7:0] External memory interface data bus.
DSN Data strobe for external memory interface.
FB Fast Blanking. Video analog DAC output.
GND Digital circuit ground.
GNDA Analog circuit ground (must be tied externally to digital GND).
GNDM External memory interface ground.
HSYNC/CSYNC Horizontal/Composite sync. Horizontal or composite video synchronisation input to
OSD. Positive or negative polarity.
JTRST0 Test pin: must be tied to GND.
MCFM Analog pin for the display pixel frequency
multiplier.
MMU[5:0] External memory interface MMU segment bus
OSCIN, OSCOUT Oscillator (input and output).
These pins connect a parallel-resonant crystal
(24MHz maximum), or an external source to the
on-chip clock oscillator and buffer. OSCIN is the
input of the oscillator inverter and internal clock
generator; OSCOUT is the output of the oscillator
inverter.
PXFM Analog pin for the Display Pixel Frequency
Multiplier
RESET Reset (input, active low). The ST9+ is initialised by the Reset signal. With the deactivation
of RESET, program execution begins from the
Program memory location pointed to by the vector
contained in program memory locations 00h and
01h.
R/G/B Red/Green/Blue. Video color analog DAC
outputs.
RWN Read/Write strobe for external memory interface.
TEST0 Test pin: must be tied to VDDA.
TXCF Analog pin for the teletext PLL.
VDD Main power supply voltage (5V ±10%, digital)
VDDA Analog power supply (must be tied externally to VDDA ).
VDDM External memory interface power supply.
VSYNC Vertical Sync. Vertical video synchronisation input to OSD. Positive or negative polarity.
WSCF, WSCR Analog pins for the VPS/WPP slicer. These pins must be tied to ground or not connected.
P0[2:0], P2[5:0], P3[7:4], P4[7:0], P5[1:0]- I/O
Port Lines (Input/Output, TTL or CMOS compatible). 23 lines grouped into I/O ports, bit programmable as general purpose I/O or as Alternate functions (see I/O section).
Important: Note that open-drain outputs are for
logic levels only and are not true open drain.
1.2.1 I/O Port Alternate Functions.
Each pin of the I/O ports of the ST92R195B may
assume software programmable Alternate Functions as shown in the Pin Configuration drawings.
Table 1. shows the Functions allocated to each I/O
Port pin.
5/18
ST92R195B - GENERAL DESCRIPTION
MMU0
MMU3
DAT5
DAT6
DAT7
DAT2
DAT1
DAT0
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR12
ADDR15
Figure 2. 80-Pin Package Pin-Out
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1
64
63
2
DAT4
DAT3
7
58
CVBSO
RWN
8
57
TXCF
9
56
JTRST0
VDDM
10
55
MCFM
OSCIN
11
54
RESET
OSCOUT
12
53
PXFM
ADDR13
13
52
VDDA
ADDR14
14
51
WSCF
MMU1
15
50
WSCR
MMU2
16
49
HSYNC/CSYNC
MMU4
17
48
VSYNC
MMU5
18
47
R
CSO/RESETO/P3.7
19
46
G
ASN/P3.6
20
45
B
P3.5
21
44
FB
P3.4
22
43
P4.0/PWM0
SDI/SDO/INT1/P5.1
23
42
24
41
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P4.1/PWM1
GNDM
INT7/P2.0
SCK/INT2/P5.0
6/18
PWM3/TSLU/HT/P4.3
TEST0
ADDR8
PWM4/P4.4
59
INT4/AIN3/VSO2/P2.5
6
INT0/AIN2/P2.2
CVBS2
ADDR9
INT5/AIN1/P2.1
60
GND
5
VDD
ADDR11
PWM5/P4.5
CVBS1
PWM6/P4.6
61
PWM7/EXTRG/INT3/STOUT/P4.7
4
P0.0
DSN
P0.1
GNDA
AIN4/P0.2
62
NMI/P2.4
3
INT6/VSO1/P2.3
ADDR10
P4.2/PWM2
ST92R195B - GENERAL DESCRIPTION
Table 1. ST92R195B I/O Port Alternate Function
Port
Name
General
Purpose I/O
Pin No.
PQFP80
Alternate Functions
P0.0
30
P0.1
29
P0.2
28
AIN4
I
A/D Analog Data Input 4
P2.0
25
INT7
I
External Interrupt 7
P2.1
36
AIN1
I
A/D Analog Data Input 1
INT5
I
External Interrupt 5
INT0
I
External Interrupt 0
AIN2
I
A/D Analog Data Input 2
INT6
I
External Interrupt 6
VSO1
O
Voltage Synthesis Output 1
NMI
I
Non Maskable Interrupt Input
AIN3
I
A/D Analog Data Input 3
INT4
I
External Interrupt 4
VSO2
O
Voltage Synthesis Output 2
P2.2
37
P2.3
26
P2.4
27
I/O
I/O
P2.5
38
P3.4
22
I/O
P3.5
I/O
P4.0
21
All ports useable 20
for general purpose I/O (input,
19
output or bidirectional)
43
P4.1
42
P4.2
41
P3.6
P3.7
P4.3
40
ASN
O
External Memory Interface Address Strobe
RESET0
O
Internal Reset Output
CSO
O
Composite Sync output
PWM0
O
PWM Output 0
PWM1
O
PWM Output 1
PWM2
O
PWM Output 2
PWM3
O
PWM Output 3
TSLU
O
Translucency Digital Output
HT
O
Half-tone Output
P4.4
39
PWM4
O
PWM Output 4
P4.5
33
PWM5
O
PWM Output 5
P4.6
32
PWM6
O
PWM Output 6
EXTRG
I
A/D Converter External Trigger Input
PWM7
O
PWM Output 7
STOUT
O
Standard Timer Output
INT3
I
External Interrupt 3
INT2
I
External Interrupt 2
SCK
O
SPI Serial Clock
SDO
O
SPI Serial Data Out
SDI
I
SPI Serial Data In
INT1
I
External Interrupt 1
P4.7
P5.0
P5.1
31
24
23
7/18
ST92R195B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
1.2.2 I/O Port Styles
Pins
P0[2:0]
P2[5,4,3,2]
P2[1:0]
P3.7
P3[6,5,4]
P4[7:0]
P5[1:0]
Physical Pull-Up
no
no
no
yes
no
no
no
Pin Style
standard I/O
standard I/O
std I/O, trigger
standard I/O
standard I/O
standard I/O
standard I/O
Reset Values
BID / OD / TTL
BID / OD / TTL
BID / OD / TTL
AF / PP / TTL
BID / OD / TTL
BID / OD / TTL
BID / OD / TTL
Legend:
AF= Alternate Function, BID = Bidirectional, OD = Open Drain
PP = Push-Pull, TTL = TTL Standard Input Levels
How to Read this Table
To configure the I/O ports, use the information in
this table and the Port Bit Configuration Table in
the I/O Ports Chapter of the datasheet.
Port Style= the hardware characteristics fixed for
each port line.
Inputs:
– If port style = Standard I/O, either TTL or CMOS
input level can be selected by software.
– If port style = Schmitt trigger, selecting CMOS or
TTL input by software has no effect, the input will
always be Schmitt Trigger.
Weak Pull-Up = This column indicates if a weak
pull-up is present or not.
– If WPU = yes, then the WPU can be enabled/disable by software
– If WPU = no, then enabling the WPU by software
has no effect
Alternate Functions (AF) = More than one AF
cannot be assigned to an external pin at the same
time:
An alternate function can be selected as follows.
AF Inputs:
– AF is selected implicitly by enabling the corresponding peripheral. Exception to this are ADC
analog inputs which must be explicitly selected
as AF by software.
8/18
AF Outputs or Bidirectional Lines:
– In the case of Outputs or I/Os, AF is selected
explicitly by software.
Example 1: ADC trigger digital input
AF: EXTRG, Port: P4.7, Port Style: Standard I/O.
Write the port configuration bits (for TTL level):
P4C2.7=1
P4C1.7=0
P4C0.7=1
Enable the ADC trigger by software as described
in the ADC chapter.
Example 2: PWM 0 output
AF: PWM0, Port: P4.0
Write the port configuration bits (for output pushpull):
P4C2.0=0
P4C1.0=1
P4C0.0=1
Example 3: ADC AIN1 analog input
AF: AIN1, Port : P2.1, Port style: does not apply to
analog inputs
Write the port configuration bits:
P2C2.1=1
P2C1.1=1
P2C0.1=1
4.7 µF
C14
+5V
XT1
4MHZ-OSC
82pF
C4
82pF
C3
10uH
L2
100nF
C7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
QFP80
MMU0
MMU3
ADDR10
DSN
ADDR11
ADDR9
ADDR8
R/WN
GNDM
VDDM
OSCIN
OSCOUT
ADDR13
ADDR14
MMU1
MMU2
MMU4
MMU5
P3.7/CSO/RESETO
P3.6/ASN
P3.5
P3.4
P5.1/SDI/SDO/INT1
P5.0/SCK/INT2
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
ST92R195B
ADDR15
ADDR12
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
DAT0
DAT1
DAT2
DAT7
DAT6
DAT5
C15
100nF
L3
10uH
DAT4
DAT3
GNDA
CVBS1
CVBS2
TEST0
CVBSO
TXCF
JTRST0
MCFM
RESETN
PXFM
VDDA
WSCF
WSCR
CSYNC/HSYNC
VSYNC
R
G
B
FB
P4.0/PWM0
P4.1/PWM1
P4.2/PWM2
C16
4.7 µF
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P2.0/INT7
P2.3/INT6/VSO1
P2.4/NMI
P0.2/AIN4
P0.1
P0.0
P4.7/PWM7/INT3
P4.6/PWM6
P4.5/PWM5
VDD
GND
P2.1/INT5/AIN1
P2.2/INT0/AIN2
P2.5/INT4/AIN3/VSO2
P4.4/PWM4
P4.3/PWM3/TSLU/HT
U1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
100nF
+5V
C12
HSYNC
VSYNC
R
G
B
FB
C13
4.7 µF
L1
R4
82pF
C2
10uH
5.6K
CVBS
+5V
4.7NF
C9
22PF
C5
470nF
C1
RST
S1
1µF
C6
10k
1N4148
D1
R3
22PF
C8
4.7NF
C10
5.6K
R2
ST92R195B - GENERAL DESCRIPTION
Figure 3. ST92R195B Required External components
9/18
ST92R195B - GENERAL DESCRIPTION
1.3 MEMORY MAP
No Internal ROM
Internal RAM, 1 Kbytes
The internal RAM is mapped in MMU segment
20h; from address FC00h to FFFFh.
Internal TDSRAM, 8K bytes expandable up to 16K
(into segment 22h)
The Internal TDSRAM is mapped into theMMU segment 22h. The TDSRAM is a fully static memory.
The TDSRAM is an 8K bytes mapped at the address 8000h to 9FFFh.
Figure 4. ST92R195B Memory Map
39FFFFh
External RAM
229FFFh
Reserved
8 Kbytes
TDSRAM
228000h
SEGMENT 22h
64 Kbytes
Internal
RAM
1 Kbyte
22C000h
22BFFFh
228000h
227FFFh
Reserved
224000h
223FFFh
Reserved
SEGMENT 21h
64 Kbytes
22FFFFh
220000h
21FFFFh
PAGE 91 - 16 Kbytes
PAGE 90 - 16 Kbytes
PAGE 89 - 16 Kbytes
PAGE 88 - 16 Kbytes
Reserved
210000h
20FFFFh
20FFFFh
PAGE 83 - 16 Kbytes
20C000h
20BFFFh
20FC00h
SEGMENT 20h
64 Kbytes
Reserved
PAGE 82 - 16 Kbytes
208000h
207FFFh
PAGE 81 - 16 Kbytes
Reserved
204000h
203FFFh
PAGE 80 - 16 Kbytes
Reserved
200000h
01FFFFh
PAGE 7 - 16 Kbytes
01C000h
01BFFFh
SEGMENT 1
64 Kbytes
PAGE 6 - 16 Kbytes
018000h
017FFFh
PAGE 5 - 16 Kbytes
014000h
013FFFh
External ROM/EPROM
01000 0h
00FFFFh
PAGE 4 - 16 Kbytes
PAGE 3 - 16 Kbytes
00C000h
00BFFFh
SEGMENT 0
64 Kbytes
PAGE 2 - 16 Kbytes
008000h
007FFFh
PAGE 1 - 16 Kbytes
004000h
003FFFh
PAGE 0 - 16 Kbytes
000000h
10/18
ST92R195B - ELECTRICAL CHARACTERISTICS
2 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V DD
Supply Voltage
VSS - 0.3 to V SS + 7.0
V
V SSA
Analog Ground
VSS - 0.3 to V SS + 0.3
V
V DDA
Analog Supply Voltage
V
VI
Input Voltage
VDD -0.3 to VDD +0.3
VSS - 0.3 to V DD +0.3
V
VSS - 0.3 to V DD +0.3
V AI
Analog Input Voltage (A/D Converter)
VO
Output Voltage
VSS - 0.3 to V DD + 0.3
V
TSTG
Storage Temperature
- 55 to + 150
°C
Pin Injected Current
- 5 to + 5
mA
- 50 to +5 0
mA
IINJ
V
VSSA - 0.3 to VDDA +0.3
Maximum Accumulated Pin
Injected Current In Device
Note: Stress above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
Min.
Max.
0
70
°C
TA
Operating Temperature
VDD
Supply Voltage
4.5
5.5
V
VDDA
Analog Supply Voltage (PLL)
4.5
5.5
V
fOSCE
External Oscillator Frequency
3.3
8.7
MHz
fOSCI
Internal Clock Frequency (INTCLK)
24
MHz
11/18
ST92R195B - ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
(VDD= 5V +/-10%; TA = 0 to 70°C; unless otherwise specified)
Symbol
Parameter
Test Conditions
VIHCK
Clock in high level
external clock
VILCK
Clock in low level
external clock
VIH
Input high level
TTL
VIL
Input low level
TTL
VIH
Input high level
CMOS
VIL
Input low level
CMOS
VIHRS
Reset in high level
VILRS
Reset in low level
VHYRS
Reset in hysteresis
VIHY
P2.(1:0) input hysteresis
VIHVH
HSYNC/VSYNC input high level
VILVH
HSYNC/VSYNC input low level
VHYHV
HSYNC/VSYNC input hysteresis
VOH
Output high level
Push-pull Ild=-0.8mA
VOL
Output low level
Push-pull ld=+1.6mA
Value
Min.
Max.
0.7 V DD
Unit
V
0.3 VDD
2.0
V
V
0.8
0.8 V DD
V
V
0.2 VDD
0.7 V DD
V
V
0.3 VDD
0.3
V
V
0.9
V
0.7 V DD
V
0.3 VDD
0.5
V
V
V DD-0.8
V
0.4
V
bidir. state
IWPU
Weak pull-up current
VOL= 3V
µA
50
VOL= 7V
350
ILKIO
I/O pin input leakage current
0<VIN<VDD
-10
+10
µA
ILKRS
Reset pin input
0<VIN<VDD
-10
+10
µA
ILKAD
A/D pin input leakage current
alternate funct. op. drain
-10
+10
µA
ILKOS
OSCIN pin input leakage current
0<VIN<VDD
-10
+10
µA
12/18
ST92R195B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
PIN CAPACITANCE
(VDD= 5V +/-10%; TA = 0 to 70°C; unless otherwise specified))
Symbol
C IO
Parameter
Value
Conditions
min
max
Pin Capacitance Digital Input/Output
10
Unit
pF
CURRENT CONSUMPTION
(VDD= 5V +/-10%; TA = 0 to 70°C; unless otherwise specified)
Symbol
Parameter
Value
Condition s
min
typ.
max
Unit
IDD1
Run Mode Current
notes 1,2; all On
70
100
mA
IDDA1
Run Mode Analog Current
(pin VDDA )
Timing Controller On
35
50
mA
IDD2
HALT Mode Current
notes 1,4
10
100
µA
IDDA2
HALT Mode Analog Current
(pin VDDA )
notes 1,4
40
100
µA
Notes:
1. Port 0 is configured in push-pull output mode (output is high). Ports 2, 3, 4 and 5 are configured in bi-directional weak pull-up mode resistor.
The external CLOCK pin (OSCIN) is driven by a square wave external clock at 8 MHz. The internal clock prescaler is in divide-by-1 mode.
2. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to VSS, HSYNC is driven by a 15625Hz clock.
All peripherals working including Display.
3. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to VSS, HSYNC is driven by a 15625Hz clock.
The TDSRAM interface and the Slicers are working; the Display controller is not working.
4. VSYNC and HSYNC tied to VSS. External CLOCK pin (OSCIN) is held low. All peripherals are disabled.
EXTERNAL INTERRUPT TIMING TABLE (rising or falling edge mode)
(VDD= 5V +/-10%; TA = 0 to 70°C; unless otherwise specified))
Symbol
Parameter
Condition s
INTCLK=24 MHz.
Value
min
Unit
max
TwLR
Low level pulse width
TpC+12
95
ns
TwHR
High level pulse width
TpC+12
95
ns
TpC is the INTCLK clock period.
13/18
ST92R195B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS (Cont’d)
EXTERNAL MEMORY INTERFACE TIMING TABLE
(VDD= 5V +/-10%; TA = 0 to 70°C; unless otherwise specified))
Symbol
TwDSR
Value
Parameter
Unit
typ
DSN low level pulse width (read)
max
TpC*(1/2+WDS)-6
ns
TwDSW
DSN low level pulse width (write)
TpC*(1/2+WDS)-6
ns
TdDSR(DR)
DSN↓ to data valid delay
TpC*(1/2+WDS)-16
ns
ThDR(DS)
Data to DSN↑ hold time
TdDS(A)
DSN↑ to address active delay
ThDS(AS)
DSN↑ to ASN↓ delay
TsRW(AS)
R/WN setup time before ASN↑
TdDSR(RW)
DSN↑ to R/WN and address not valid delay
TdDW(DSW)
Write data valid to DSN↓ delay (write)
ThDS(DW)
Data hold time after DSN↑ (write)
TdA(DR)
Address valid to data valid delay (read)
0
ns
TpC/2
ns
TpC/2 + 6
ns
TpC*(1/2 + WAS) - 8
ns
TpC/2
ns
0
ns
TpC/2
ns
TpC*(3/2+WDS+WAS)-14
ns
TpC is the INTCLK clock period.
SPI TIMING TABLE
(VDD= 5V +/-10%; TA = 0 to 70°C; Cload= 50pF)
Symbol
Parameter
Conditi on
Value
min
max
Unit
TsDI
Input Data Set-up Time
ThDI
Input Data Hold Time
TdOV
SCK to Output Data Valid
ThDO
Output Data Hold Time
tbd
ns
TwSKL
SCK Low Pulse Width
tbd
ns
TwSKH
SCK High Pulse Width
tbd
ns
tbd
(1)
OSCIN/2 as internal Clock
1INTCLK
ns
+100ns
ns
tbd
ns
(1) TpC is the OSCIN clock period; TpMC is the “Main Clock Frequency” period.
SKEW CORRECTOR TIMING TABLE
(VDD= 5V +/-10%, TA = 0 to 70°C, unless otherwise specified)
Symbol
Tjskw
Parameter
Jitter on RGB output
Conditions
36 MHz Skew corrector clock frequency
max
Value
Unit
5*
ns
(*) The OSD jitter is measured from leading edge to leading edge of a single character row on consecutive TV lines. The value is an envelope
of 100 fields
14/18
ST92R195B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS (Cont’d)
OSD DAC CHARACTERISTICS
(VDD= 5V +/-10%, TA = 0 to 70°C, unless otherwise specified).
Symbol
Parameter
Conditio ns
Output impedance: FB,R,G,B
Output voltage: FB,R,G,B
Value
min
typical
max
300
500
700
Unit
Ohm
Cload= 20pF
RL = 100K
code= 111
1.000
code= 011
0.459
0.509
V
V
code= 000
0.025
0.050
V
FB= 1
2.4
3.0
4.0
V
FB= 0
0
0.025
0.050
V
+/-5
%
Global voltage accuracy
A/D CONVERTER, EXTERNAL TRIGGER TIMING TABLE
(VDD= 5V +/-10%; TA = 0 to 70°C; unless otherwise specified
Symbol
Parameter
Tlow
Pulse Width
Thigh
Pulse Distance
Text
Period/fast Mode
Tstr
Start Conversion Delay
OSCIN divide by
2;min/max
OSCIN divide
by 1; min/max
Value
min
max
1.5
INTCLK
Unit
ns
ns
78+1
INTCLK
0.5
µs
1.5
INTCLK
Core Clock issued by Timing Controller
Tlow
Pulse Width
ns
Thigh
Pulse Distance
ns
Text
Period/fast Mode
µs
Tstr
Start Conversion Delay
ns
15/18
ST92R195B - ELECTRICAL CHARACTERISTICS
A/D CONVERTER. ANALOG PARAMETERS TABLE
(VDD= 5V +/-10%; TA = 0 to 70°C; unless otherwise specified)
Parameter
Value
typ (*)
Analog Input Range
Conversion Time Fast/Slow
Sample Time Fast/Slow
Power-up Time
Resolution
Differential Non Linearity
Unit
min
max
VSS
V DD
(**)
Note
V
78/138
INTCLK
(1,2)
51.5/87.5
INTCLK
(1)
60
µs
8
bits
1.5
2.5
LSBs
(4)
Integral Non Linearity
2
3
LSBs
(4)
Absolute Accuracy
2
3
LSBs
(4)
Input Resistance
1.5
Kohm
(3)
Hold Capacitance
1.92
pF
Notes: (*)
(**)
(1)
(2)
(3)
(4)
16/18
The values are expected at 25 Celsius degrees with VDD= 5V
’LSBs’ , as used here, as a value of VDD/256
@ 24 MHz external clock
including Sample time
it must be considered as the on-chip series resistance before the sampling capacitor
DNL ERROR= max {[V(i) -V(i-1)] / LSB-1}
INL ERROR= max {[V(i) -V(0)] / LSB-i}
ABSOLUTE ACCURACY= overall max conversion error
ST92R195B - GENERAL INFORMATION
3 GENERAL INFORMATION
3.1 PACKAGE MECHANICAL DATA
Figure 5. 80-Pin Plastic Quad Flat Package
0.10mm
.004
seating plane
Dim
mm
Min
Typ
A
inches
Max
Min
Typ
3.40
Max
0.134
A1
0.25
A2
2.55 2.80 3.05 0.100 0.110 0.120
B
0.30
0.45 0.012
0.018
C
0.13
0.23 0.005
0.009
D
22.95 23.20 23.45 0.904 0.913 0.923
D1
19.90 20.00 20.10 0.783 0.787 0.791
D3
0.010
18.40
0.724
E
16.95 17.20 17.45 0.667 0.677 0.687
E1
13.90 14.00 14.10 0.547 0.551 0.555
E3
12.00
e
0.80
K
L
0°
0.472
0.031
7°
0.65 0.80 0.95 0.026 0.031 0.037
L1
1.60
0.063
Number of Pins
N
PQFP080
80
ND
24
NE
16
3.2 ORDERING INFORMATION
Sales Type
ST92R195B9Q1
OSD
50/60 or 100/120 Hz
Temperature
Range
0-70°C
Package
PQFP80
17/18
ST92R195B - GENERAL INFORMATION
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2000 STMicroelectronics - All Rights Reserved.
Purchase of I2 C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
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18/18