STA506 40V 4A QUAD POWER HALF BRIDGE 1 FEATURES ■ MINIMUM INPUT OUTPUT PULSE WIDTH DISTORTION ■ 200mΩ RdsON COMPLEMENTARY DMOS OUTPUT STAGE ■ CMOS COMPATIBLE LOGIC INPUTS ■ THERMAL PROTECTION ■ THERMAL WARNING OUTPUT ■ UNDER VOLTAGE PROTECTION ■ SHORT CIRCUIT PROTECTION 2 MULTIPOWER BCD TECHNOLOGY PowerSO36 Table 1. Order Code DESCRIPTION Part Number Package STA506 PowerSO36 to make the output stage of a stereo All-Digital High Efficiency (DDX™) amplifier capable to deliver 60 + 60W @ THD = 10% at Vcc 32V output power on 8Ω load and 80W @ THD = 10% at VCC 36V on 8Ω load in single BTL configuration. In single BTL configuration is also capable to deliver a peak of 120W @THD = 10% at VCC = 32V on 4Ω load (t ≤1sec). The input pins have threshold proportional to VL pin voltage. STA506 is a monolithic quad half bridge stage in Multipower BCD Technology. The device can be used as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current capability, and as half bridge (Binary mode) with half current capability. The device is particularly designed Figure 1. APPLICATION CIRCUIT (Dual BTL) +VCC VCC1A IN1A 29 VL 23 M3 IN1A +3.3V R57 10K CONFIG 24 PWRDN PWRDN 25 R59 10K FAULT 27 C58 100nF TH_WAR 26 17 16 M2 PROTECTIONS & LOGIC TRI-STATE M5 TH_WAR 28 IN1B 30 C58 100nF C53 100nF C60 100nF VDD 21 22 VSS 33 VSS 34 VCCSIGN IN2A IN2A GND-Reg GND-Clean IN2B GND1A 12 VCC1B M4 REGULATORS 13 GND1B 7 VCC2A IN2B GNDSUB 8 9 M15 31 20 19 M16 1 C32 1µF GND2A 4 VCC2B OUT2B OUT2B M14 5 8Ω C21 100nF C110 100nF C109 330pF R103 6 C33 1µF 3 R100 6 C99 100nF C23 470nF C101 100nF L113 22µH OUT2A 6 R98 6 L19 22µH OUT2A 2 32 R63 20 OUT1B OUT1B 35 36 C20 100nF C52 330pF C31 1µF 11 C55 1000µF L18 22µH OUT1A 14 M17 VCCSIGN C30 1µF OUT1A 10 IN1B VDD 15 R104 20 R102 6 C107 100nF C108 470nF C106 100nF 8Ω C111 100nF L112 22µH GND2B D00AU1148B June 2004 REV. 4 1/14 STA506 Table 2. PIN FUNCTION Pin n. Pin Name 1 GND-SUB 2;3 OUT2B Output Half Bridge 2B 4 VCC 2B Positive Supply 5 GND2B Negative Supply 6 GND2A Negative Supply 7 VCC 2A Positive Supply 8;9 OUT2A Output Half Bridge 2A 10 ; 11 OUT1B Output Half Bridge 1B 12 VCC1B Positive Supply 13 GND1B Negative Supply 14 GND1A Negative Supply 15 VCC1A Positive Supply 16 ; 17 OUT1A Output Half Bridge 1A 18 NC Not Connected 19 GND-clean Logical Ground 20 GND-Reg Ground for Regulator Vdd 21 ; 22 Vdd 5V Regulator Referred to Ground 23 VL Logic Reference Voltage 24 CONFIG Configuration pin 25 PWRDN Stand-by pin 26 TRI-STATE 27 FAULT 28 TH-WAR 29 IN1A Input of Half Bridge 1A 30 IN1B Input of Half Bridge 1B 31 IN2A Input of Half Bridge 2A 32 IN2B Input of Half Bridge 2B 33 ; 34 VSS 5V Regulator Referred to +VCC 35 ; 36 VCC Sign 2/14 Description Substrate Ground Hi-Z pin Fault pin advisor Thermal warning advisor Signal Positive Supply STA506 Table 3. FUNCTIONAL PIN STATUS Pin name Pin n. Logical value FAULT 27 0 Fault detected (Short circuit, or Thermal ..) 27 1 Normal Operation TRI-STATE 26 0 All powers in Hi-Z state TRI-STATE 26 1 Normal operation PWRDN 25 0 Low absorpion PWRDN 25 1 Normal operation THWAR 28 0 Temperature of the IC =130°C THWAR(*) 28 1 Normal operation CONFIG 24 0 Normal Operation CONFIG(**) 24 1 OUT1A = OUT1B ; OUT2A=OUT2B (IF IN1A = IN1B; IN2A = IN2B) FAULT (*) : (**): (*) IC -STATUS The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor. To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd) to implement single BTL (mono mode) operation for high current. Figure 2. PIN CONNECTION VCCSign 36 1 GND-SUB VCCSign 35 2 OUT2B VSS 34 3 OUT2B VSS 33 4 VCC2B IN2B 32 5 GND2B IN2A 31 6 GND2A IN1B 30 7 VCC2A IN1A 29 8 OUT2A TH_WAR 28 9 OUT2A FAULT 27 10 OUT1B TRI-STATE 26 11 OUT1B PWRDN 25 12 VCC1B CONFIG 24 13 GND1B VL 23 14 GND1A VDD 22 15 VCC1A VDD 21 16 OUT1A GND-Reg 20 17 OUT1A GND-Clean 19 18 N.C. D01AU1273 3/14 STA506 Table 4. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VCE DC Supply Voltage (Pin 4,7,12,15) 40 V Vmax Maximum Voltage on pins 23 to 32 (logic reference) 5.5 V Ptot Power Dissipation (Tcase = 70°C) 50 W Top Operating Temperature Range 0 to 70 °C -40 to 150 °C Tstg, Tj Storage and Junction Temperature Table 5. (*) RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min. DC Supply Voltage 9.0 VL Input Logic Reference 2.7 Tamb Ambient Temperature 0 VCC Typ. 3.3 Max. Unit 36.0 V 5.0 v 70 °C (*) performances not guaranteed beyond recommended operating conditions Table 6. THERMAL DATA Symbol Tj-case Parameter Min. Typ. Thermal Resistance Junction to Case (thermal pad) Max. Unit 1.5 °C/W TjSD Thermal shut-down junction temperature 150 °C Twarn Thermal warning temperature 130 °C thSD Thermal shut-down hysteresis 25 °C Table 7. ELECTRICAL CHARACTERISTCS: refer to circuit in Fig.1 (VL = 3.3V; VCC = 32V; R L = 8Ω; fsw = 384KHz; Tamb = 25°C unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit 200 270 mΩ 50 µA RdsON Power Pchannel/Nchannel MOSFET RdsON Id=1A Idss Power Pchannel/Nchannel leakage Idss VCC =35V gN Power Pchannel RdsON Matching Id=1A 95 % gP Power Nchannel RdsON Matching Id=1A 95 % Dt_s Low current Dead Time (static) see test circuit no.1; see fig. 3 Dt_d 20 ns High current Dead Time (dinamic) L=22µH; C = 470nF; RL = 8 Ω Id=3.5A; see fig. 5 50 ns td ON Turn-on delay time Resistive load 100 ns td OFF Turn-off delay time Resistive load 100 ns tr Rise time Resistive load; as fig.3 25 ns tf Fall time Resistive load; as fig. 3 25 ns 36 V VL/2 +300mV V VCC Supply voltage operating voltage VIN-H High level input voltage 4/14 10 9 STA506 TABLE 6. ELECTRICAL CHARACTERISTCS (continued) Symbol Parameter Test conditions Min. Typ. Max. VL/2 300mV Unit VIN-L Low level input voltage IIN-H Hi level Input current Pin Voltage = VL 1 µA IIN-L Low level input current Pin Voltage = 0.3V 1 µA 35 µA IPWRDN-H Hi level PWRDN pin input current VL = 3.3V VLOW Low logical state voltage VLow VL = 3.3V (pin PWRDN, TRISTATE) (note 1) VHIGH High logical state voltage VHigh VL = 3.3V (pin PWRDN, TRISTATE) (note 1) IVCCPWRDN Supply CURRENT from Vcc in Power Down IFAULT Output Current pins FAULT -TH-WARN when FAULT CONDITIONS IVCC-hiz IVCC IVCC-q VOUT-SH 0.8 V PWRDN = 0 Vpin = 3.3V 1.7 V 3 mA 1 mA Supply Current from Vcc in Tristate VCC = 30V; Tri-state = 0 22 mA Supply Current from Vcc in operation both channel switching) VCC =30V; Input Pulse width = 50% Duty; Switching Frequency = 384KHz; No LC filters; 50 mA Isc (short circuit current limit) (note 2) 4 Undervoltage protection threshold Output minimum pulse width VOV V 6 8 A 7 No Load 70 V 150 ns Notes: 1. The following table explains the VLOW, VHIGH variation with VL Table 8. VL VLOW min VHIGH max Unit 2.7 0.7 1.5 V 3.3 0.8 1.7 V 5 0.85 1.85 V Note 2: See relevant Application Note AN1994 Table 9. LOGIC TRUTH TABLE (see fig. 4) TRI-STATE INxA INxB Q1 Q2 Q3 Q4 OUTPUT MODE 0 x x OFF OFF OFF OFF Hi-Z 1 0 0 OFF OFF ON ON DUMP 1 0 1 OFF ON ON OFF NEGATIVE 1 1 0 ON OFF OFF ON POSITIVE 1 1 1 ON ON OFF OFF Not used 5/14 STA506 Figure 3. Test Circuit. OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t DTr Duty cycle = 50% DTf M58 OUTxY INxY R 8Ω M57 + - gnd V67 = vdc = Vcc/2 D03AU1458 Figure 4. +VCC Q1 Q2 OUTxA INxA OUTxB Q3 INxB Q4 GND D00AU1134 Figure 5. High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B DTout(A) M58 DTin(A) Q1 Q2 Rload=8Ω OUTA INA Iout=4A M57 Q3 DTout(B) L67 22µ C69 470nF L68 22µ C71 470nF C70 470nF DTin(B) OUTB INB Iout=4A Q4 Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure 6/14 M64 M63 D03AU1517 STA506 3 TECHNICAL INFO: The STA506 is a dual channel H-Bridge that is able to deliver more than 60W per channel (@ THD=10%) of audio output power in high efficiency. The STA506 converts both DDX and binary-controlled PWM signals into audio power at the load. It includes a logic interface , integrated bridge drivers, high efficiency MOSFET outputs and thermal and short circuit protection circuitry. In DDX mode, two logic level signals per channel are used to control high-speed MOSFET switches to connect the speaker load to the input supply or to ground in a Bridge configuration, according to the damped ternary Modulation operation. In Binary Mode operation , both Full Bridge and Half Bridge Modes are supported. The STA506 includes overcurrent and thermal protection as well as an under-voltage Lockout with automatic recovery. A thermal warning status is also provided. Figure 6. STA506 Block Diagram Full-Bridge DDX® or Binary Modes INL[1:2] INR[1:2] VL OUTPL Logic I/F and Decode Left H-Bridge PWRDN OUTNL TRI-STATE FAULT TWARN Protection Circuitry OUTPR Right H-Bridge Regulators OUTNR Figure 7. STA506 Block Diagram Binary Half-Bridge Mode LeftA ‰-Bridge OUTPL LeftB ‰-Bridge OUTNL Protection Circuitry RightA ‰-Bridge OUTPR Regulators RightB ‰-Bridge OUTNR INL[1:2] INR[1:2] VL Logic I/F and Decode PWRDN TRI-STATE FAULT TWARN 3.1 Logic Interface and Decode: The STA506 power outputs are controlled using one or two logic level timing signals. In order to provide a proper logic interface, the Vbias input must operate at the dame voltage as the DDX control logic supply. 3.2 Protection Circuitry: The STA506 includes protection circuitry for over-current and thermal overload conditions. A thermal warning pin (pin.28) is activated low (open drain MOSFET) when the IC temperature exceeds 130C, in advance of the thermal shutdown protection. When a fault condition is detected , an internal fault signal acts to immediately disable the output power MOSFETs, placing both H-Bridges in high impedance state. At the same time an opendrain MOSFET connected to the fault pin (pin.27) is switched on. 7/14 STA506 There are two possible modes subsequent to activating a fault: – 1) SHUTDOWN mode: with FAULT (pull-up resistor) and TRI-STATE pins independent, an activated fault will disable the device, signaling low at the FAULT output. The device may subsequently be reset to normal operation by toggling the TRI-STATE pin from High to Low to High using an external logic signal. – 2) AUTOMATIC recovery mode: This is shown in the Application Circuit of fig.1. The FAULT and TRI-STATE pins are shorted together and connected to a time constant circuit comprising R59 and C58. An activated FAULT will force a reset on the TRI-STATE pin causing normal operation to resume following a delay determined by the time constant of the circuit. If the fault condition is still present , the circuit operation will continue repeating until the fault condition is removed . An increase in the time constant of the circuit will produce a longer recovery interval. Care must be taken in the overall system design as not to exceed the protection thesholds under normal operation. 3.3 Power Outputs: The STA506 power and output pins are duplicated to provide a low impedance path for the device's bridged outputs . All duplicate power, ground and output pins must be connected for proper operation. The PWRDN or TRI-STATE pins should be used to set all MOSFETS to the Hi-Z state during power-up until the logic power supply, VL , is settled. 3.4 Parallel Output / High Current Operation: When using DDX Mode output , the STA506 outputs can be connected in parallel in order to increase the output current capability to a load. In this configuration the STA506 can provide 80W into 8 ohm or up to 120W into 4ohm. This mode of operation is enabled with the CONFIG pin (pin.24) connected to VREG1 and the inputs combined INLA=INLB, INRA=INRB and the outputs combined OUTLA=OTLB, OUTRA=OUTRB. 3.5 Additional Informations: Output Filter: A passive 2nd-order passive filter is used on the STA506 power outputs to reconstruct an analog Audio Signal . System performance can be significantly affected by the output filter design and choice of passive components. A filter design for 6ohm/8ohm loads is shown in the Typical Application circuit of fig.1. Figure 9 shows a filter design suitable for 4ohm loads. Figure 10 shows a filter for ½ bridge mode , 4 ohm loads. Power Dissipation & Heat Sink requirements: The power dissipated within the device will depend primarily on the supply voltage, load impedance and output modulation level. The PowerSO36 package of the STA506 includes an exposed thermal slug on the top of the device to provide a direct thermal path from the IC to the heatsink. Careful consideration must be given to the overall thermal design . See figure 8 for power derating versus Slug temperature using different heatsinks and considering the Rth-jc =1.5°C/W. 8/14 STA506 Figure 8. STA506 power derating curve 60 Pdiss(W) 1 –Infinite 2- 1.5C/W 3- 3 C/W 4- 4 C/W 1 50 40 2 30 3 20 4 10 0 0 20 40 60 80 100 120 140 160 Slug temperature C° Figure 9. Typical Single BTL Configurationto obtain 120W @ THD 10%, RL = 4Ω, VCC = 32V (note 1)) VL +3.3V GND-Clean GND-Reg 10K 23 18 N.C. 10µH 100nF 100nF X7R VDD VDD CONFIG TH_WAR TH_WAR PWRDN nPWRDN 10K FAULT IN1A IN1B IN1A IN2A IN2B IN1B VSS VSS 100nF X7R 20 21 22 24 28 25 27 TRI-STATE 100nF 19 VCCSIGN 100nF X7R VCCSIGN Add. GNDSUB 26 29 17 16 11 10 OUT1B OUT1B OUT2A 8 34 22Ω 1/2W 6.2 1/2W 330pF 6.2 1/2W OUT2B 3 15 12 7 4 100nF X7R 470nF FILM 100nF X7R 4Ω 100nF FILM OUT2B 2 10µH VCC1A VCC1B 32V 1µF X7R VCC2A 32 33 100nF FILM OUT1A OUT2A 9 30 31 OUT1A VCC2B 2200µF 63V 32V 1µF X7R GND1A 14 GND1B 35 13 36 6 1 5 GND2A GND2B D03AU1514 Note: 1. "A PWM modulator as driver is needed . In particular, this result is performed using the STA30X+STA50X demo board". Peak Power for t ≤1sec 9/14 STA506 Figure 10. Typical Quad Half Bridge Configuration +VCC VCC1P IN1A 29 M3 IN1A +3.3V PWRDN R57 10K R59 10K C58 100nF TH_WAR VL 23 CONFIG 24 PWRDN FAULT 16 26 M2 PROTECTIONS & LOGIC TRI-STATE M5 TH_WAR 28 IN1B 30 VDD 21 VDD 22 VSS 33 VSS 34 C53 100nF C60 100nF IN2A GND-Reg GND-Clean IN2B PGND1P 12 VCC1N C51 1µF REGULATORS 13 7 C41 330pF PGND1N VCC2P C71 100nF R51 6 IN2B GNDSUB R42 20 C42 330pF C72 100nF R52 6 C82 100nF 9 36 M15 31 20 19 M16 6 PGND2P 4 VCC2N 3 2 32 1 OUTPR C52 1µF 5 C43 330pF PGND2N C73 100nF R53 6 C83 100nF C62 100nF OUTNR OUTNR M14 R43 20 C44 330pF R66 5K R67 5K L14 22µH R44 20 R64 5K R65 5K L13 22µH OUTPR R62 5K R63 5K L12 22µH 8 35 D03AU1474 C74 100nF R54 6 For more information refer to the application notes AN1456 and AN1661 10/14 C81 100nF C61 100nF OUTNL OUTNL M4 R41 20 M17 VCCSIGN VCCSIGN IN2A 14 10 IN1B C58 100nF OUTPL OUTPL 11 R61 5K L11 22µH 17 25 27 15 C84 100nF R68 5K C21 2200µF C31 820µF C91 1µF 4Ω C32 820µF C92 1µF 4Ω C33 820µF C93 1µF 4Ω C34 820µF C94 1µF 4Ω STA506 The following measures are related to the application using STA308A driver Figure 11. THD+N vs Frequency Figure 14. THD+N vs Output Power 1 T THD(%) 10 5 0.5 Vcc=32V Rl=8ohm 2 Vcc=36V Rl=8ohm 0.2 1 F=1KHz 0.5 % 0.1 0.2 0.05 0.1 0.05 0.02 0.02 0.01 20 50 100 200 500 1k 2k 5k 10k 20k 0.01 100m 200m 500m 1 2 Hz 5 10 20 50 80 Pout(W) Figure 12. Output Power vs Vsupply Table 10. THD+N vs Output PowerRevision THD(%) 10 Po(W) 80 5 70 Rl=8ohm 60 2 Vcc=32V Rl=8ohm F=1KHz 1 THD=10% F=1KHz 50 0.5 40 0.2 30 0.1 20 0.05 THD=1% 10 0.02 0.01 +14 +16 +18 +20 +22 +24 +26 +28 +30 +32 +34 +36 Vsupply(V) 100m 200m 500m 1 2 5 10 20 50 80 Pout(W) Figure 13. THD+N vs Output Power THD(%) 10 5 2 Vcc=34V Rl=8ohm 1 F=1KHz 0.5 0.2 0.1 0.05 0.02 0.01 100m 200m 500m 1 2 5 10 20 50 80 Pout(W) 11/14 STA506 DIM. A A2 A4 A5 a1 b c D D1 D2 E E1 E2 E3 E4 e e3 G H h L N s MIN. 3.25 3.1 0.8 mm TYP. MAX. 3.43 3.2 1 MIN. 0.128 0.122 0.031 -0.040 0.38 0.32 16 9.8 0.0011 0.008 0.009 0.622 0.37 14.5 11.1 2.9 6.2 3.2 0.547 0.429 0.2 0.030 0.22 0.23 15.8 9.4 5.8 2.9 0.8 OUTLINE AND MECHANICAL DATA -0.0015 0.015 0.012 0.630 0.38 0.039 0.57 0.437 0.114 0.244 1.259 0.228 0.114 0.65 11.05 0 15.5 MAX. 0.135 0.126 0.039 0.008 1 13.9 10.9 inch TYP. 0.026 0.435 0.075 0 15.9 0.61 1.1 1.1 0.031 10˚ (max) 8˚ (max) 0.003 0.625 0.043 0.043 (1) “D and E1” do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006”) (2) No intrusion allowed inwards the leads. PowerSO36 (SLUG UP) 7183931 C 12/14 STA506 Table 11. History Date Revision Description of Changes December 2003 1 First Issue April 2004 2 Inserted Technical Info and Graphics April 2004 3 Small changes in pag 4 and 5 June 2004 4 Note 2: See relevant Application Note AN1994 13/14 STA506 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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