STA508 40V 4.5A QUAD POWER HALF BRIDGE 1 ■ ■ FEATURES Figure 1. Package MULTIPOWER BCD TECHNOLOGY MINIMUM INPUT OUTPUT PULSE WIDTH DISTORTION ■ 200mΩ RdsON COMPLEMENTARY DMOS OUTPUT STAGE ■ CMOS COMPATIBLE LOGIC INPUTS ■ THERMAL PROTECTION ■ THERMAL WARNING OUTPUT ■ UNDER VOLTAGE PROTECTION 2 PowerSO36 Table 1. Order Codes Part Number Package STA508 PowerSO36 The device is particularly designed to make the output stage of a stereo All-Digital High Efficiency (DDX™) amplifier capable to deliver 80 + 80W @ THD = 10% at Vcc 35V output power on 8Ω load. DESCRIPTION STA508 is a monolithic quad half bridge stage in Multipower BCD Technology. The device can be used as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current capability, and as half bridge (Binary mode) with half current capability. In single BTL configuration is also capable to deliver a peak of 160W @THD = 10% at VCC = 35V on 4Ω load (t ≤1sec). The input pins have threshold proportional to Ibias pin voltage. Figure 2. Block Diagram +VCC VCC1A IN1A 29 VL 23 CONFIG 24 PWRDN 25 FAULT 27 M3 IN1A +3.3V PWRDN R57 10K R59 10K C58 100nF TH_WAR 26 17 16 M2 PROTECTIONS & LOGIC TRI-STATE M5 TH_WAR 28 IN1B 30 C58 100nF C53 100nF C60 100nF VDD 21 22 VSS 33 VSS 34 VCCSIGN IN2A IN2A GND-Reg GND-Clean IN2B 12 VCC1B IN2B GNDSUB M4 REGULATORS M15 20 M16 GND1B 7 VCC2A C32 1µF GND2A 4 VCC2B OUT2B OUT2B M14 5 8Ω C21 100nF C110 100nF C109 330pF R103 6 C33 1µF 3 R100 6 C99 100nF C23 470nF C101 100nF L113 22µH OUT2A 6 R98 6 L19 22µH OUT2A 2 32 R63 20 OUT1B 13 8 31 1 C31 1µF 11 9 19 C20 100nF C52 330pF OUT1B 35 36 OUT1A GND1A C55 1000µF L18 22µH OUT1A M17 VCCSIGN C30 1µF 14 10 IN1B VDD 15 R104 20 R102 6 C107 100nF C108 470nF C106 100nF 8Ω C111 100nF L112 22µH GND2B D00AU1148B June 2004 REV. 2 1/10 STA508 Table 2. Pin Description N° Pin 1 GND-SUB 2;3 OUT2B Output Half Bridge 2B 4 VCC 2B Positive Supply 5 GND2B Negative Supply 6 GND2A Negative Supply 7 VCC 2A Positive Supply 8;9 OUT2A Output Half Bridge 2A 10 ; 11 OUT1B Output Half Bridge 1B 12 VCC1B Positive Supply 13 GND1B Negative Supply 14 GND1A Negative Supply 15 VCC1A Positive Supply 16 ; 17 OUT1A Output Half Bridge 1A 18 NC Not Connected 19 GND-clean Logical Ground 20 GND-Reg Ground for Regulator Vdd 21 ; 22 Vdd 5V Regulator Referred to Ground 23 VL High Logical State Setting Voltage 24 CONFIG Configuration pin 25 PWRDN Stand-by pin 26 TRI-STATE 27 FAULT 28 TH-WAR 29 IN1A Input of Half Bridge 1A 30 IN1B Input of Half Bridge 1B 31 IN2A Input of Half Bridge 2A 32 IN2B Input of Half Bridge 2B 33 ; 34 VSS 5V Regulator Referred to +VCC 35 ; 36 VCC Sign 2/10 Description Substrate Ground Hi-Z pin Fault pin Advisor Thermal Warning Advisor Signal Positive Supply STA508 Table 3. FUNCTIONAL PIN STATUS PIN NAME Logical value IC -STATUS FAULT 0 Fault detected (Short circuit, or Thermal ..) FAULT (*) 1 Normal Operation TRI-STATE 0 All powers in Hi-Z state TRI-STATE 1 Normal operation PWRDN 0 Low absorpion PWRDN 1 Normal operation THWAR 0 Temperature of the IC =130°C THWAR(*) 1 Normal operation CONFIG 0 Normal Operation CONFIG(**) 1 OUT1A = OUT1B ; OUT2A=OUT2B (IF IN1A = IN1B; IN2A = IN2B) (*) : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor. (**): To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd) Figure 3. PIN CONNECTION VCCSign 36 1 GND-SUB VCCSign 35 2 OUT2B VSS 34 3 OUT2B VSS 33 4 VCC2B IN2B 32 5 GND2B IN2A 31 6 GND2A IN1B 30 7 VCC2A IN1A 29 8 OUT2A TH_WAR 28 9 OUT2A FAULT 27 10 OUT1B TRI-STATE 26 11 OUT1B PWRDN 25 12 VCC1B CONFIG 24 13 GND1B VL 23 14 GND1A VDD 22 15 VCC1A VDD 21 16 OUT1A GND-Reg 20 17 OUT1A GND-Clean 19 18 N.C. D01AU1273 Table 4. THERMAL DATA Symbol Description Rth j-case Thermal Resistance Junction-case Value Unit max 1.5 °C/W 3/10 STA508 Table 5. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VCE DC Supply Voltage (Pin 4,7,12,15) 40 V Vmax Maximum Voltage on pins 23 to 32 5.5 V Ptot Power Dissipation (Tcase = 70°C) 50 W Top Operating Temperature Range 0 to 70 °C -40 to 150 °C Tstg, Tj Storage and Junction Temperature Table 6. ELECTRICAL CHARACTERISTCS (VL = 3.3V; VCC = 30V; Tamb = 25°C ; fsw =384 unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit 200 270 mΩ 50 µA RdsON Power Pchannel/Nchannel MOSFET RdsON Id=1A Idss Power Pchannel/Nchannel leakage Idss VCC =35V gN Power Pchannel RdsON Matching Id=1A 95 % gP Power Nchannel RdsON Matching Id=1A 95 % Dt_s Low current Dead Time (static) see test circuit no.1; see fig. 4 Dt_d 20 ns High current Dead Time (dinamic) L=22µH; C = 470nF; RL = 8 Ω Id=3.5A; see fig. 3 50 ns td ON Turn-on delay time Resistive load 100 ns td OFF Turn-off delay time Resistive load 100 ns tr Rise time Resistive load; as fig.4 25 ns tf Fall time Resistive load; as fig. 4 25 ns 36 V VL/2 +300mV V VCC Supply voltage operating voltage 10 9 VIN-High High level input voltage VIN-Low Low level input voltage IIN-High High level Input current Pin Voltage = VL 1 µA IIN-Low Low level input current Pin Voltage = 0.3V 1 µA 35 µA IPWRDN-H High level PWRDN pin input current VL 4/10 Low logical state voltage VL (pin PWRDN, TRISTATE) (note 1) VL/2 300mV VL = 3.3V VL = 3.3V 0.8 V V STA508 Table 6. ELECTRICAL CHARACTERISTCS (continued) Symbol Parameter VH High logical state voltage VH (pin PWRDN, TRISTATE) (note 1) VL = 3.3V IVCCPWRDN Supply CURRENT from Vcc in Power Down PWRDN = 0 IFAULT Output Current pins FAULT -TH-WARN when FAULT CONDITIONS IVCC-hiz IVCC IVCC-q VOUT-SH VOV Test conditions Min. Vpin = 3.3V Typ. Max. Unit 1.7 V 3 mA 1 mA Supply Current from Vcc in Tristate VCC = 30V; Tri-state = 0 22 mA Supply Current from Vcc in operation both channel switching) VCC =30V; Input Pulse width = 50% Duty; Switching Frequency = 384KHz; No LC filters; 50 mA Isc (short circuit current limit) (note 2) 4.5 Undervoltage protection threshold Output minimum pulse width 6 9 A 7 No Load 70 V 150 ns Table 7. Notes: 1. The following table explains the VLow, VHigh variation with Ibias VL VLow min VHigh max Unit 2.7 0.7 1.5 V 3.3 0.8 1.7 V 5 0.85 1.85 V Note 2: See relevant Application Note AN1994 Table 8. LOGIC TRUTH TABLE (see fig. 5) TRI-STATE INxA INxB Q1 Q2 Q3 Q4 OUTPUT MODE 0 x x OFF OFF OFF OFF Hi-Z 1 0 0 OFF OFF ON ON DUMP 1 0 1 OFF ON ON OFF NEGATIVE 1 1 0 ON OFF OFF ON POSITIVE 1 1 1 ON ON OFF OFF Not used 5/10 STA508 Figure 4. Test Circuit. OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t DTr Duty cycle = 50% DTf M58 OUTxY INxY R 8Ω M57 V67 = vdc = Vcc/2 + - gnd D03AU1458 Figure 5. +VCC Q1 Q2 OUTxA INxA OUTxB Q3 INxB Q4 GND D00AU1134 Figure 6. High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B DTout(A) M58 DTin(A) Q1 Q2 OUTA INA Iout=4A M57 Q3 DTout(B) Rload=8Ω L67 22µ C69 470nF L68 22µ C71 470nF C70 470nF DTin(B) OUTB INB Iout=4A Q4 Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure 6/10 M64 M63 D03AU1517 STA508 Figure 7. Typical Single BTL Configuration VL +3.3V GND-Clean GND-Reg 100nF X7R 10K 23 18 N.C. 10µH 100nF VDD VDD CONFIG TH_WAR TH_WAR PWRDN nPWRDN FAULT 10K IN1A IN1B IN1A IN2A IN2B IN1B VSS VSS 100nF X7R 16 20 11 10 21 VCCSIGN 100nF X7R VCCSIGN Add. GNDSUB OUT1A 100nF FILM OUT1A OUT1B 9 24 OUT2A 6.2 1/2W 330pF 8 OUT2B 28 3 15 26 29 12 30 31 7 10µH VCC1A 32V 1µF X7R VCC1B 4 2200µF 63V VCC2A 32V 1µF X7R 32 33 4Ω 100nF FILM OUT2B 2 25 100nF X7R 470nF FILM 100nF X7R 6.2 1/2W 22Ω 1/2W OUT1B OUT2A 22 27 TRI-STATE 100nF 17 19 VCC2B GND1A 34 14 GND1B 35 13 36 6 GND2A GND2B 1 5 D03AU1514 Figure 8. Typical Quad Half Bridge Configuration +VCC VCC1P IN1A 29 VL 23 CONFIG 24 PWRDN 25 FAULT 27 M3 IN1A +3.3V PWRDN R57 10K R59 10K C58 100nF TH_WAR 26 16 M2 PROTECTIONS & LOGIC M5 28 IN1B 30 VDD 21 VDD 22 VSS 33 VSS 34 C53 100nF C60 100nF VCCSIGN IN2A GND-Reg GND-Clean IN2B PGND1P 12 VCC1N C51 1µF REGULATORS 13 7 C41 330pF PGND1N VCC2P C71 100nF R51 6 C81 100nF C61 100nF OUTNL OUTNL M4 R41 20 R42 20 C42 330pF C72 100nF R52 6 C82 100nF IN2B GNDSUB 9 36 M15 31 20 19 M16 1 OUTPR 6 PGND2P 4 VCC2N 3 2 32 OUTPR C52 1µF 5 C43 330pF PGND2N D03AU1474 C73 100nF R53 6 C83 100nF C62 100nF OUTNR OUTNR M14 R43 20 C44 330pF R66 5K R67 5K L14 22µH R44 20 R64 5K R65 5K L13 22µH 8 35 R62 5K R63 5K L12 22µH M17 VCCSIGN IN2A 14 10 IN1B C58 100nF OUTPL OUTPL 11 R61 5K L11 22µH 17 TRI-STATE TH_WAR 15 C74 100nF R54 6 C84 100nF R68 5K C21 2200µF C31 820µF C91 1µF 4Ω C32 820µF C92 1µF 4Ω C33 820µF C93 1µF 4Ω C34 820µF C94 1µF 4Ω For more information refer to the application notes AN1456 and AN1661 7/10 STA508 Figure 9. Power SO36 (SLUG UP) Mechanical Data & Package Dimensions DIM. A A2 A4 A5 a1 b c D D1 D2 E E1 E2 E3 E4 e e3 G H h L N s MIN. 3.25 3.1 0.8 mm TYP. MAX. 3.43 3.2 1 MIN. 0.128 0.122 0.031 -0.040 0.38 0.32 16 9.8 0.0011 0.008 0.009 0.622 0.37 14.5 11.1 2.9 6.2 3.2 0.547 0.429 0.2 0.030 0.22 0.23 15.8 9.4 5.8 2.9 0.8 OUTLINE AND MECHANICAL DATA -0.0015 0.015 0.012 0.630 0.38 0.039 0.57 0.437 0.114 0.244 1.259 0.228 0.114 0.65 11.05 0 15.5 MAX. 0.135 0.126 0.039 0.008 1 13.9 10.9 inch TYP. 0.026 0.435 0.075 0 15.9 0.61 1.1 1.1 0.031 10˚ (max) 8˚ (max) 0.003 0.625 0.043 0.043 (1) “D and E1” do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006”) (2) No intrusion allowed inwards the leads. PowerSO36 (SLUG UP) 7183931 C 8/10 STA508 Table 9. Revision History Date Revision Description of Changes September 1994 1 First Issue June 2004 2 Note 2: See relevant Application Note AN1994 9/10 STA508 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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