STD16NE10L N - CHANNEL 100V - 0.07 Ω - 16A DPAK STripFET POWER MOSFET PRELIMINARY DATA TYPE V DSS R DS(o n) ID STD16NE10L 100 V < 0.10 Ω 16 A ■ ■ ■ ■ ■ ■ ■ TYPICAL RDS(on) = 0.07 Ω AVALANCHE RUGGED TECHNOLOGY LOW GATE CHARGE HIGH CURRENT CAPABILITY 175 oC OPERATING TEMPERATURE LOW THRESHOLD DRIVE ADD SUFFIX ”T4” FOR ORDERING IN TAPE & REEL DESCRIPTION This Power MOSFET is the latest development of STMicroelectronics unique ”Single Feature Size” strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. 3 1 DPAK TO-252 (Suffix ”T4”) INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ SOLENOID AND RELAY DRIVERS ■ DC-DC & DC-AC CONVERTERS ■ AUTOMOTIVE ENVIRONMENT ABSOLUTE MAXIMUM RATINGS Symb ol V DS V DGR Value Unit Drain-source Voltage (VGS = 0) Parameter 100 V Drain- gate Voltage (R GS = 20 kΩ) 100 V G ate-source Voltage ± 20 V ID Drain Current (continuous) at Tc = 25 oC 16 A ID Drain Current (continuous) at Tc = 100 o C 11 A Drain Current (pulsed) 64 A VGS I DM (•) P tot o T otal Dissipation at Tc = 25 C Derating Factor dv/ dt (1 ) Peak Diode Recovery voltage slope T st g Tj Storage Temperature Max. Operating Junction Temperature (•) Pulse width limited by safe operating area May 2000 55 W 0.36 W /o C 7 V/ns -65 to 175 o C 175 o C ( 1) ISD ≤16A, di/dt ≤ 300 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX 1/6 STD16NE10L THERMAL DATA R th j-pc b R thj -amb R t hj-s ink Tl Thermal Resistance Junction-PC Board Max Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink T yp Maximum Lead Temperature F or Soldering Purpose o 2.73 100 1.5 275 C/W C/W o C/W o C o AVALANCHE CHARACTERISTICS Symbo l Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 16 A E AS Single Pulse Avalanche Energy (starting Tj = 25 o C, ID = IAR , V DD = 30 V) 75 mJ ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbo l V (BR)DSS Parameter Drain-source Breakdown Voltage Test Con ditions I D = 250 µA V GS = 0 I DSS V DS = Max Rating Zero Gate Voltage Drain Current (V GS = 0) V DS = Max Rating IGSS Gate-body Leakage Current (VDS = 0) Min. Typ. Max. 100 Unit V T c = 125 oC V GS = ± 20 V 1 10 µA µA ± 100 nA Max. Unit ON (∗) Symbo l Parameter Test Con ditions ID = 250 µA V GS(th) Gate Threshold Voltage V DS = V GS R DS(on) Static Drain-source On Resistance V GS = 10 V V GS = 5 V I D(o n) On State Drain Current V DS > ID(o n) x R DS(on )ma x V GS = 10 V Min. 1 ID = 8 A ID = 8 A Typ. 1.7 2.5 V 0.07 0.085 0.085 0.1 Ω Ω 16 A DYNAMIC Symbo l g f s (∗) C iss C os s C rss 2/6 Parameter Test Con ditions Forward Transconductance V DS > ID(o n) x R DS(on )ma x Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 25 V f = 1 MHz ID = 8 A V GS = 0 V Min. Typ. Max. Unit 5 9 S 1750 165 45 pF pF pF STD16NE10L ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbo l Parameter Test Con ditions Min. Typ. Max. Unit t d(on) tr Turn-on Delay T ime Rise Time V DD = 50 V ID = 8 A R G = 4.7 Ω V GS = 4.5 V (Resistive Load, see fig. 3) 40 80 Qg Q gs Q gd Total G ate Charge Gate-Source Charge Gate-Drain Charge V DD = 80 V ID = 16 A V GS = 5 V 24 5.5 11 32 nC nC nC Typ. Max. Unit ns ns SWITCHING OFF Symbo l Parameter Test Con ditions Min. t d(of f) tf Turn-off Delay T ime Fall T ime V DD = 50 V ID = 8 A V GS = 4.5 V R G = 4.7 Ω (Resistive Load, see fig. 3) 45 12 ns ns tr (Voff) tf tc Off-voltage Rise T ime Fall T ime Cross-over Time V DD = 80 V I D = 16 A V GS = 4.5 V R G = 4.7 Ω (Induct ive Load, see fig. 5) 12 17 35 ns ns ns SOURCE DRAIN DIODE Symbo l Parameter Test Con ditions ISD I SDM (•) Source-drain Current Source-drain Current (pulsed) V SD (∗) Forward On Voltage I SD = 16 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 16 A di/dt = 100 A/µs T j = 150 o C V DD = 40 V (see test circuit, fig. 5) t rr Q rr I RRM Min. Typ. V GS = 0 Max. Unit 16 64 A A 1.5 V 100 ns 300 nC 6 A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area 3/6 STD16NE10L Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 4/6 STD16NE10L TO-252 (DPAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.64 0.9 0.025 0.035 B2 5.2 5.4 0.204 0.212 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 E 6.4 6.6 0.252 0.260 G 4.4 4.6 0.173 0.181 H 9.35 10.1 0.368 0.397 L2 0.8 L4 0.031 0.6 1 0.023 0.039 A1 C2 A H A2 C DETAIL ”A” L2 D = 1 = G 2 = = = E = B2 3 B DETAIL ”A” L4 0068772-B 5/6 STD16NE10L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 6/6