STMICROELECTRONICS STD1NB50

STD1NB50

N - CHANNEL 500V - 7.5Ω - 1.4A IPAK
PowerMESH MOSFET
TYPE
V DSS
R DS(on)
ID
ST D1NB50
500V
< 9Ω
1.4 A
■
■
■
■
■
■
TYPICAL RDS(on) = 7.5 Ω
EXTREMELY HIGH dv/dt CAPABILITY
100% AVALANCHE TESTED
VERY LOW INTRINSIC CAPACITANCES
GATE CHARGE MINIMIZED
FOR SMD DPAK VERSION CONTACT
SALES OFFICE
3
1
DESCRIPTION
Using the latest high voltage MESH OVERLAY
process, STMicroelectronics has designed an
advanced family of power MOSFETs with
outstanding performances. The new patent
pending strip layout coupled with the Company’s
proprietary edge termination structure, gives the
lowest RDS(on) per area, exceptional avalanche
and dv/dt capabilities and unrivalled gate charge
and switching characteristics.
2
IPAK
TO-251
(Suffix ”-1”)
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
SWITCH MODE POWER SUPPLIES (SMPS)
■ DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
■
ABSOLUTE MAXIMUM RATINGS
Symbol
V DS
V DGR
V GS
Parameter
Value
Un it
500
V
Drain- gate Voltage (R GS = 20 kΩ)
500
V
G ate-source Voltage
± 36
V
1.4
A
Drain Current (continuous) at Tc = 100 C
0.91
A
Drain Current (pulsed)
5.6
A
T otal Dissipation at Tc = 25 o C
45
W
Derating Factor
0.36
W /o C
Peak Diode Recovery voltage slope
3.5
V/ns
Drain-source Voltage (VGS = 0)
o
ID
Drain Current (continuous) at Tc = 25 C
ID
o
I DM (•)
P tot
dv/dt( 1)
Ts tg
Tj
Storage Temperature
Max. Operating Junction Temperature
(•) Pulse width limited by safe operating area
March 2000
-65 to 150
o
C
150
o
C
( 1) ISD ≤1.4A, di/dt ≤ 150 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX
1/8
STD1NB50
THERMAL DATA
R thj -case
Rthj -amb
R thc-sink
Tl
Thermal Resistance Junction-case
Max
Thermal Resistance Junction-ambient
Max
Thermal Resistance Case-sink
Typ
Maximum Lead Temperature F or Soldering Purpose
o
2.78
100
1.5
275
C/W
oC/W
o
C/W
o
C
Max Value
Unit
AVALANCHE CHARACTERISTICS
Symbo l
Parameter
IAR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tj max, δ < 1%)
1.4
A
E AS
Single Pulse Avalanche Energy
(starting Tj = 25 o C, ID = IAR , V DD = 50 V)
40
mJ
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified)
OFF
Symbo l
V (BR)DSS
Parameter
Drain-source
Breakdown Voltage
Test Con ditions
I D = 250 µA
V GS = 0
I DSS
V DS = Max Rating
Zero Gate Voltage
Drain Current (V GS = 0) V DS = Max Rating
IGSS
Gate-body Leakage
Current (VDS = 0)
Min.
Typ.
Max.
500
Unit
V
1
50
µA
µA
± 100
nA
Typ.
Max.
Unit
3
4
V
7.5
9
Ω
T c = 125 oC
V GS = ± 30 V
ON (∗)
Symbo l
Parameter
Test Con ditions
V GS(th)
Gate Threshold Voltage V DS = V GS
ID = 250 µA
R DS(on)
Static Drain-source On
Resistance
V GS = 10V
ID =0.5 A
I D(o n)
On State Drain Current
V DS > ID(o n) x R DS(on )ma x
V GS = 10 V
Min.
2
1.4
A
DYNAMIC
Symbo l
g f s (∗)
C iss
C os s
C rss
2/8
Parameter
Test Con ditions
Forward
Transconductance
V DS > ID(o n) x R DS(on )ma x
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V DS = 25 V
f = 1 MHz
I D = 0.7 A
V GS = 0
Min.
Typ.
0.45
0.7
150
24
2.5
Max.
Unit
S
200
32
3.3
pF
pF
pF
STD1NB50
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbo l
Parameter
Test Con ditions
t d(on)
tr
Turn-on Time
Rise Time
V DD = 250 V
ID = 0.7 A
R G = 4.7 Ω
V GS = 10 V
(see test circuit, figure 3)
Qg
Q gs
Q gd
Total G ate Charge
Gate-Source Charge
Gate-Drain Charge
V DD = 400 V
Min.
I D =1.4 A V GS = 10 V
Typ.
Max.
Unit
8
8
12
12
ns
ns
9
5.5
2.4
13
nC
nC
nC
Typ.
Max.
Unit
20
22
30
28
31
42
ns
ns
ns
Typ.
Max.
Unit
1.4
5.6
A
A
1.6
V
SWITCHING OFF
Symbo l
tr (Voff)
tf
tc
Parameter
Off-voltage Rise T ime
Fall T ime
Cross-over Time
Test Con ditions
Min.
V DD = 400 V I D = 1.4 A
R G = 4.7 Ω VGS = 10 V
(see test circuit, figure 5)
SOURCE DRAIN DIODE
Symbo l
Parameter
Test Con ditions
ISD
I SDM (•)
Source-drain Current
Source-drain Current
(pulsed)
V SD (∗)
Forward On Voltage
I SD = 1.4 A
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
I SD = 1.4 A di/dt = 100 A/µs
o
T j = 150 C
V DD = 100 V
(see test circuit, figure 5)
t rr
Q rr
I RRM
Min.
V GS = 0
330
ns
780
nC
4.7
A
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Safe Operating Area
Thermal Impedance
3/8
STD1NB50
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
4/8
STD1NB50
Normalized Gate Threshold Voltage vs
Temperature
Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
5/8
STD1NB50
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/8
STD1NB50
TO-251 (IPAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
MAX.
MIN.
A
2.2
TYP.
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A3
0.7
1.3
0.027
0.051
B
0.64
0.9
0.025
0.031
B2
5.2
5.4
0.204
0.212
B3
TYP.
MAX.
0.85
B5
0.033
0.3
0.012
B6
0.95
0.037
C
0.45
0.6
0.017
0.023
C2
0.48
0.6
0.019
0.023
D
6
6.2
0.236
0.244
E
6.4
6.6
0.252
0.260
G
4.4
4.6
0.173
0.181
H
15.9
16.3
0.626
0.641
L
9
9.4
0.354
0.370
L1
0.8
1.2
0.031
0.047
L2
0.8
1
0.031
0.039
A1
C2
A3
A
C
H
B
B6
=
1
=
2
G
=
=
=
E
B2
=
3
B5
L
D
B3
L2
L1
0068771-E
7/8
STD1NB50
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specific ation mentioned in this publication are
subjec t to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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 1999 STMicroelectronics – Printed in Italy – All Rights Reserved
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8/8
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