STMICROELECTRONICS STD3NC50

STD3NC50

N - CHANNEL 500V - 2.4Ω - 3A TO-251/TO-252
PowerMESH ΙΙ MOSFET
PRELIMINARY DATA
TYPE
ST D3NC50
■
■
■
■
■
■
V DSS
R DS(on)
ID
500 V
< 2.7 Ω
3 A
TYPICAL RDS(on) = 2.4 Ω
EXTREMELY HIGH dv/dt CAPABILITY
100% AVALANCHE TESTED
NEW HIGH VOLTAGE BENCHMARK
GATE CHARGE MINIMIZED
ADD SUFFIX ”T4” FOR ORDERING IN TAPE
& REEL.
DESCRIPTION
The PowerMESH ΙΙ is the evolution of the first
generation of MESH OVERLAY . The layout
refinements introduced greatly improve the
Ron*area figure of merit while keeping the device
at the leading edge for what concerns switching
speed, gate charge and ruggedness.
3
3
2
1
1
DPAK
TO-252
(Suffix ”T4”)
IPAK
TO-251
(Suffix ”-1”)
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ SWITH MODE POWER SUPPLIES (SMPS)
■ DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVER
ABSOLUTE MAXIMUM RATINGS
Symbol
V DS
V DGR
V GS
Value
Un it
Drain-source Voltage (V GS = 0)
Parameter
500
V
Drain- gate Voltage (R GS = 20 kΩ)
500
V
G ate-source Voltage
± 30
V
3.2
A
2
A
12.8
A
ID
Drain Current (continuous) at Tc = 25 o C
ID
Drain Current (continuous) at Tc = 100 oC
I DM (•)
P tot
Drain Current (pulsed)
o
T otal Dissipation at Tc = 25 C
Derating Factor
dv/dt( 1 )
Ts tg
Tj
Peak Diode Recovery voltage slope
Storage Temperature
Max. Operating Junction Temperature
(•) Pulse width limited by safe operating area
January 2000
60
W
0.48
W /o C
4
V/ns
-65 to 150
o
C
150
o
C
( 1) ISD ≤3 A, di/dt ≤ 100 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX
1/7
STD3NC50
THERMAL DATA
R thj -case
Rthj -amb
R thc-sink
Tl
Thermal Resistance Junction-case
Max
Thermal Resistance Junction-ambient
Max
Thermal Resistance Case-sink
Typ
Maximum Lead Temperature For Soldering Purpose
o
2.0
100
1.5
275
C/W
oC/W
o
C/W
o
C
Max Valu e
Unit
AVALANCHE CHARACTERISTICS
Symbo l
Parameter
IAR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tj max)
3
A
E AS
Single Pulse Avalanche Energy
o
(starting Tj = 25 C, I D = IAR , VDD = 50 V)
40
mJ
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified)
OFF
Symbo l
V (BR)DSS
Parameter
Drain-source
Breakdown Voltage
Test Con ditions
I D = 250 µA
V DS = Max Rating
Zero G ate Voltage
Drain Current (V GS = 0) V DS = Max Rating
IGSS
Gate-body Leakage
Current (VDS = 0)
T yp.
Max.
500
V GS = 0
I DSS
Min.
Unit
V
T c = 125 oC
V GS = ± 30 V
1
50
µA
µA
± 100
nA
ON (∗)
Symbo l
Parameter
Test Con ditions
ID = 250 µA
V GS(th)
Gate Threshold
Voltage
R DS(on)
Static Drain-source O n V GS = 10V
Resistance
I D(o n)
V DS = V GS
Min.
T yp.
Max.
Unit
2
3
4
V
2.4
2.7
Ω
ID = 1.5 A
3
On State Drain Current V DS > ID(o n) x R DS(on )ma x
V GS = 10 V
A
DYNAMIC
Symbo l
g f s (∗)
C iss
C os s
C rss
2/7
Parameter
Test Con ditions
Forward
Transconductance
V DS > ID(o n) x R DS(on )ma x
Input Capacitance
Output Capacitance
Reverse T ransfer
Capacitance
V DS = 25 V
f = 1 MHz
I D = 1.5 A
V GS = 0
Min.
T yp.
Max.
Unit
2
S
400
62
7.5
pF
pF
pF
STD3NC50
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbo l
Parameter
Test Con ditions
Min.
T yp.
Max.
Unit
t d(on)
tr
Turn-on Time
Rise Time
V DD = 300 V
R G = 4.7 Ω
ID = 1.5 A
VGS = 10 V
11
8
ns
ns
Qg
Q gs
Q gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V DD = 480 V
I D = 3 A V GS = 10 V
15
6.5
5
21
nC
nC
nC
T yp.
Max.
Unit
SWITCHING OFF
Symbo l
tr (Voff)
tf
tc
Parameter
Off-voltage Rise Time
Fall Time
Cross-over Time
Test Con ditions
Min.
8
5
14
V DD = 400 V ID = 3 A
R G = 4.7 Ω V GS = 10 V
ns
ns
ns
SOURCE DRAIN DIODE
Symbo l
ISD
I SDM (•)
V SD (∗)
t rr
Q rr
I RRM
Parameter
Test Con ditions
Min.
T yp.
Source-drain Current
Source-drain Current
(pulsed)
Forward On Voltage
I SD = 3 A
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
I SD = 3 A di/dt = 100 A/µs
T j = 150 o C
V DD = 100 V
V GS = 0
Max.
Unit
3
12
A
A
1.6
V
245
ns
980
µC
8
A
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
3/7
STD3NC50
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
4/7
STD3NC50
TO-251 (IPAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.2
2.4
0.086
A1
0.9
1.1
0.035
0.043
A3
0.7
1.3
0.027
0.051
B
0.64
0.9
0.025
0.031
B2
5.2
5.4
0.204
0.212
B3
0.094
0.85
B5
0.033
0.3
0.012
B6
0.95
0.037
C
0.45
0.6
0.017
C2
0.48
0.6
0.019
0.023
0.023
D
6
6.2
0.236
0.244
E
6.4
6.6
0.252
0.260
G
4.4
4.6
0.173
0.181
H
15.9
16.3
0.626
0.641
L
9
9.4
0.354
0.370
L1
0.8
1.2
0.031
L2
0.8
0.047
1
0.031
0.039
A1
C2
A3
A
C
H
B
B6
=
1
=
2
G
=
=
=
E
B2
=
3
B5
L
D
B3
L2
L1
0068771-E
5/7
STD3NC50
TO-252 (DPAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.2
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A2
0.03
0.23
0.001
0.009
B
0.64
0.9
0.025
0.035
B2
5.2
5.4
0.204
0.212
C
0.45
0.6
0.017
0.023
C2
0.48
0.6
0.019
0.023
D
6
6.2
0.236
0.244
E
6.4
6.6
0.252
0.260
G
4.4
4.6
0.173
0.181
H
9.35
10.1
0.368
0.397
L2
0.8
L4
0.031
0.6
1
0.023
0.039
A1
C2
A
H
A2
C
DETAIL ”A”
L2
D
=
1
=
G
2
=
=
=
E
=
B2
3
B
DETAIL ”A”
L4
0068772-B
6/7
STD3NC50
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
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