STD40NF06LZ N-CHANNEL 60V - 0.020 Ω - 40A DPAK Zener-Protected STripFET™ II POWER MOSFET TYPE STD40NF06LZ ■ ■ ■ ■ ■ ■ VDSS RDS(on) ID 60 V < 25 mΩ 40 A TYPICAL RDS(on) = 0.020Ω 100% AVALANCHE TESTED LOW GATE CHARGE LOGIC LEVEL GATE DRIVE SURFACE-MOUNTING DPAK (TO-252) POWER PACKAGE IN TAPE & REEL (SUFFIX “T4") BUILT-IN ZENER DIODES TO IMPROVE ESD PROTECTION UP TO 2kV DESCRIPTION This Power MOSFET is the latest development of STMicroelectronis unique "Single Feature Size™" strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. 3 1 DPAK TO-252 (Suffix “T4”) INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ SINGLE-ENDED SMPS IN MONITOTS, COMPUTER AND INDUSTRIAL APPLICATION ■ WELDING EQUIPMENT ■ AUTOMOTIVE ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID ID IDM(•) Ptot VESD(G-S) dv/dt(1) EAS(2) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Gate-source ESD(HBM-C=100pF, R=15kΩ) Peak Diode Recovery voltage slope Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature (•) Pulse width limited by safe operating area. October 2002 . Value 60 60 ± 16 40 28 160 100 0.67 ± 2.5 9 450 Unit V V V A A A W W/°C kV V/ns mJ -55 to 175 °C (1)ISD ≤40A, di/dt ≤100A/µs, VDD ≤ V(BR)DSS, Tj ≤ T JMAX . (2) Starting Tj = 25 oC ID = 20A VDD = 45V 1/8 STD40NF06LZ THERMAL DATA Rthj-case Rthj-PCB Tl Thermal Resistance Junction-case Thermal Resistance Junction-PCB (#) Maximum Lead Temperature For Soldering Purpose Max Max 1.5 50 300 °C/W °C/W °C (#) When Mounted on 1 inch2 FR-4 board, 2 oz Cu. ELECTRICAL CHARACTERISTICS (Tcase = 25 °C unless otherwise specified) OFF Symbol Parameter Test Conditions Min. Typ. Max. Unit Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating TC = 125°C 1 50 µA µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 16 V ±10 µA Max. Unit V(BR)DSS 60 V ON (*) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS ID = 250 µA RDS(on) Static Drain-source On Resistance VGS = 5 V VGS = 10 V ID = 20 A D = 20 A Min. Typ. 1 V 0.030 0.025 Ω Ω Max. Unit DYNAMIC Symbol 2/8 Parameter Test Conditions gfs (*) Forward Transconductance VDS = 15 V Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25V, f = 1 MHz, VGS = 0 ID = 20 A Min. Typ. 25 S 1360 302 115 pF pF pF STD40NF06LZ ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time ID = 20 A VDD = 30 V RG = 4.7 Ω VGS = 4.5 V (Resistive Load, Figure 3) 17 75 ns ns Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD =48 V ID =40 A VGS=10V 54 11 12 nC nC nC SWITCHING OFF Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions Min. ID = 20 A VDD = 30V RG = 4.7Ω, VGS = 4.5 V (Resistive Load, Figure 3) Typ. Max. 38 23 Unit ns ns SOURCE DRAIN DIODE Symbol Parameter ISD ISDM (•) Source-drain Current Source-drain Current (pulsed) VSD (*) Forward On Voltage ISD = 40A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current di/dt = 100A/µs ISD = 40 A VDD = 30 V Tj = 150°C (see test circuit, Figure 5) trr Qrr IRRM Test Conditions Min. Typ. VGS = 0 66 142 4.3 Max. Unit 40 160 A A 1.6 V ns nC A (*)Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•)Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/8 STD40NF06LZ Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STD40NF06LZ Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized Breakdown Voltage vs Temperature. . . 5/8 STD40NF06LZ Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STD40NF06LZ TO-252 (DPAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.64 0.9 0.025 0.035 B2 5.2 5.4 0.204 0.212 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 E 6.4 6.6 0.252 0.260 G 4.4 4.6 0.173 0.181 H 9.35 10.1 0.368 0.397 L2 0.8 L4 0.031 0.6 1 0.023 0.039 A1 C2 A H A2 C DETAIL "A" L2 D = 1 = G 2 = = = E = B2 3 B DETAIL "A" L4 0068772-B 7/8 STD40NF06LZ Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics 2001 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 8/8