STMICROELECTRONICS STD5N20-1

STD5N20

N - CHANNEL 200V - 0.7Ω - 5A - TO-251/TO-252
POWER MOS TRANSISTOR
TYPE
STD5N20
■
■
■
■
■
■
■
■
■
■
V DSS
R DS(on)
ID
200 V
< 0.8 Ω
5 A
TYPICAL RDS(on) = 0.7 Ω
AVALANCHE RUGGED TECHNOLOGY
100% AVALANCHE TESTED
REPETITIVE AVALANCHE DATA AT 100oC
LOW GATE CHARGE
HIGH CURRENT CAPABILITY
150oC OPERATING TEMPERATURE
APPLICATION ORIENTED
CHARACTERIZATION
THROUGH-HOLE IPAK (TO-251) POWER
PACKAGE IN TUBE (SUFFIX ”-1”)
SURFACE-MOUNTING DPAK (TO-252)
POWER PACKAGE IN TAPE & REEL
(SUFFIX ”T4”)
3
3
2
1
IPAK
TO-251
(Suffix ”-1”)
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ SOLENOID AND RELAY DRIVERS
■ DC-DC CONVERTERS & DC-AC INVERTERS
■ TELECOMMUNICATION POWER SUPPLIES
INDUSTRIAL MOTOR DRIVES
1
DPAK
TO-252
(Suffix ”T4”)
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symb ol
V DS
V DGR
V GS
Value
Un it
Drain-source Voltage (V GS = 0)
Parameter
200
V
Drain- gate Voltage (R GS = 20 kΩ)
200
V
± 20
V
G ate-source Voltage
o
ID
Drain Current (continuous) at Tc = 25 C
5
A
ID
Drain Current (continuous) at Tc = 100 C
3.5
A
Drain Current (pulsed)
20
A
45
W
0.36
W /o C
I DM (•)
P tot
o
o
T otal Dissipation at Tc = 25 C
Derating Factor
T s tg
Tj
Storage T emperature
Max. Operating Junction Temperature
-65 to 150
o
C
150
o
C
(•) Pulse width limited by safe operating area
March 1999
1/10
STD5N20
THERMAL DATA
R thj -case
R thj -amb
R thc-sink
Tl
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Thermal Resistance Case-sink
Maximum Lead Temperature F or Soldering Purpose
Max
Max
T yp
o
2.77
100
1.5
275
C/W
C/W
o
C/W
o
C
o
AVALANCHE CHARACTERISTICS
Symbo l
Parameter
IAR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tj max,)
E AS
Single Pulse Avalanche Energy
(starting Tj = 25 o C, ID = IAR , V DD = 50 V)
Max Value
Unit
5
A
130
mJ
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified)
OFF
Symbo l
V (BR)DSS
Parameter
Drain-source
Breakdown Voltage
Test Con ditions
I D = 250 µA
V GS = 0
I DSS
V DS = Max Rating
Zero Gate Voltage
Drain Current (V GS = 0) V DS = Max Rating
IGSS
Gate-body Leakage
Current (VDS = 0)
Min.
Typ.
Max.
200
Unit
V
T c =125 o C
V GS = ± 20 V
10
100
µA
µA
± 100
nA
Max.
Unit
ON (∗)
Symbo l
Parameter
Test Con ditions
ID = 250 µA
V GS(th)
Gate Threshold Voltage V DS = V GS
R DS(on)
Static Drain-source On
Resistance
V GS = 10 V
I D(o n)
On State Drain Current
V DS > ID(o n) x R DS(on )ma x
V GS = 10 V
Min.
2
ID = 2.5 A
Typ.
3
4
V
0.7
0.8
Ω
5
A
DYNAMIC
Symbo l
g f s (∗)
C iss
C os s
C rss
2/10
Parameter
Test Con ditions
Forward
Transconductance
V DS > ID(o n) x R DS(on )ma x
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V DS = 25 V
f = 1 MHz
I D = 2.5 A
V GS = 0
Min.
Typ.
1.5
3
450
75
15
Max.
Unit
S
600
100
20
pF
pF
pF
STD5N20
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbo l
t d(on)
tr
(di/dt) on
Qg
Q gs
Q gd
Typ.
Max.
Unit
Turn-on Time
Rise Time
Parameter
V DD = 100 V
I D = 2.5 A
R G = 4.7 Ω
V GS = 10 V
(see test circuit, figure 3)
Test Con ditions
7
6
10
8
ns
ns
Turn-on Current Slope
V DD = 160 V
ID = 5 A
V GS = 10 V
R G = 47 Ω
(see test circuit, figure 5)
400
Total G ate Charge
Gate-Source Charge
Gate-Drain Charge
V DD = 160 V
18
6
7
25
nC
nC
nC
Typ.
Max.
Unit
7
5
15
10
7
20
ns
ns
ns
Typ.
Max.
Unit
5
20
A
A
1.5
V
ID = 5 A
Min.
VGS = 10 V
A/µs
SWITCHING OFF
Symbo l
tr (Voff)
tf
tc
Parameter
Off-voltage Rise T ime
Fall T ime
Cross-over Time
Test Con ditions
Min.
V DD = 160 V I D = 5 A
R G = 4.7 Ω VGS = 10 V
(see test circuit, figure 5)
SOURCE DRAIN DIODE
Symbo l
Parameter
Test Con ditions
ISD
I SDM (•)
Source-drain Current
Source-drain Current
(pulsed)
V SD (∗)
Forward On Voltage
I SD = 5 A
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
I SD = 5 A
di/dt = 100 A/µs
T j = 150 o C
V DD = 100 V
(see test circuit, figure 5)
t rr
Q rr
I RRM
Min.
V GS = 0
180
ns
1125
nC
12.5
A
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Safe Operating Area
Thermal Impedance
3/10
STD5N20
Derating Curve
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
4/10
STD5N20
Capacitance Variations
Normalized Gate Threshold Voltage vs
Temperature
Normalized On Resistance vs Temperature
Turn-on Current Slope
Turn-off Drain-source Voltage Slope
Cross-over Time
5/10
STD5N20
Switching Safe Operating Area
Accidental Overload Area
Source-drain Diode Forward Characteristics
Fig. 1: Unclamped Inductive Load Test Circuit
6/10
Fig. 2: Unclamped Inductive Waveform
STD5N20
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And DIode Recovery Times
7/10
STD5N20
TO-251 (IPAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
MAX.
MIN.
A
2.2
TYP.
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A3
0.7
1.3
0.027
0.051
B
0.64
0.9
0.025
0.031
B2
5.2
5.4
0.204
0.212
B3
TYP.
MAX.
0.85
B5
0.033
0.3
0.012
B6
0.95
0.037
C
0.45
0.6
0.017
0.023
C2
0.48
0.6
0.019
0.023
D
6
6.2
0.236
0.244
E
6.4
6.6
0.252
0.260
G
4.4
4.6
0.173
0.181
H
15.9
16.3
0.626
0.641
L
9
9.4
0.354
0.370
L1
0.8
1.2
0.031
0.047
L2
0.8
1
0.031
0.039
A1
C2
A3
A
C
H
B
B6
=
1
=
2
G
=
=
=
E
B2
=
3
B5
L
D
B3
L2
L1
0068771-E
8/10
STD5N20
TO-252 (DPAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.2
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A2
0.03
0.23
0.001
0.009
B
0.64
0.9
0.025
0.035
B2
5.2
5.4
0.204
0.212
C
0.45
0.6
0.017
0.023
C2
0.48
0.6
0.019
0.023
D
6
6.2
0.236
0.244
E
6.4
6.6
0.252
0.260
G
4.4
4.6
0.173
0.181
H
9.35
10.1
0.368
0.397
L2
0.8
L4
0.031
0.6
1
0.023
0.039
A1
C2
A
H
A2
C
DETAIL ”A”
L2
D
=
1
=
G
2
=
=
=
E
=
B2
3
B
DETAIL ”A”
L4
0068772-B
9/10
STD5N20
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granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specific ation mentioned in this publication are
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 1999 STMicroelectronics – Printed in Italy – All Rights Reserved
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10/10
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