STLC2500 BLUETOOTH™ SINGLE CHIP PRELIMINARY DATA 1 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ FEATURES Bluetooth™ specification compliance: V1.1 and V1.2 Ericsson Licensing Technology Baseband Core (EBC) Point-to-point, point-to-multi-point (up to 7 slaves) and scatternet capability Asynchronous Connection Oriented (ACL) logical transport link Synchronous Connection Oriented (SCO) link: 2 simultaneous SCO channels Support Pitch-Period Error Concealment (PPEC) – Improves speech quality in the vicinity of interference – Improves coexistence with WLAN – Works at receiver, no Bluetooth implication Adaptive Frequency Hopping (AFH): hopping kernel, channel assessment as Master and as Slave Faster Connection: Interlaced scan for Page and Inquiry scan, first FHS without random back off, RSSI used to limit range Extended SCO (eSCO) links HW support for packet types – ACL: DM1, 3, 5 and DH1, 3, 5 – SCO: HV1, 3 and DV – eSCO: EV3, 5 Clock support – System clock input (digital or sine wave) at 13, 26, 19.2 or 38.4 MHz – LPO clock input at 3.2, 16.384, 32 or 32.768 kHz ARM7TDMI CPU – 32-bit Core – AMBA (AHB-APB) bus configuration Patch RAM capability Memory organization – On chip RAM, including provision for patches – On chip ROM, preloaded with SW up to HCI Communication interfaces – Fast UART – PCM interface – 4 programmable GPIOs – External interrupts possible through the GPIOs – Fast master I2C interface Efficient support for WLAN coexistence in collocated scenario Ciphering support up to 128 bits key Software support – Lower level stack (up to HCI) – HCI Transport Layer: H4 (including propri- Figure 1. Package TFBGA84 Table 1. Order Codes ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Part Number Package STLC2500 TFBGA84 etary extensions) – HCI proprietary commands (e.g. peripherals control) – Single HCI command for patch/upgrade download Single power supply with internal regulators for core voltage generation Supports 1.65 to 2.85 Volts IO systems Total number of external components limited to 7 (6 decoupling capacitors and 1 filter) thanks to: – Fully integrated synthesizer (VCO and loop filter) – Integrated antenna switch – Low IF receiver Auto calibration (VCO, Filters) No need for calibration of the RF part Timer and watchdog Power class 2 compatible Ultra low power architecture with 3 different low power levels: – Sleep Mode – Deep Sleep Mode – Complete Power Down Mode Software Initiated Low Power Mode Dual Wake-up mechanism: initiated either by the Host or by the Bluetooth device Standard TFBGA-84 pins package 2 DESCRIPTION The STLC2500 is a single chip ROM-based Bluetooth solution implemented in 0.13 m ultra low power, low leakage CMOS technology for applications requiring integration up to HCI level. Patch RAM is available enabling multiple patches/upgrades. The STLC2500's main interfaces are UART for HCI transport, PCM for voice and GPIOs for control purposes. The Radio is designed for the single chip requirement and for drastic power consumption reduction. May 2004 This is preliminary information on a new product now in development. Details are subject to change without notice. REV. 1 1/23 STLC2500 3 QUICK REFERENCE DATA VDD_IO_x means VDD_IO_A, VDD_IO_B. (See also table 13 subsection Power supply.) 3.1 Absolute Maximum Ratings The Absolute Maximum Rating (AMR) corresponds to the maximum value that can be applied without leading to instantaneous or very short-term unrecoverable hard failure (destructive breakdown). Table 2. Absolute Maximum Ratings Symbol VDD_HV VDD_IO_x Vssdiff Min. Max. Unit Regulator input supply voltage Parameter Vss - 0.3 4.0 V Supply voltage I/O Vss - 0.3 4.0 V -0.3 0.3 V Maximum voltage difference between different types of VSS pins Vin Input voltage of any digital pin Tstg Storage temperature Tlead Lead temperature <10s Vss - 0.3 4.0 V -65 +150 °C +250 °C VSS can be any VSS_xxx pin. 3.2 Operating Ranges Operating ranges define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied. Table 3. Operating ranges Symbol Parameter Min. Tamb Operating ambient temperature -40 VDD_HV Regulator input supply voltage (*) 2.65 Typ. Max. +85 2.75 2.85 Unit ° C (*) V VDD_IO_A Supply voltage for I/O 1.65 2.85(**) V VDD_IO_B Supply voltage for I/O 1.35 2.85(**) V (*) The chip will be characterized from 2.62 [V] up to 2.9 [V]. (**) The chip will be characterized up to 2.9 [V]. 3.3 I/O specifications The I/Os comply with the EIA/JEDEC standard JESD8-B. Table 4. DC Input specification (all digital I/Os except system clock) Symbol Parameter VIL Low Level input voltage VIH High Level input voltage Vhyst Min. Typ. Max. Unit 0.35 * VDD_IO_x V 0.65 * VDD_IO_x Schmitt trigger hysteresis V 0.4 0.5 0.6 V Min. Typ. Max. Unit 0.15 V Table 5. DC Output specification Symbol Parameter Condition VOL Low Level output voltage Id = X mA VOH High Level output voltage Id = X mA VDD_IO_x - 0.15 Note: X is the source/sink current under worst-case conditions according to the drive capabilities (see section 5) 2/23 V STLC2500 3.4 Clock specifications The STLC2500 supports, on the same input pin, the system clock both as a sine wave clock and as a digital clock (see table 15 for selection). The system clock section is powered by VDD_CLD (G08 and H09). The voltage range for VDD_CLD is the same as for VDD_IO_A. Table 6. System clock supported frequencies Symbol FIN Parameter Clock input frequency list Values Unit 13, 26, 19.2, 38.4 MHz Table 7. System clock overall specifications Symbol FINTOL Parameter Min. Tolerance on input frequency Typ. -20 Max. Unit 20 ppm Max. Unit Table 8. System clock, sine wave specifications Symbol Parameter VPP Peak to peak voltage range NH Total harmonic content of input signal ZINRe Min. Typ. 0.2 0.5 Real part of parallel input impedance at pin 30 60 1 V -25 dBc 90 KΩ Table 9. System clock, digital clock DC specifications Symbol Parameter VIL Low Level input voltage VIH High Level input voltage Min. Typ. Max. Unit 0.22 * VDD_IO_A V 0.85 * VDD_IO_A V Table 10. System clock, digital clock AC specifications Symbol Typ. Max. Unit TRISE 10%-90% rise time 1,5 6 ns TFALL 90%-10% fall time 1,5 6 ns 50 55 % DCYCLE Parameter Duty Cycle Min. 45 Table 11. Low Power clock specifications The low power clock pin is powered by connecting VDD_IO_B to the wanted supply. Symbol Parameter Duty Cycle Accuracy Min. 30 Typ. Max. Unit 70 % ±250 ppm 3/23 STLC2500 3.5 Current Consumption Table 12. Typical current consumption (Tamb = 25°C, 26 MHz digital clock, 1.8 Volts at I/Os) STLC2500 state Value Unit Complete Power Down 6 µA Deep Sleep Mode 25 µA Sleep Mode 1.4 mA Page/Inquiry scan (1,28 seconds period), combined with Deep Sleep Mode 0.4 mA Active: audio (HV3) 10.9 mA Active: data (DH1) (172,8 Kbps symmetrical) 21.8 mA Active: audio eSCO (EV3), (64 Kbps symmetrical TSCO=6) 11.3 mA Active: audio eSCO (EV5), (64 Kbps symmetrical TSCO=12) 9.6 mA Active: audio eSCO (EV5), (64 Kbps symmetrical TSCO=18) 9.1 mA Active: audio eSCO (EV5), (64 Kbps symmetrical TSCO=24) 8.9 mA Active: audio eSCO (EV5), (64 Kbps symmetrical TSCO=36) 8.5 mA Continuous RX, RF sub chip only. 34 mA Continuous TX, RF sub chip only at 2.5 dBm output power. 32 mA 4 BLOCK DIAGRAM AND ELECTRICAL SCHEMA Figure 2. The complete chip EMU 2.75V VDD_IO 1.2V 2.5V (1.8-2.75V) Internal Supply Management JTAG ARM7TDMI CPU Wrapper Demo- LP_CLK RAM RFP RF PLL (FracN) Filter RFN Control & Registers ModuTransmitter lator Auto Calib. RF_CLK_IN Baseband Core EBC dulator HOST_WAKEUP ROM UART AMBA Timer Peripheral Interrupt Bus PCM BT_WAKEUP RESETN UART [3:0] PCM [3:0] Sq. PLL WLAN I2C 4/23 Input / Output Receiver JTAG [4:0] CONFIG [4:0] GPIO [3:0] STLC2500 5 5.1 PINOUT Pin out bottom view 10 9 ANA_1 ABUS_ QP_IP 8 7 VSS_ANA VSS_ANA ANA_3 VDD_HV VSS_ANA VDD_HV ANA_4 VSS_ANA VSS_DIG JTAG_TCK JTAG_TMS VDD_DSM VSS_ANA VSS_ANA VSS_DIG PCM_SYNC PCM_CLK VDD_N VDD_HV VSS_ANA VDD_IO_A PCM_A PCM_B VDD_CL VSS_ANA VDD_CLD VSS_DIG VDD_IO_A VDD_IO_A RF_CLK_IN VDD_CLD VSS_DIG VSS_DIG VSS_DIG VSS_DIG VSS_DIG CONFIG _R CONFIG _CLK CONFIG _JS ABUS_ IN_QN 6 5 4 3 2 1 VSS_RF RFN RFP VSS_RF VDD_HV VSS_ANA VSS_DIG ABUS_ IP_QP VSS_ ANA VDD_RF ANA_2 VSS_ANA VDD_DIG JTAG_TDO VSS_ANA VDD_T VSS_ANA VSS_ANA VDD_DIG JTAG_ NTRST JTAG_TDI A ABUS_ QN_IN B C D E F G H VDD_DIG GPIO_2 GPIO_0 UART_ RXD UART_ CTS HOST_ WAKEUP CONFIG _RF BT_ WAKEUP VDD_DIG CONFIG _M AF_PRG GPIO_3 PGIO_1 UART_ TXD UART_ RTS LP_CLK VDD_IO_B RESETN VDD_D VDD_HV J K 5.2 Pin Description and Assignment Table 13 shows the pin list of the STLC2500. The column "PU/PD" shows the pads implementing a pulldown/up. The column "DIR" describes the pin directions: – I for Inputs – O for Outputs – I/O for Input/Output – O/t for tri-state outputs The column Reset and Default show the state of the pins in reset and the default value after reset. For the output pin the default drive capability is 2 mA. Table 13. STLC2500 pin list (Functional and Supply) Name Pin # Description DIR Reset Default after reset VDD_ IO_x I I I Input Input Input Input Input Input (3) Clock and Reset pins RESETN RF_CLK_IN LP_CLK K03 H10 K05 Global reset - active low Reference clock input Low power clock input A B 5/23 STLC2500 Table 13. STLC2500 pin list (Functional and Supply) - continued Name Pin # Description SW initiated Low Power mode HOST_WAKEUP J05 Wake-up signal to host DIR Reset I/O Input PD Default after reset VDD_ IO_x B BT_WAKEUP J03 Wake-up signal to Bluetooth I Input (2) Output high Input UART interface UART_RXD J07 UART receive data I Input PD Input A UART_TXD K07 UART transmit data O/t (I/O) J06 UART clear to send I Output high Input A UART_CTS Tri-state PD Input PU A A (2) UART_RTS K06 UART Request to send O/t (I/O) Tri-state PU Output low A PCM interface PCM_SYNC PCM_CLK PCM_A PCM_B JTAG interface JTAG_TDI JTAG_TDO E02 E01 F02 F01 PCM frame signal PCM clock signal PCM data PCM data I/O I/O I/O I/O Input PD Input PD Input PD Input PD Input PD Input PD Input PD Input PD A A A A C01 B01 JTAG data input JTAG data output I O/t Input PU Tri-state A A JTAG_TMS JTAG_NTRST JTAG_TCK D01 C02 D02 JTAG mode signal JTAG reset active low JTAG clock input Input PU Tri-state PD Input PU Input PD Input (1) Input PU Input PD Input A A A I I I General purpose Input/Output pins GPIO_0 J08 GPIO_1 K08 GPIO_2 J09 GPIO_3 K09 Configuration pins CONFIG_JS H01 CONFIG_CLK H02 CONFIG_R H03 CONFIG_M J01 CONFIG_RF J04 RF signals RFP RFN Power supply VDD_HV VDD_D 6/23 A05 A06 A03 C09 D10 F09 K01 K02 General purpose IO General purpose IO General purpose IO General purpose IO I/O I/O I/O I/O Input PD Input PD Input PD Input PD Input PD Input PD Input PD Input PD A A A A Configuration signal Configuration signal Configuration signal Configuration signal Configuration signal I I I I I Input Input Input Input Input Input Input Input Input Input A A A A A Differential RF port I/O I/O Power supply (Connect all to 2.75V) Output regulator for core logic STLC2500 Table 13. STLC2500 pin list (Functional and Supply) - continued Name VDD_DIG VDD_IO_A VDD_IO_B Pin # B02 C03 J02 J10 F03 G02 G01 K04 G08 VDD_CLD H09 VDD_DSM VDD_N VDD_CL E10 F10 G10 VDD_RF B05 A01 D03 E03 G03 H04 H05 H06 H07 H08 VSS_DIG VSS_ANA VSS_RF (1) (2) (3) A02 B03 B06 B09 B10 C04 C05 C07 C08 D08 E08 E09 F08 G09 A04 A07 Description DIR Reset Default after reset VDD_ IO_x Core logic supply (Connect all to VDD_D) 1.65V to 2.85V I/Os supply (Connect all) 1.35V to 2.85V I/Os supply System clock supply 1.65V to 2.85V (Connect all to VDD_IO_A in case of a digital reference clock input, to VSS_ANA in case of an analogue reference clock input) Internal supply decoupling Internal supply decoupling Internal supply decoupling Internal supply decoupling Digital ground Analogue ground RF ground Should be strapped to VSS_DIG if not used Should be strapped to VDD_IO_A if not used See also pin VDD_CLD in table 13 7/23 STLC2500 Table 14. STLC2500 pin list (Test) Name Analogue test pin VDD_T ABUS_IN_QN PIN # Description DIR Reset Default C06 A08 Test supply Test pin I/O Input (1) Input (1) ABUS_QP_IP A09 Test pin I/O Input (1) Input (1) ABUS_IP_QP B07 Test pin I/O Input (1) Input (1) ABUS_QN_IN B08 Test pin I/O (1) Input (1) ANA_1 A10 ANA_2 B04 ANA_3 C10 ANA_4 D09 AF_PRG K10 Analogue test pin (Leave unconnected) Analogue test pin (Leave unconnected) Analogue test pin (Leave unconnected) Analogue test pin (Leave unconnected) Test pin (Leave unconnected) I/O Input Open VDDIO Open (1) To be strapped to VSS_ANA Table 15. STLC2500 pin list (Configuration) The configuration pins are used to select different modes of operation for the chip: Digital or analogue incoming system clock CONFIG_CLK =’1’ The incoming system clock is a digital square signal. (See chapter 3.4.) CONFIG_CLK =’0’ The incoming system clock is a sine wave signal. (See chapter 3.4.) Initiated Low Power modes CONFIG_JS =’0’ AND CONFIG_M = ‘0’ Reserved CONFIG_JS =’0’ AND CONFIG_M = ‘1’ Initiated low power, mode 1. (See chapter 7.8.) CONFIG_JS =’1’ AND CONFIG_M = ‘0’ Initiated low power, mode 2. (See chapter 7.8.) CONFIG_JS =’1’ AND CONFIG_M = ‘1’ Reserved Where '1' means VDD_IO_A and '0' means VSS_DIG. The other two configuration pins, CONFIG_RF and CONFIG_R have to be strapped to VSS_DIG. 6 FUNCTIONAL DESCRIPTION 6.1 Transmitter The transmitter uses the serial transmit data from the baseband. The transmitter modulator converts this data into GFSK modulated I and Q digital signals. These signals are then converted to analogue signals that are low pass filtered before up-conversion. The carrier frequency drift is limited by a closed loop PLL. 6.2 Receiver The STLC2500 implements a low-IF receiver for Bluetooth modulated input signals. The radio signal is taken from a balanced RF input and amplified by an LNA. The mixers are driven by two quadrature LO signals, which are locally generated from a VCO signal running at twice the frequency. The I and Q mixer output signals are band pass filtered by a poly-phase filter for channel filtering and image rejection. The 8/23 STLC2500 output of the band pass filter is amplified by a VGA to the optimal input range for the A/D converter. Further channel filtering is done in the digital part. The digital part demodulates the GFSK coded bit stream by evaluating the phase information in the digital I and Q signals. RSSI data is extracted. Overall automatic gain amplification in the receive path is controlled digitally. The RC time constants for the analogue filters are automatically calibrated on chip. 6.3 PLL The on-chip VCO is part of a PLL. The tank resonator circuitry for the VCO is completely integrated without need of external components. Variations in the VCO centre frequency are calibrated out automatically. 6.4 Baseband 1.1 Features The baseband is based on Ericsson Licensing Technology Baseband Core (EBC) and it is compliant with the Bluetooth specification 1.1: – Point to multipoint (up to 7 Slaves) – Asynchronous Connection Less (ACL) link support giving data rates up to 721 kbps – Synchronous Connection Oriented (SCO) link with support for 2 voice channels over the air interface – Flexible voice format to Host and over the air (CVSD, PCM 13/16 bits, A-law, µ-law) – HW support for packet types: DM1, 3, 5; DH1, 3, 5; HV1, 3; DV – Scatternet capabilities (Master in one piconet and Slave in the other one; Slave in two piconets). All scatternet v.1.1 errata supported – Ciphering support up to 128 bits key – Paging modes R0, R1, R2 – Channel Quality Driven Data Rate – Full Bluetooth software stack available – Low-level link controller 6.5 Baseband 1.2 Features The baseband part is also compliant with the Bluetooth specification 1.2: – Adaptive Frequency Hopping (AFH): hopping kernel, channel assessment as Master and as Slave – Faster Connection: Interlaced scan for Page and Inquiry scan, answer FHS at first reception, RSSI used to limit range – Extended SCO (eSCO) links: supports EV3 and EV5 packets – QoS Flush – Synchronization: BT clocks are available at HCI level for synchronization of parallel applications on different Slaves – L2CAP Flow & Error control – LMP improvements – LMP SCO handling – Parameter Ranges update 6.5.1 V1.2 detailed functionality - Extended SCO User Perspective - Extended SCO This function gives improved voice quality since it enables the possibility to retransmit lost or corrupted voice packets in both directions. Technical perspective - Extended SCO eSCO incorporates CRC, negotiable data rate, negotiable retransmission window and multi-slot packets. Retransmission of lost or corrupted packets during the retransmission window guarantees on-time delivery. 9/23 STLC2500 Figure 3. eSCO SCO SCO SCO SCO ACL ACL SCO SCO t eSCO retransmission window 6.5.2 V1.2 detailed functionality - Adaptive Frequency Hopping User Perspective - Adaptive Frequency Hopping In the Bluetooth spec 1.1, the Bluetooth devices hop in the 2.4 GHz band over 79-channels. As WLAN 802.11 has become popular, there are improvements in the Bluetooth spec 1.2 specifying how Bluetooth units can avoid jammed bands and provide an improved co-existence with WLAN. Technical perspective - Adaptive Frequency Hopping Figure 4. AFH f AFH(79) WLAN used frequency t f AFH(19<N<79) WLAN used frequency t First the Master and/or the Slaves identify the jammed channels. The Master decides on the channel distribution and informs the involved slaves. The Master and the Slaves, at a predefined instant, switch to the new channel distribution scheme. No longer jammed channels are re-inserted into the channel distribution scheme. AFH uses the same hop frequency for transmission as for reception. 6.5.3 V1.2 detailed functionality - Faster Connection User Perspective - Faster Connection This feature gives the User about 65% faster connection on average when enabled compared to Bluetooth spec 1.1 connection procedure. 10/23 STLC2500 Technical perspective - Faster Connection The Faster Inquiry functionality is based on a removed/shortened random back off and also a new Interlaced Inquiry Scan scheme. The Faster Page functionality is based on Interlaced Page Scan. 6.5.4 V1.2 detailed functionality - Quality of Service User Perspective - Quality of Service Small changes to the BT1.1 spec regarding Quality of Service make a large difference. Allowing all QoS parameters to be communicated over HCI to the link manager enables efficient bandwidth management. Here after a short list of user perspectives: 1) Flush timeout: enables time-bounded traffic such as video streaming to become more robust when the channel degrades. It sets the maximum delay of an L2CAP frame. It does not enable multiple streams in one piconet, or heavy data transfer at the same time. 2) Simple latency control: allows the Host to set the poll interval. This provides support for HID devices mixed with other traffic in the piconet. 6.6 Processor and memory – ARM7TDMI – On chip RAM, including provision for patches – On chip ROM, preloaded with SW up to HCI 7 GENERAL SPECIFICATION All the provided values are specified over the operational conditions (VDD and temperature) according to the Bluetooth 1.1 and 1.2 specifications unless otherwise specified. 7.1 Receiver To be compliant with the Bluetooth norm, an external RF filter is required to provide minimum -17dB of attenuation in the band: 30MHz - 2000MHz and 3000MHz - 12.75GHz. All specifications below are given at pin level and over temperature unless otherwise specified. Table 16. Receiver Parameters (Tamb = 25°C, VDD_HV = 2.75V, parameters are given at device pin.) Symbol RFin Parameter Test Condition Input frequency range Min. Typ. 2402 Max. Unit 2480 MHz RXsens Receiver Sensitivity (Clean transmitter) @ BER 0.1% -85 dBm RXmax Maximum useable input signal level @ BER 0.1% +15 dBm Receiver interferer performance @BER 0.1% C/Ico-channel Co-channel interference @ Input signal strength = -60dBm 9 dB C/I1MHz Adjacent (±1MHz) interference @ Input signal strength = -60dBm -2 dB C/I+2MHz Adjacent (+2MHz) interference @ Input signal strength = -60dBm -35 dB C/I-2MHz Adjacent (-2MHz) interference @ Input signal strength = -67dBm -25 dB 11/23 STLC2500 Table 16. Receiver Parameters (Tamb = 25°C, VDD_HV = 2.75V, parameters are given at device pin.) Symbol Parameter Test Condition Min. Typ. Max. Unit C/I+3MHz Adjacent (+3MHz) interference @ Input signal strength = -67dBm -44 dB C/I-3MHz Adjacent (-3MHz) interference @ Input signal strength = -67dBm -37 dB C/I≥4MHz Adjacent (≥±4MHz) interference @ Input signal strength = -67dBm -46 dB Measured as defined in BT test specification. -35 dBm Receiver inter-modulation IMD Inter-modulation 7.2 Transmitter All output power specifications are given at the pin level and over temperature range unless otherwise specified. Table 17. Transmitter Parameters (Tamb = 25°C, VDD_HV = 2.75V, parameters are given at device pin.) Symbol Parameter RFout Output frequency range TXpout Nominal Output power Test Condition Min. Typ. 2402 @2402-2480 MHz 0 3 Max. Unit 2480 MHz 5 dBm In-band spurious emission FCC FCC’s 20 dB BW 932 kHz TX_SE2 Channel offset=2 -51 dBm TX_SE3 Channel offset=3 -55 dBm TX_SE4 Channel offset≥4 (except 13) -57 dBm Initial carrier frequency tolerance (for an exact reference) ∆F |f_TX-f0| -75 75 kHz One slot packet 25 kHz |∆f_p3| Three slots packet 40 kHz |∆f_p5| Five slots packet 40 kHz 20 kHz/µs Carrier Frequency Drift |∆f_p1| Carrier Frequency Drift rate |∆f/50us| Frequency drift rate 7.3 System clock The STLC2500 works with a single clock (sine wave or digital) provided on the RF_CLK_IN pin. Precision of this clock should be 20 ppm. The external STLC2500 clock could be 13 or 26 MHz (for GSM application), 19.2 MHz and 38.4 MHz (for 2.5 & 3G & CDMA platforms). 7.4 Low power clock The low power clock is used by the baseband part as reference clock during the low power modes. It requires an accuracy of 250ppm. The external STLC2500 clock, provided on the LP_CLK digital pin could be 3.2 kHz, 16.384 kHz, 32 kHz and 32.768 kHz. The low power clock must be available at all times. 7.5 Clock detection The system and low power clocks can be either selected by specific HCI command or by integrated automatic detection algorithm. The clock detection routine steps are: 12/23 STLC2500 – Identification of the system clock frequency (13 MHz, 26MHz, 19.2 MHz or 38.4 MHz) – Identification of the low power clock (3.2 KHz, 16.384 KHz, 32 KHz or 32.768 KHz) Remark: The STLC2500 assumes that the low power clock is available at all times. 7.6 Interrupts The user can program the GPIOs as external interrupt sources. 7.7 Low power modes To save power, three low power modes are supported. Depending of the Bluetooth and of the Host's activity, the STLC2500 autonomously decides to use Deep Sleep Mode, Sleep Mode or active mode. Complete Power Down is entered only after an explicit command from the Host. Table 18. Low power modes Low power mode Description Sleep Mode The STLC2500: - Accepts HCI commands from the Host. - Supports all types of Bluetooth links. - Can transfer data over Bluetooth links. - Dynamically switches between sleep and active mode when needed. - The system clock is still active in part of the design. - Parts of the chip can be dynamically powered off depending on the Bluetooth activity. Deep Sleep Mode The STLC2500: - Does not accept HCI commands from the Host. - Supports page- and inquiry scans. - Supports Bluetooth links that are in Sniff, Hold or Park. - Does not transfer data over Bluetooth links. - Dynamically switches between deep sleep and active mode during Bluetooth activity. - The system clock is not active in any part of the design. - Parts of the chip can be dynamically powered off depending on the Bluetooth activity. Complete Power Down The STLC2500 is effectively powered down: - No Bluetooth activity is supported. - The HCI interface is shut down. - The system clock is not active in any part of the design. - Most parts of the chip are completely powered off. - RAM content is not maintained (initialisation is required at wakeup). Some examples for the usage of the low power modes: 7.7.1 SNIFF OR PARK The STLC2500 is in active mode with a Bluetooth connection, once the connection is concluded, SNIFF or PARK is programmed. Once one of these two states is entered, the STLC2500 goes into Sleep Mode. After that, the Host may decide to place the STLC2500 in Deep Sleep Mode by putting the UART LINK in low power mode. The Deep Sleep Mode allows for lower power consumption. When the STLC2500 needs to send or receive a packet (e.g. at TSNIFF or at the beacon instant), it requires the clock and it goes into active mode for the needed transmission/reception. Immediately afterwards, it will go back to Deep Sleep Mode. If some HCI transmission is needed, the UART link will be reactivated, using one of the two ways explained in 7.8, and the STLC2500 will move from Deep Sleep Mode to Sleep Mode. 7.7.2 INQUIRY/PAGE SCAN When only inquiry scan or page scan is enabled, the STLC2500 will go in Sleep Mode or Deep Sleep Mode outside the receiver activity. The selection between Sleep Mode and Deep Sleep Mode depends on the UART activity like in SNIFF or PARK. 13/23 STLC2500 7.7.3 NO CONNECTION If the Host places the UART in low power and there is no activity, then the STLC2500 can be placed in Deep Sleep Mode. In this mode (no connection), the Host can also decide to put the STLC2500 in Complete Power Down to further reduce the power consumption. In this case some part of the STLC2500 will be completely powered off. It's possible to exit the Complete Power Down by using one of the two methods explained in 7.8. The request to quit the Complete Power Down may be done with an HW reset or it may come from the Host. 7.7.4 ACTIVE LINK When there is an active link (SCO or ACL), the STLC2500 can go neither in Deep Sleep Mode nor in Complete Power Down whatever the UART state is. But the STLC2500 baseband is made such that whenever it is possible, depending on the scheduled activity (number of link, type of link, amount of data exchanged), it goes in Sleep Mode. 7.8 SW initiated low power mode During periods of no activity either on the Bluetooth or on the Host side, the chip can be placed in low power mode. Two modes to initiate low power mode and to wake up are supported (selection is done through pin configuration, see table 15): 1 [Initiated Low power, mode 1] It requires HOST_WAKEUP, UART_RXD (connected with BT_WAKEUP, the two paths will be physically connected on the board) and UART_RTS. The UART_RXD is used as wakeup signal from the host, the HOST_WAKEUP requires the clock from the Host and the UART_RTS indicates when the controller is available. In this mode, the break function (UART_RXD is low for more than 1 word) is used to distinguish between normal operation and low power mode usage. The system goes in low power mode in this way: the Host tells the Bluetooth device that it can go in low power by forcing the UART_RXD of the Bluetooth device to '0' for more than 1 word. Then, the device can decide whether to go in low power mode or not depending on its scheduled activity. In case it decides to go in low power mode, it signals it by forcing UART_RTS high; then it asserts HOST_WAKEUP low to tell the Host that it does not need the clock anymore. The Bluetooth baseband cannot go in sleep mode by itself. This is a logical consequence of the fact that the system clock is needed to receive characters on the UART and only the Host can stop the UART link. - The system wakes up in this way: the Bluetooth baseband first asks the Host to restart the system clock by setting HOST_WAKEUP to '1'. When the clock is available, the device sets UART_RTS low, and then the Host can give confirmation by releasing the UART_RXD of the device. In case the Host wants to wake up the chip, it sets the UART_RXD pin of the Bluetooth device to '1'. The device then confirms it is awake by releasing UART_RTS to '0'. 2 [Initiated Low power, mode 2] It requires HOST_WAKEUP, BT_WAKEUP, UART_RTS and UART_CTS. The wakeup is always initiated by HOST_WAKEUP or BT_WAKEUP signal (the peer acknowledges the request). UART_RTS and UART_CTS are placed at the value for which they block the UART communication. - The system goes in low power in this way: the Host sets BT_WAKEUP to '0', telling the Bluetooth device that it can go in low power. The device can decide whether to go in low power mode or not depending on its scheduled activity. If it decides to go in low power it first asserts UART_RTS pin to '1' and then it sets HOST_WAKEUP to '0' to tell the Host that it does not need the system clock anymore. The Host confirms by setting UART_CTS to '1' and by stopping the clock. - The system wakes up in this way: the Bluetooth device sets HOST_WAKEUP to '1' to tell the Host that it needs the clock. The Host delivers the clock, when the device is ready it releases UART_RTS to '0'. Then the Host confirms by asserting BT_WAKEUP to '1' and by releasing UART_CTS to '1'. If the Host wakes up first, it tells it to the Bluetooth device by setting BT_WAKEUP to '1'. The Bluetooth device sets HOST_WAKEUP to '1' and then UART_RTS and UART_CTS are released by device and Host respectively to tell they are ready to start communicating. 14/23 STLC2500 7.9 Patch RAM The STLC2500 includes a HW block that allows patching of the ROM code. Additionally, a SW patch mechanism allows replacing complete SW functions without changing the ROM image. A part of the RAM memory is used for HW and SW patches. 7.10 Download of SW parameters To change the device configuration a set of customizable parameters have been defined and put together in one file. This file is downloaded at start-up into the STLC2500. Examples of parameters are: radio configuration, PCM settings etc. The same HCI command is used to download the file containing the patches (both those for the SW and HW mechanism). A more detailed description of the SW parameters is available upon request. 7.11 Bluetooth - WLAN coexistence in collocated scenario Bluetooth and WLAN 802.11 b/g technologies occupy the same 2.4 GHz ISM band. STLC2500 implements a set of mechanisms to avoid interference in a collocated scenario. The STLC2500 supports 5 different algorithms in order to provide efficient and flexible simultaneous functionality between the two technologies in collocated scenarios: – Algorithm 1: PTA (Packet Traffic Arbitration) based coexistence algorithm defined in accordance with the IEEE 802.15.2 recommended practice. – Algorithm 2: the WLAN is the master and it indicates to the STLC2500 when not to operate in case of simultaneous use of the air interface. – Algorithm 3: the STLC2500 is the master and it indicates to the WLAN chip when not to operate in case of simultaneous use of the air interface. – Algorithm 4: Two-wire mechanism – Algorithm 5: Alternating Wireless Medium Access (AWMA), defined in accordance with the WLAN 802.11 b/g technologies. The algorithm is selected via HCI command. The default algorithm is algorithm 1. 7.11.1 Algorithm 1: PTA (Packet Traffic Arbitration) The Algorithm is based on a bus connection between the STLC2500 and the WLAN chip: STLC2500 WLAN By using this coexistence interface it's possible to dynamically allocate bandwidth to the two devices when simultaneous operations are required while the full bandwidth can be allocated to one of them in case the other one does not require activity. The algorithm involves a priority mechanism, which allows preserving the quality of certain types of link. A typical application would be to guarantee optimal quality to the Bluetooth voice communication while an intensive WLAN communication is ongoing. Several algorithms have been implemented in order to provide a maximum of flexibility and efficiency for the priority handling. Those algorithms can be activated via specific HCI commands. The combination of a time division multiplexing techniques to share the bandwidth in case of simultaneous 15/23 STLC2500 operations and of the priority mechanism avoid the interference due to packet collision and it allows the maximization of the 2.4 GHz ISM bandwidth usage for both devices while preserving the quality of some critical types of link. 7.11.2 Algorithm 2: WLAN master In case the STLC2500 has to cooperate, in a collocated scenario, with a WLAN chip not supporting a PTA based algorithm, it's possible to put in place a simpler mechanism. The interface is reduced to 1 line: RF_NOT_ALLOWED STLC2500 WLAN When the WLAN has to operate, it alerts HIGH the RF_NOT_ALLOWED signal and the STLC2500 will not operate while this signals stays HIGH. This mechanism permits to avoid packet collision in order to make an efficient use of the bandwidth but cannot provide guaranteed quality over the Bluetooth links. 7.11.3 Algorithm 3: Bluetooth master This algorithm represents the symmetrical case of section 7.11.2. Also in this case the interface is reduced to 1 line: RF_NOT_ALLOWED STLC2500 WLAN When the STLC2500 has to operate it alerts HIGH the RF_NOT_ALLOWED signal and the WLAN will not operate while this signals stays HIGH. This mechanism permits to avoid packet collision in order to make an efficient use of the bandwidth, it provides high quality for all Bluetooth links but cannot provide guaranteed quality over the WLAN links. 7.11.4 Algorithm 4: Two-wire mechanism Based on algorithm 2 and 3, the Host decides, on a case-by-case basis, whether WLAN or Bluetooth is master. 7.11.5 Algorithm 5: Alternating Wireless Medium Access (AWMA) AWMA utilizes a portion of the WLAN beacon interval for Bluetooth operations. From a timing perspective, the medium assignment alternates between usage following WLAN procedures and usage following Bluetooth procedures. The timing synchronization between the WLAN and the STLC2500 is done by the HW signal MEDIUM_FREE. Table 19. WLAN HW signal assignment Scenario 1: PTA Scenario 2: WLAN master Scenario 3: BT master Scenario 4: 2-wire Scenario 5: AWMA WLAN 1 TX_ CONFIRM BT_RF_NOT_ ALLOWED Not used BT_RF_NOT_ ALLOWED MEDIUM_FREE WLAN 2 TX_ REQUEST Not used WLAN_RF_ NOT_ ALLOWED WLAN_RF_ NOT_ ALLOWED Not used WLAN WLAN 3 STATUS Not used Not used Not used Not used WLAN 4 OPTIONAL_ SIGNAL Not used Not used Not used Not used 16/23 STLC2500 8 DIGITAL INTERFACES 8.1 The UART interface The STLC2500 contains a 4-pin (UART_RXD, UART_TXD, UART_RTS, and UART_CTS) UART compatible with 16450, 16550 and 16750 standards. It is running up to 1842 kbps (+1.5%/-1%). The configuration is 8 data bits, 1 start bit, 1 stop bit, and no parity bit. 128-byte FIFO with configurable threshold interrupts for low CPU load and high throughput. Auto RTS/CTS is implemented in HW, controllable by SW. The UART accepts all HCI commands as described in the Bluetooth specification, it supports H4 proprietary commands and the 4-wire UART sleep mode. The complete list of supported proprietary HCI commands is available in the STLC2500 Software Interface document. Table 20 contains the list of supported baud rates selectable by HCI commands. The default baud rate is 115200 [bps]. Table 20. List of supported baud rates Baud rate 1842 k 57.6 k 4800 921.6 k 38.4 k 2400 460.8 k 28.8 k 1800 230.4 k 19.2 k 1200 153.6 k 14.4 k 900 115.2 k (default) 9600 600 76.8 k 7200 300 8.2 The PCM interface The chip contains a 4-pin (PCM_CLK, PCM_SYNC, PCM_A, and PCM_B) direct voice interface to connect to standard CODEC including internal decimator and interpolator filters. The implementation is compliant with the MP-PCM requirements for voice transfer (8 kHz PCM_SYNC and 8 or 16 bits data). The four signals of the PCM interface are: – PCM_CLK: PCM clock – PCM_SYNC: PCM 8KHz sync – PCM_A: PCM data – PCM_B: PCM data The data can be linear PCM (13-16 bit), µ-Law (8 bit) or A-Law (8bit). The interface can be programmed as Master or as Slave via specific HCI commands. Two additional PCM_SYNC signals can be provided via the GPIOs. See section 8.4 for more details. Figure 5. PCM (A-law, µ-law) standard mode 0 1 15 PCM_CLK PCM_SYNC PCM_A PCM_B 125 µs 17/23 STLC2500 Figure 6. Linear mode PCM_CLK 0 1 15 PCM_SYNC PCM_A PCM_B 125 µs Figure 7. Multi-slot operation 0 1 15 PCM_CLK P_SYNC_DELAY PCM_SYNC DATA SIZE PCM_A PCM_B 125 µs The PCM implementation supports from 1 up to 3 slots per frame with the following parameters: Table 21. PCM interface parameters Symbol Description Min. Typ. Max. Unit 4000 kHz PCM Interface FPCM_CLK Frequency of PCM_CLK 140 FPCM_SYNC Frequency of PCM_SYNC Psync_delay Pclk_number Ss 18/23 8 kHz Delay of the starting of the first slot 0 255 cycles Available PCM_CLK clock cycles 0 255 cycles Slot starts (programmable for every slot) 0 255 cycles bit D Data size 8 16 N Number of slots per frame 1 3 STLC2500 Table 22. PCM interface timing Symbol Description Min. Typ. Max. Unit tWCH High period of PCM_CLK 200 ns tWCL Low period of PCM_CLK 200 ns tWSH High period of PCM_SYNC 200 ns tSSC Setup time, PCM_SYNC high to PCM_CLK low 100 ns tSDC Setup time, PCM_A/B input valid to PCM_CLK low 100 ns tHCD Hold time, PCM_CLK low to PCM_A/B input valid 100 tDCD Delay time, PCM_CLK high to PCM_A/B output valid ns 150 ns Figure 8. PCM interface timing t WCL PCM_CLK t WCH t SSC PCM_SYNC t WSH t SDC t HCD PCM_A/B in MSB MSB-1 MSB-2 MSB-3 t DCD PCM_A/B out MSB MSB-1 MSB-2 MSB-3 8.3 The JTAG interface The JTAG interface is compliant with the JTAG IEEE Standard 1149.1. It allows both the boundary scan of the digital pins and the debug of the ARM7TDMI application when connected with the standard ARM7 developments tools. It is also used for the industrial test of the device. 8.4 The GPIOs The STLC2500 has 4 GPIO pins. They are fully programmable via specific HCI commands. They can be configured as input, output, interrupt with asynchronous or synchronous edge or level detection and/or wake-up. Also other functions are multiplexed on the GPIO pins. The alternative functions are – WLAN co-existence control – I2C interface – PCM synchronization; – GPIOs Some functions are mutually exclusive, as per table 23. 19/23 STLC2500 Table 23. GPIO multiplexing Multiplexed GPIOs WLAN (See also table 19.) I2C WLAN 1 I2C clock [I2C or GPIO] GPIO 0 WLAN 2 I2C data [I2C or GPIO] GPIO 1 WLAN 3 [PCM or GPIO] PCM sync 1 GPIO 2 WLAN 4 [PCM or GPIO] PCM sync 2 GPIO 3 PCM GPIO 8.5 The I2C interface The I2C interface (version 2.1) has been specified by Philips. The I2C interface is used to access I2C peripherals. The implemented interface is a fast master I2C; it has full control of the interface at all times. I2C slave functionality is not supported, forcing attached devices to be slave, otherwise bus contention will occur. 9 HCI UART TRANSPORT LAYER The UART transport Layer has been specified by the Bluetooth SIG and allows HCI level communication between a Bluetooth controller (STLC2500) and a Host (e.g. a GSM), via a serial line. The objective of this HCI UART Transport Layer is to make possible to use Bluetooth HCI over a serial interface between two UARTs on the same PCB. The HCI UART Transport Layer assumes that the UART communication is free from line errors. UART Settings The HCI UART Transport Layer uses the following settings for RS232: – Baud rate: configurable (default baud rate 115.2 [kbps]) – Number of data bits: 8 – Parity bit: no parity – Stop bit: 1 stop bit – Flow control: RTS/CTS – Flow-off response time: 3 ms Flow control with RTS/CTS is used to prevent temporary UART buffer overrun. It should not be used for flow control of HCI, since HCI has its own flow control mechanism for HCI commands, HCI events and HCI data. If CTS is high, then the Host/Bluetooth controller is allowed to send. If CTS is low, then the Host/Bluetooth controller is not allowed to send. The flow-off response time defines the maximum time from setting RTS low until the byte flow actually stops. The RS232 signals should be connected in a null-modem fashion, i.e. the local TXD should be connected to the remote RXD and the local RTS should be connected to the remote CTS and vice versa. Figure 9. UART Transport Layer BLUETOOTH HOST BLUETOOTH HCI HCI UART TRANSPORT LAYER 20/23 BLUETOOTH HOST CONTROLLER STLC2500 Figure 10. TFBGA84 Mechanical Data & Package Dimensions mm inch DIM. MIN. A 1.010 A1 0.150 A2 TYP. MAX. MIN. 1.200 0.040 TYP. MAX. 0.047 0.006 0.820 0.032 b 0.250 0.300 0.350 0.010 0.012 0.014 D 5.750 6.000 6.150 0.226 0.236 0.242 D1 E 4.500 5.750 E1 6.000 0.177 6.150 0.226 4.500 0.236 0.242 Body: 6 x 6 x 1.20mm 0.177 e 0.450 0.500 0.550 0.018 0.020 0.022 f 0.600 0.750 0.900 0.024 0.029 0.035 ddd OUTLINE AND MECHANICAL DATA 0.080 0.003 TFBGA84 Thin Profile Fine Pitch Ball Grid Array 7104670 B 21/23 STLC2500 Table 24. Revision History 22/23 Date Revision May 2004 1 Description of Changes First Issue STLC2500 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. The BLUETOOTH™ word mark and logos are owned by the Bluetooth SIG, Inc. and any use of such marks by STMicroelectronics is under license. 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