STLC60133 XDSL LINE DRIVER PRELIMINARY DATA ■ LOW NOISE : 4nV/ H z ■ HIGH PEAK OUTPUT CURRENT: 500 mA ■ HIGH SPEED – 140MHz Gain Bandwidth – 30MHz Gain Flatness – 400 V/us Slew Rate ■ HTSSOP28 LOW POWER OPERATION ORDERING NUMBER: STLC60133 – ±5V to ±15V Voltage Supply – 12.5 mA/Amp (typ) Supply current Temperature Range: -40°C to +85°C – Power reduced Current ■ LOW SINGLE TONE DISTORTION ■ THERMAL AND OVERLOAD PROTECTION ■ HTSSOP28 PACKAGE ■ -40 TO +85°C OPERATING RANGE Two digital pins (PWDN0 and PWDN1) allow the driver to work in full performance mode, in low-power mode or two intermediate bias states. DESCRIPTION The low-power mode biases the output stage in order to provide a low impedance at the amplifier outputs for back termination. The STLC60133 is a dual amplifier featuring a high slew rate and a large bandwidth optimized for XDSL applications. The device is available in a HTSSOP 28 pin package (4x9 mm) with an exposed leadframe. The STLC60133 is designed optimizing bandwidth and distortion performances. For proper device operating it is necessary to work with a gain level greater than 15.6dB. Thanks to its small package this line driver is suitable for high density ADSL line card. Typical differential gain is normally +27dB, while typical common mode gain is 15.6dB Figure 1. BLOCK DIAGRAM -VS IN1N - IN1P + +VS Op1 OUT1 PWDN0 PWDN1 LOGIC TH DETCT. BIAS DGND IN2N - IN2P + OUT2 Op2 D00TL462A October 2001 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/9 STLC60133 PIN CONNECTION RES 1 28 RES N.C. 2 27 N.C. N.C. 3 26 N.C. IN2P 4 25 N.C. IN2N 5 24 PWDN1 OUT2 6 23 BIAS +VS 7 22 -VS +VS 8 21 -VS OUT1 9 20 DGND IN1N 10 19 N.C. IN1P 11 18 PWDN0 N.C 12 17 N.C. N.C. 13 16 N.C. N.C. 14 15 N.C. D00TL463A ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VCC Positive Supply voltage (note1) +16.5 V VSS Negative Supply voltage (note1) -16.5 V Vid Differential Input Voltage (note2) ±5 V Vi Common mode Input Voltage ±1 V Top Operating Free Air Temperature Range -40 to +85 °C Tstg Storage temperature -65 to +150 °C Tj Junction temperature 150 °C Value Unit 29 °C/W THERMAL DATA Symbol Rthj-amb 2/9 Parameter Thermal resistance junction to ambient (note 3) STLC60133 OPERATING RANGE Symbol Parameter Value Unit Top Operating Temperature Range -40 to 85 °C VCC Positive Supply voltage (note1) +5 to +15 V VSS Negative Supply voltage (note1) -5 to -15 V VSS+5<VDGND<VCC-5 V ±1 V VDGND Digital Ground level Vicm Common Mode Input Voltage Range Notes 1) All voltages values , except differential voltage , are with respect to network ground terminal . 2) Differential voltages are non-inverting input terminal with respect to the inverting input terminal 3) Specification is for device on a 4 layer board within 10 square inches of oz. copper at +85°C and 200m/s air velocity. With 0m/s air velocity the parameter increases up to 33°C/W . PIN DESCRIPTION N° Pin Description 2, 3, 12, 13, 14, 15, 16, 17, 19, 25, 26, 27 NC 4 IN2P Non Inverting Input of Op. Amplifier 2 5 IN2N Inverting Input of Op. Amplifier 2 6 OUT2 Ouput of Op. Amplifier 2 7, 8 +Vs Positive Supply Voltage 9 OUT1 Ouput of Op. Amplifier 1 10 IN1N Inverting Input of Op. Amplifier 1 11 IN1P Non Inverting Input of Op. Amplifier 1 14 PWDN1 Power Down 1 logic input 18 PWDN0 Power Down 0 logic input 21, 22 -Vs Negative Supply Voltage 23 BIAS Bias Control pin 1, 28 RES To be left not connected Not Connected Power Down Management The STLC60133 provides several quiescent bias levels from full performance, to reduced bias (in three steps through PWDN0/1 pins) or to full OFF operation (through BIAS pin). According to the different XDSL application (both site CO and CPE), different bias levels can be chosen maintaining good MTPR performances. In the following table are shown the bias levels versus the PWDN values. PWDN1 PWDN0 Bias Level 1 1 100% 1 0 60% 0 1 40% 0 0 25% (low Zout but not OFF) X X Full OFF (High Zout via 250uA pulled out of BIAS pin) 3/9 STLC60133 The bias level is programmed by the TTL logic level applied to the PWDN pins. The DGND pin is the logic ground reference for the PWDN pins. For normal operation the BIAS pin shall be left open. The BIAS control pin can be used to adjust the internal biasing and thus the quiescent current. By pulling out a current of 0µA to 200µA, the quiescent current can be adjusted from 100% (full ON) to a full OFF condition. However, considering the internal parameter spread to full shutdown the STLC60133 is recommended to pull down a 250µA current from the BIAS pin. In the following figure is shown an implementation of a complete amplifier shutdown. To partially reduce the internal biasing also the PWDN pins can be used. Figure 2. Logic drive of bias pin for complete Amplifier Shutdown. 3.3V R1 BIAS R2 50KΩ STLC60133 R1 = 47KΩ for ± 12V R1 = 22KΩ for ± 6V D01TL492 THERMAL SHUTDOWN A thermal protection is embedded in the STLC60133. In case of thermal overload the device is shut down at 160°C and returns to normal operation when the temperature becomes lower than 145°C. During the thermal shutdown the voltage at the BIAS pin goes to the DGND rail; when the device returns to the normal operation the voltage at the BIAS pin goes to the positive rail. In this condition the BIAS pin can be used as thermal overload indicator. MAXIMUM POWER DISSIPATION Maximum Junction Temperature allowed for proper device operation is T j = 140°C. A Typical Thermal Resistance Junction to ambient of 29°C/W can be obtained mounting the device on a 4 layer board whithin 10 square inches of copper and having the exposed pad contacting a proper copper area . It shall be noted that the exposed pad of the device is electrically connected to the VSS negative supply. Figure 3. Shutdown and alarm circuit VCC STLC60133 200µA VBIAS=VCC -1.5V 10KΩ BIAS SHUT DOWN OR 0-200µA BIAS VEE PWDN0 PWDN1 +5V 10KΩ VCC +5V OR 10KΩ BIAS ALARM 1MΩ 100KΩ 1/4 HCF40109B ST 4/9 ALARM BIAS D01TL491 MIN β 350 STLC60133 ELECTRICAL CHARACTERISTCS Test Conditions: (VCC = ±12V , Tamb = 0 to 70°C , Single amplifier in normal condition (PWDN0 = 1, PWDN1 = 1), unless otherwise specified). The limits listed below are guaranted in the above temperature range (0-70°C) by specific testing at different temperature or by product characterisation. TRANSMISSION PATH Symbol SR Parameter Test Condition Slew Rate G = 6, Vout = 2Vpp GBW Gain Bandwidth G = 6, Vout = 2Vpp, f = 5MHz THD Single ended Distortion DTHD IMD DIMD Min. Max. Unit 400 V/us 90 140 MHz G = 6, f = 1MHz, Vout = 12Vpp, Rl = 16.5Ω Rl = 100Ω -40 -45 -47 -52 dBc Differential THD (2) G = 6, f = 1MHz, Vout = 24Vpp, Rl = 33Ω Rl = 100Ω -50 -55 Single ended IMD G = 6, Vout = 3Vp each tone, f = 500KHz, ∆f = 10KHz Rl = 16.5Ω Rl = 100Ω -54 -60 G = 6, Vout = 6Vp each tone, f = 500KHz, ∆f = 10KHz Rl = 33Ω Rl = 100Ω -66 -72 Differential IMD (2) IB Input Biasing OZ Output Impedance PWDN0 = PWDN1 = 0; f = 1MHz VN Voltage Noise (RTI) f = 30KHz IOV Input Offset Voltage -70 -75 dBc dBc 4 Input Common Mode Voltage Range f = 1 MHz CMRR Common Mode Rejection Ratio f = 1 MHz, Vin = 100mV OVS Output Voltage Swing Single ended, Rl = 100Ω, G = 6 -10.8 LOC Linear Output Current Single ended, Rl = 10Ω, G = 6 400 SCC Short Circuit Current (1) Single ended QC Quiescent Current PWDN1, PWDN1, PWDN1, PWDN1, SC Shutdown Current 250µA out of Bias pin PSRR Power Supply Rejection ratio f = 500kHz, V = 100mV BIASV Bias Pin Voltage DC Gain dBc µA 5 ICMR DCG Typ. -1 2 Ω 10 nV/ Hz 6 mV +1 V 40 PWDN0 = 1,1 PWDN0 = 1,0 PWDN0 = 0,1 PWDN0 = 0,0 +10.8 600 V mA 1000 1400 mA 12 8 5 4 16.2 10.7 7.5 5.3 mA/Amp 1.5 2.0 mA/Amp 30 10 dB dB 10.5 V 80 dB Notes: 1. The output stage of the STLC60133 is designed for maximum load current capability. As a result, shorting the output to common can cause the STLC60133 to source or sink 1.4A. 2. Guaranteed by product characterization. 5/9 STLC60133 ELECTRICAL CHARACTERISTICS Test conditions (V CC = ±6V, Tamb = 0 to 70°C ,Single amplifier in normal condition (PWDN0 = 1, PWDN1 = 1), unless otherwise specified.) The limits listed below are guaranted in the above temperature range by (0-70°C) specific testing at different temperature or by product characterisation. TRANSMISSION PATH Symbol SR Parameter Test Condition Slew Rate G = 6, Vout = 2Vpp GBW Gain Bandwidth G = 6, Vout = 2Vpp, f = 5MHz THD Single Ended Distortion DTHD IMD DIMD Min. Max. Unit 400 V/us 90 140 MHz G = 6, f = 1MHz, Vout = 6Vpp, Rl = 25Ω Rl = 100Ω -40 -45 -46 -51 dBc Differential THD (2) G = 6, f = 1MHz, Vout = 12Vpp, Rl = 25Ω Rl = 100Ω -50 -55 Single Ended IMD G = 6, Vout = 1.5Vp each tone, f = 500KHz, ∆f = 10KHz Rl = 25Ω Rl = 100Ω -65 -70 G = 6, Vout = 3Vp each tone, f = 500KHz, ∆f = 10KHz Rl = 25Ω Rl = 100Ω -77 -82 Differential IMD (2) IB Input Biasing VN Voltage Noise (RTI) IOV Input Offset Voltage f = 30KHz -76 -81 dBc dBc 4 Input Common Mode Voltage Range f = 1 MHz CMRR Common Mode Rejection Ratio f = 1 MHz, Vin = 100mV OVS Output Voltage Swing Single ended, Rl = 100Ω, G=6 -5 LOC Linear Output Current Single ended, Rl = 10Ω, G=6 300 SCC Short Circuit Current (1) Single ended, QC Quiescent Current PWDN1, PWDN0 = PWDN1, PWDN0 = PWDN1, PWDN0 = PWDN1, PWDN0 = SC Shutdown Current 250µA out of Bias pin PSRR Power Supply Rejection ratio f = 500kHz, V = 100mV BIASV Bias Pin Voltage DC Gain dBc µA 5 ICMR DCG Typ. -1 10 nV/ Hz 6 mV +1 V 40 1,1 1,0 0,1 0,0 dB +5 420 V mA 1000 1400 mA 10 7 5 3.5 13.7 9 6.5 4.5 mA/Amp 1.5 2.0 mA/Amp 30 40 dB 4 4.5 V 80 dB Notes: 1. The output stage of the STLC60133 is designed for maximum load current capability. As a result, shorting the output to common can cause the STLC60133 to source or sink 1.4A. 2. Guaranteed by product characterization. 6/9 STLC60133 DIGITAL INTERFACE (PWDN0, PWDN1, Vcc = ±12 V or ±6 V) Symbol Parameter Test Condition Min. Typ. Max. Unit Vil Input low voltage 0 0.8 V Vih Input high voltage 2.2 5.5 V Max. Unit THERMAL PROTECTION Symbol Parameter Test Condition Min. Typ. Thsd Thermal shut down threshold 160 °C Thist Thermal detector histeresys 15 °C Figure 4. Single ended Test Circuit G = 6 200Ω 1200Ω VIN VOUT RL + +VS 0.1µF 10µF 0.1µF 10µF -VS D00TL464 Figure 5. Differential Test Circuit G = 6 10µF +VS 200Ω + 0.1µF +VOUT 1200Ω VIN RL 1200Ω 200Ω - -VOUT + 0.1µF -VS 10µF D00TL465A 7/9 STLC60133 mm inch DIM. MIN. TYP. MAX. A 1.2 A1 0.15 A2 0.8 b TYP. 0.0 0.006 0.031 0.19 0.3 0.007 0.012 c 0.09 0.2 0.003 0.008 D (*) 9.6 9.8 0.377 9.7 0.039 0.382 0.041 0.385 0.216 5.5 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 (*) 4.3 4.4 4.5 0.169 0.173 0.177 E2 3.0 0.118 e 0.65 0.026 L 0.45 L1 0.6 0.75 0.018 0.024 1.0 k OUTLINE AND MECHANICAL DATA MAX. 1.05 D1 1.0 MIN. 0.029 0.039 0˚ (min), 8˚ (max) aaa 0.1 0.004 HTSSOP28 (Exposed Pad) (*) Dimensions D and E1 does not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm per side. A2 aaa C b A A1 e c E1 D 0.25mm 0.10inch GAUGE PLANE D1 SEATING PLANE 1 1 4 C E2 28 E k L L1 15 HTSSO28M 8/9 STLC60133 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 9/9