STLVD210 DIFFERENTIAL LVDS CLOCK DRIVER ■ ■ ■ ■ ■ ■ ■ ■ ■ 100ps PART-TO-PART SKEW 50ps BANK SKEW DIFFERENTIAL DESIGN MEETS LVDS SPEC. FOR DRIVER OUTPUTS AND RECEIVER INPUTS REFERENCE VOLTAGE AVAILABLE OUTPUT VBB LOW VOLTAGE VCC RANGE OF 2.375V TO 2.625V HIGH SIGNALLING RATE CAPABILITY (EXCEEDS 700MHz) SUPPORT OPEN, SHORT, AND TERMINATED INPUT FAIL-SAFE (LOW OUTPUT STATE) PROGRAMMABLE DRIVERS POWER OFF CONTROL DESCRIPTION The STLVD210 is a low skew programmable 1-to-5 dual differential LVDS driver, designed with clock distribution in mind. The LVDS input signals can be either differential or single-ended if the VBB output is used. The STLVD210 is provided with a 11 bit shift register with a serial in and a Control Register. The purpose is to enable or power off each output clock channel and to select the clock input. The TQFP32 STLVD210 is specifically designed, modelled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within a device. The net result is a dependable guaranteed low skew device. The STLVD210 can be used for high performance clock distribution in 2.5V systems with LVDS levels. Designers can be take advantage of the device’s performance to distribute low skew clocks across the backplane or the board. ORDERING CODES Type Temperature Range Package Comments STLVD210BF STLVD210BFR -40 to 85 °C -40 to 85 °C TQFP32 (Tray) TQFP32 (Tape & Reel) 250 parts per Tray 2400 parts per reel December 2002 1/9 STLVD210 PIN CONFIGURATION PIN DESCRIPTION PlN N° SYMBOL 1 CK 2 3, 4, 6, 7 SI CLKn/CLKn VBB 5 8 9, 25 10, 11, 12, 13, 14, 15, 17, 18, 19, 20, 21, 22, 23, 24, 26, 27, 28, 29, 30, 31 16, 32 2/9 EN GND Qn0:4/Qn0:4 VCC NAME AND FUNCTION Control Register Clock Control Register Serial IN/CLK_SEL LVDS CLK Inputs Reference Voltage Output Device Enable/Program GROUND LVDS Supply Voltage STLVD210 LOGIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Value Supply Voltage Unit -0.3 to 2.8 V VI Input Voltage -0.2 to (VCC+0.2) V VO Output Voltage -0.2 to (VCC+0.2) V IOSD Driver Short Circuit Current ESD Electrostatic Discharge (HBM 1.5KΩ, 100pF) Continuous >2 KV Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. THERMAL DATA Symbol RTj-c Parameter Value Unit 13 °C/W Thermal Resistance Junction-Case RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min TYP Max Unit VCC Supply Voltage 2.375 2.625 V VIC Receiver Common Mode Input Voltage 0.5(VID) 2-0.5(VID) V TOPR Operating Free-Air Temperature Range -40 85 °C Operating Junction Temperature -40 105 °C TJ 3/9 STLVD210 DRIVER ELECTRICAL CHARACTERISTICS (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise noted. Typical values are at TA = 25°C) (Note 1) Value Symbol VOD ∆VOD VOS ∆VOS IOS Parameter Output Differential Voltage Test Conditions RL = 100 Ω Unit Min. Typ. Max. 400 500 600 mV 30 mV 1.25 V VOD Magnitude Change Offset Voltage 1.05 1.15 VOS Magnitude Change Output Short Circuit Current VO = 0V VOD = 0V 30 mV 15 30 mA 7 15 NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. RECEIVER ELECTRICAL CHARACTERISTICS (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise noted. Typical values are at TA = 25°C) (Note 1) Value Symbol Parameter Test Conditions Unit Min. VIDH Input Threshold High VIDL Input Threshold Low IIN Input Current Typ. Max. 100 -100 mV mV VI = 0V 42 100 VI = VCC 2 10 µA NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. DRIVER ELECTRICAL CHARACTERISTICS (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise noted. Typical values are at TA = 25°C) (Note 1) Value Symbol Parameter Test Conditions VBB Output Reference Voltage VCC = 2.5 V ICCD Power Supply Current CIN Input Capacitance All driver enabled and loaded All driver disabled VI = 0V to VCC COUT Typ. Max. 1.15 1.25 1.35 V 125 18 5 180 25 mA Output Capacitance pF 5 VIH Logic Input High Threshold VIL Logic Input Low Threshold VCC = 2.5 V Logic Input Current VCC = 2.5 V, II IBB = 0.5 mA Unit Min. VCC = 2.5 V pF 2 VIN = VCC or GND V 0.8 V ±10 µA NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 4/9 STLVD210 LVDS TIMING CHARACTERISTICS (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise noted. Typical values are at TA = 25°C) (Note 1) Value Symbol Parameter Test Conditions Unit Min. tTLH Transition Time Low to High tTHL Transition Time High to Low RL = 100 Ω, CL = 5 pF Typ. 220 300 ps 220 300 ps 2 2.5 tPHL, tPLH Propagation Delay to Output fMAX tSKEW Maximum Input Frequency 700 Bank Skew Part-to-Part Skew Pulse Skew Max. ns 900 MHz 50 100 60 ps NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. SPECIFICATION OF CONTROL REGISTER The STLVD210 is provided with a 11 bit shift register with a Serial In and a Control Register. The purpose is to enable or power of each output clock channel. The STLVD210 provides two working modality: PROGRAMMED MODE (EN=1) The shift register have a serial input to load the working configuration. Once the configuration is loaded with 11-clock pulse, another clock pulse loads the configuration into the control register. The first bit on the serial input line enables the outputs Qb4 and Qb4, the second bit enables the outputs Qb3 and Qb3 and so on. The last bit is the fewer significations. To restart the configuration of the shift register a reset of the state machine must be done with a clock pulse on CK and the EN set to Low. The control register can be configured on time after each reset. STANDARD MODE (EN=0) In Standard Mode the STLVD210 isn’t programmable, all the clock outputs are enabled. TRUTH TABLE OF STATE MACHINE INPUTS EN SI CK OUTPUT L X X H L All Outputs Enable First stage stores "L", other stages store the data of previous stage H H First stage stores "H", other stages store the data of previous stage L X Reset of the state machine, Shift register and Control Register SERIAL INPUT SEQUENCE BIT#10 BIT#9 BIT#8 BIT#7 BIT#6 BIT#5 BIT#4 BIT#3 BIT#2 BIT#1 BIT#0 N.A. Qa0 Qa1 Qa2 Qa3 Qa4 Qb0 Qb1 Qb2 Qb3 Qb4 5/9 STLVD210 TRUTH TABLE OF SEQUENCE BIT#10 BIT#(0-4) Qb(0-4) X X L H OFF ON BIT#10 BIT#(5-9) Qa(0-4) X X L H OFF ON TRUTH TABLE 6/9 CLKa CLKa Qa (0-4) Qa (0-4) H L L H H L L H CLKb CLKb Qb (0-4) Qb (0-4) H L L H H L L H STLVD210 TQFP32 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 1.6 A1 0.05 A2 1.35 B 0.30 C 0.09 0.063 0.15 0.002 0.006 1.40 1.45 0.053 0.055 0.057 0.37 0.45 0.012 0.015 0.018 0.20 0.0035 0.0079 D 9.00 0.354 D1 7.00 0.276 D3 5.60 0.220 E 0.80 0.031 E 9.00 0.354 E1 7.00 0.276 E3 5.60 0.220 L 0.45 0.60 L1 0.75 0.018 0.024 1.00 K 0˚ 0.030 0.039 3.5˚ 7˚ 0˚ 3.5˚ 7˚ D A D1 A2 D3 24 A1 17 25 16 0.10mm .004 B E E1 B E3 Seating Plane 9 32 8 1 C L L1 e K TQFP32 0060661/C 7/9 STLVD210 Tape & Reel TQFP32 MECHANICAL DATA mm. inch DIM. MIN. A MAX. MIN. 330 13.2 TYP. MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 8/9 TYP 0.504 22.4 0.519 0.882 Ao 9.5 9.7 0.374 0.382 Bo 9.5 9.7 0.374 0.382 Ko 2.1 2.3 0.083 0.091 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 STLVD210 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 9/9