STLVDS105 4-PORT LVDS AND 4-PORT TTL-TO LVDS REPEATERS ■ ■ ■ ■ ■ ■ ■ RECEIVER AND DRIVERS MEET OR EXCEED THE REQUIREMENTS OF ANSI EIA/TIA-644 STANDARD: RECEIVERS LOW-VOLTAGE TTL (LVTTL) LEVELS DESIGNED FOR SIGNALING RATES UP TO 630Mbps OPERATES FROM A SINGLE 3.3V SUPPLY LOW VOLTAGE DIFFERENTIAL SIGNALING WITH TYPICAL OUTPUT VOLTAGE OF 350mV AND A 100Ω LOAD PROPAGATION DELAY TIME: 2.2ns (TYP) ELECTRICALLY COMPATIBLE WITH LVDS, PECL, LVPECL, LVTTL, LVCOMOS, GTL, BTL, CTT, SSTL, OR HSTL OUTPUTS WITH EXTERNAL NETWORK BUS TERMINAL ESD (HBM) EXCEEDS 7KV SO AND TSSOP PACKAGING DESCRIPTION The STLVDS105 is a differential line receiver and a LVTTL input connected to four differential line drivers that implement the electrical characteristics of low voltage differential signaling, for point to point baseband data transmission over controlled impedance media of approximately 100Ω. The transmission media can be printed-circuit board traces, backplanes, or cable. SOP TSSOP LVDS, as specified in EIA/TIA-644 is a data signaling technique that offers low-power, low noise coupling, and switching speed to transmit data at a speed up to 630Mbps at relatively long distances. The drivers integrated into the same substrate, along with the low pulse skew of balanced signaling, allow extremely precise timing alignment of the signals repeated from the input. The device allows extremely precise timing alignment of the signal repeated from the input. This is particularly advantageous in distribution or expansion of signals such as clock or serial data stream. ORDERING CODES Type Temperature Range Package Comments STLVDS105BD STLVDS105BDR STLVDS105BTR -40 to 85 °C -40 to 85 °C -40 to 85 °C SO-16 (Tube) SO-16 (Tape & Reel) TSSOP16 (Tape & Reel) 50parts per tube / 20tube per box 2500 parts per reel 2500 parts per reel May 2003 1/8 STLVDS105 PIN CONFIGURATION FUNCTIONAL DIAGRAM PIN DESCRIPTION FUNCTIONAL TABLE PlN N° SYMBOL 1, 2, 3, 8 6 7 9, 11, 13, 15 10, 12, 14, 16 5 EN1 to EN4 A NC 1Z to 4Z 1X to 4X GND VCC 4 NAME AND FUNCTION Enable Driver Inputs Receiver Input Not Connected Driver Inputs Driver Inputs Ground Supply Voltage INPUT ENABLES OUTPUTS A #EN #Y #Z L H Open X X H H H L X L H L Z Z H L H Z Z L=Low level, H=High Level, Z= High Impedance ABSOLUTE MAXIMUM RATINGS Symbol Parameter VCC Supply Voltage (Note 1) VR Voltage Range ESD ESD Protection Voltage (HBM) Tstg Storage Temperature Range Enable Inputs A, Y or Z Y, Z, to GND All Pins Value Unit -0.5 to 4 V -0.5 to 6 -0.5 to 4 7 2 V V KV KV -65 to +150 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. Note 1: All voltages except differential I/O bus voltage, are with respect to the network ground terminal. 2/8 STLVDS105 RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min. Typ. Max. Unit 3.3 3.6 V VCC Supply Voltage 3.0 VIH HIGH Level Input Voltage 2.0 VIL LOW Level Input Voltage |VID| Magnitude Of Differential Input Voltage VIC Common Mode Input Voltage V 0.8 V 0.1 3.6 V |VID|/2 24-|VID|/2 V VCC-0.8 TA Operating Temperature Range 85 -40 °C ELECTRICAL CHARACTERISTICS (TA = -40 to 85°C, and VCC = 3.3V ±10% over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C) Symbol |VOD| Parameter Test Conditions Min. Typ. Max. Unit VID = ±100mV 247 340 454 mV -50 50 mV -50 50 mV 1.2 1.375 V 25 150 mV Enabled, RL = 100Ω 18 28 mA 0.3 7 1 20 mA µA 3 10 µA ICC Differential Output Voltage Magnitude Change in Differential Output Voltage Magnitude Between Logic State Change in Steady-state Common Mode Output Voltage Between Logic State Steady-state Common Mode Output Voltage Peak to Paek Common mode Output Voltage Supply Current IIH High Level Input Current Disabled VIH = 2V IIL Low Level Input Current VIL = 0.8V IOC Short Circuit Output Current VO(Y) or VO(Z) = 0V ∆|VOD| ∆VOC(SS) VOC(SS) VOC(PP) IOZ IO(OFF) CIN CO High Impedance Output Current Power OFF Output Current RL = 100Ω 1.125 ± 10 mA VOD = 0 ± 10 mA VO = 0 or 2.4V ±1 µA ±1 µA VCC = 1.5V VO = 2.4V Input Capacitance (A or B VI = 0.4 sin (4e6πt)+0.5V Inputs) Output Capacitance (Y or Z V = 0.4 sin (4e6πt)+0.5V, Disabled I Outputs) 0.3 5 pF 9.4 pF 3/8 STLVDS105 SWITCHING CHARACTERISTICS (TA = -40 to 85°C, and VCC = 3.3V unless otherwise noted. All typical values are at TA = 25°C) Symbol tPLH tPHL tr tf tsk(P) tsk(O) tsk(pp) tPZH tPZL tPHZ tPLZ Parameter Min. Typ. Max. Unit 1.7 2.2 3 ns 1.7 2.2 3 ns 0.3 0.7 1.2 ns 0.3 0.7 1.2 ns 50 200 ps Channel-to-channel Output Skew (note1) Part to part Skew (note2) 30 100 ps 1.5 ns Propagation Delay Time, High Impedance to High Level Output Propagation Delay Time, High Impedance to Low Level Output Propagation Delay Time, High Level to High Impedance Output Propagation Delay Time, Low Level to High Impedance Output 5 15 ns 5 15 ns 4 15 ns 5 15 ns Propagation Delay Time, Low to High Output Propagation Delay Time, High to Low Output Differential Output Signal Rise Time Differential Output Signal Fall Time Pulse Skew (|tTHL - tTLH|) Test Conditions RL = 100Ω CL = 10pF Note 1: tsk(O) is the time difference between the tPLH or tPHL of all drivers of a single device with all their inputs connected together. Note 2: tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuit. 4/8 STLVDS105 TYPICAL PERFORMANCE CHARACTERISTICS (unless otherwise specified Tj = 25°C) Figure 1 : Output Current vs Output High Voltage Figure 3 : High to Low Propagation Delay Time Figure 2 : Output Current vs Output Low Voltage Figure 4 : Low to High Propagation Delay Time 5/8 STLVDS105 SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.004 0.008 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45˚ (typ.) D 9.8 E 5.8 10 0.385 6.2 0.228 0.393 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 8 0.024 ˚ (max.) PO13H 6/8 STLVDS105 TSSOP16 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 D 4.9 5 5.1 0.193 0.197 0.201 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0˚ L 0.45 A 0.60 0.0256 BSC 8˚ 0˚ 0.75 0.018 8˚ 0.024 0.030 A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080338D 7/8 STLVDS105 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 8/8