STMICROELECTRONICS STM805SM6E

STM690, STM704, STM795
STM802, STM804, STM805, STM806
3V Supervisor with Battery Switchover
FEATURES SUMMARY
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■
■
■
■
■
■
■
■
RST OR RST OUTPUTS
NVRAM SUPERVISOR FOR EXTERNAL
LPSRAM
CHIP-ENABLE GATING (STM795 only) FOR
EXTERNAL LPSRAM (7ns max PROP
DELAY)
MANUAL (PUSH-BUTTON) RESET INPUT
200ms (TYP) trec
WATCHDOG TIMER - 1.6sec (TYP)
AUTOMATIC BATTERY SWITCHOVER
LOW BATTERY SUPPLY CURRENT - 0.4µA
(TYP)
POWER-FAIL COMPARATOR (PFI/PFO)
LOW SUPPLY CURRENT - 40µA (TYP)
GUARANTEED RST (RST) ASSERTION
DOWN TO VCC = 1.0V
OPERATING TEMPERATURE:
–40°C to 85°C (Industrial Grade)
Figure 1. Packages
8
1
SO8 (M)
TSSOP8 3x3 (DS)*
Table 1. Device Options
STM690T/S/R
Watchdog
Input
ActiveLow RST(1)
✔
✔
ActiveHigh
RST
Manual
Battery
Reset Input Switch-over
✔
Power-fail
Comparator
✔
✔
✔
✔
STM704T/S/R
✔
STM795T/S/R
✔(2)
✔
✔
✔
✔
✔
STM802T/S/R
✔
STM804T/S/R
✔
✔(2)
✔
✔
STM805T/S/R
✔
✔(2)
✔
✔
✔
✔
STM806T/S/R
✔
✔
ChipEnable
Gating
Note: 1. All RST outputs push-pull (unless otherwise noted)
2. Open drain output.
* Contact local ST sales office for availability.
September 2004
1/31
STM690/704/795/802/804/805/806
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram (STM690/802/804/805) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. Logic Diagram (STM795). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 5. STM690/802/804/805 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. STM704/806 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 7. STM795 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 8. Block Diagram (STM690/802/804/805) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 9. Block Diagram (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 10.Block Diagram (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 11.Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Push-button Reset Input (STM704/806). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Watchdog Input (NOT available on STM704/795/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Back-up Battery Switchover. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. I/O Status in Battery Back-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip-Enable Gating (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Enable Input (STM795 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Enable Output (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12.Chip-Enable Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 13.Chip Enable Waveform (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power-fail Input/Output (NOT available on STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 14.Power-fail Comparator Waveform (STM690/704/802/804/805/806) . . . . . . . . . . . . . . . . 11
Using a SuperCap™ as a Backup Power Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 15.Using a SuperCap™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Negative-Going VCC Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
TYPICAL OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 16.VBAT-to-VOUT On-Resistance vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 17.Supply Current vs. Temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 18.VPFI Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 19.Reset Comparator Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 20.Power-up trec vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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STM690/704/795/802/804/805/806
Figure 21.Normalized Reset Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 22.Watchdog Time-out Period vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 23.E to ECON On-Resistance vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 24.PFI to PFO Propagation Delay vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 25.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 26.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 27.RST Response Time (Assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 28.RESET Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 29.Power-fail Comparator Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 30.Power-fail Comparator Response Time (De-Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 31.VCC to Reset Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 32.Maximum Transient Duration vs. Reset Threshold Overdrive. . . . . . . . . . . . . . . . . . . . . 20
Figure 33.E to ECON Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . .
Figure 34.E to ECON Propagation Delay Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . .
Figure 35.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 36.MR Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 37.Watchdog Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7. DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
......
......
......
......
......
......
. . . . 21
. . . . 22
. . . . 22
. . . . 22
. . . . 23
. . . . 23
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 38.SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mech. Drawing. . . . 26
Table 8. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . . 26
Figure 39.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline . . . . . . . . . . . 27
Table 9. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data . . . . 27
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. Marking Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/31
STM690/704/795/802/804/805/806
SUMMARY DESCRIPTION
The STM690/704/795/802/804/805/806 Supervisors are self-contained devices which provide microprocessor supervisory functions with the ability
to non-volatize and write-protect external
LPSRAM. A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance condition. When an invalid VCC condition
occurs, the reset output (RST) is forced low (or
high in the case of RST). These devices also offer
a watchdog timer (except for STM704/795/806) as
well as a power-fail comparator (except for
STM795) to provide the system with an early
warning of impending power failure.
These devices are available in a standard 8-pin
SOIC package or a space-saving 8-pin TSSOP
package.
Figure 2. Logic Diagram (STM690/802/804/805)
Figure 4. Logic Diagram (STM795)
VCC VBAT
VCC VBAT
VOUT
VOUT
WDI
PFI
STM690/
802/804/
805
RST(RST)(1)
VCCSW
STM795
ECON
PFO
VSS
Figure 3. Logic Diagram (STM704/806)
VCC VBAT
VOUT
PFI
STM704
STM806
RST
PFO
VSS
VSS
AI08846
Note: 1. For STM804/805, reset output is active-high and open
drain.
MR
AI08847
AI08848
Table 2. Signal Names
MR
Push-button Reset Input
WDI
Watchdog Input
RST
Active-Low Reset Output
RST(1)
Active-High Reset Output
E(2)
Chip Enable Input
ECON(2)
Conditioned Chip Enable Output
Vccsw(2)
VCC Switch Output
VOUT
Supply Voltage Output
VCC
Supply Voltage
VBAT
Back-up Supply Voltage
PFI
Power-fail Input
PFO
Power-fail Output
VSS
Ground
Note: 1. Open drain for STM804/805 only.
2. STM795
4/31
RST
E
STM690/704/795/802/804/805/806
Figure 5. STM690/802/804/805 Connections
Figure 6. STM704/806 Connections
SO8/TSSOP8
VOUT
VCC
VSS
PFI
1
2
3
4
8
7
6
5
VBAT
RST(RST)(1)
WDI
PFO
AI08849
SO8/TSSOP8
VOUT
VCC
VSS
PFI
1
2
3
4
VBAT
8
7
6
5
RST
MR
PFO
AI08850
Note: 1. For STM804/805, reset output is active-high and open
drain.
Figure 7. STM795 Connections
SO8/TSSOP8
VOUT
VCC
VCCSW
VSS
1
2
3
4
8
7
6
5
VBAT
RST
ECON
E
AI08851
5/31
STM690/704/795/802/804/805/806
Pin Descriptions
MR. A logic low on /MR asserts the reset output.
Reset remains asserted as long as MR is low and
for trec after MR returns high. This active-low input
has an internal pull-up. It can be driven from a TTL
or CMOS logic line, or shorted to ground with a
switch. Leave open if unused.
WDI. If WDI remains high or low for 1.6sec, the internal watchdog timer runs out and reset is triggered. The internal watchdog timer clears while
reset is asserted or when WDI sees a rising or falling edge.
The watchdog function cannot be disabled by allowing the WDI pin to float.
RST. Pulses low for trec when triggered, and stays
low whenever VCC is below the reset threshold or
when MR is a logic low. It remains low for trec after
either VCC rises above the reset threshold, the
watchdog triggers a reset, or MR goes from low to
high.
RST (Open Drain). Pulses high for trec when triggered, and stays high whenever VCC is above the
reset threshold or when MR is a logic high. It remains high for trec after either VCC falls below the
reset threshold, the watchdog triggers a reset, or
MR goes from high to low.
PFI. When PFI is less than VPFI or when VCC falls
below VSW (2.4V), PFO goes low; otherwise, PFO
remains high. Connect to ground if unused.
PFO. When PFI is less than VPFI, or VCC falls below VSW, PFO goes low; otherwise, PFO remains
high. Leave open if unused.
VOUT. When VCC is above the switchover voltage
(VSO), VOUT is connected to VCC through a Pchannel MOSFET switch. When VCC falls below
VSO, VBAT connects to VOUT. Connect to VCC if no
battery is used.
Vccsw. When VOUT switches to battery, Vccsw is
high. When VOUT switches back to VCC, Vccsw is
low. It can be used to drive gate of external PMOS
transistor for IOUT requirements exceeding 75mA.
E. The input to the chip-enable gating circuit. Connect to ground if unused.
ECON. ECON goes low only when E is low and reset is not asserted. If ECON is low when reset is asserted, ECON will remain low for 15µs or until E
goes high, whichever occurs first. In the disabled
mode, ECON is pulled up to VOUT.
VBAT. When VCC falls below VSO, VOUT switches
from VCC to VBAT. When VCC rises above VSO +
hysteresis, VOUT reconnects to VCC. VBAT may exceed VCC. Connect to VCC if no battery is used.
Table 3. Pin Description
Pin
Name
Function
STM795
STM690
STM802
STM704
STM806
STM804
STM805
–
–
6
–
MR
Push-button Reset Input
–
6
–
6
WDI
Watchdog Input
7
7
7
–
RST
Active-Low Reset Output
–
–
–
7
RST
Active-High Reset Output
–
4
4
4
PFI
PFI Power-fail Input
–
5
5
5
PFO
PFO Power-fail Output
1
1
1
1
VOUT
Supply Output for External LPSRAM
2
2
2
2
VCC
Supply Voltage
3
–
–
–
Vccsw
4
3
3
3
VSS
5
–
–
–
E
6
–
–
–
ECON
Conditioned Chip Enable Output
8
8
8
8
VBAT
Backup-Battery Input
6/31
VCC Switch Output
Ground
Chip Enable Input
STM690/704/795/802/804/805/806
Figure 8. Block Diagram (STM690/802/804/805)
VCC
VOUT
VBAT
VSO
COMPARE
VRST
COMPARE
WATCHDOG
TIMER
WDI
PFI
VPFI
trec
Generator
COMPARE
RST(RST)(1)
PFO
AI07897
Note: 1. For STM804/805, reset output is active-high and open drain.
Figure 9. Block Diagram (STM704/806)
VCC
VOUT
VBAT
VSO
COMPARE
VRST
COMPARE
trec
Generator
MR
PFI
VPFI
COMPARE
RST
PFO
AI07898
7/31
STM690/704/795/802/804/805/806
Figure 10. Block Diagram (STM795)
VCC
VOUT
VBAT
VSO
COMPARE
VRST
COMPARE
VCCSW
trec
Generator
RST
ECON OUTPUT
CONTROL
E
ECON
PFI
VPFI
COMPARE
PFO
AI08852
Figure 11. Hardware Hookup
VCCSW(2)
Regulator
Unregulated
Voltage
VIN
VCC
VCC
VCC
VOUT
VCC
0.1µF
LPSRAM
STM690/704/
795/802/804/
805/806
E
E
0.1µF
WDI(1)
From Microprocessor
E(2)
ECON(2)
R1
PFI(3)
PFO(3)
MR(4)
RST
To Microprocessor NMI
R2
Push-Button
To Microprocessor Reset
VBAT
AI08853
Note: 1.
2.
3.
4.
8/31
For STM690/802/804/805.
For STM795 only.
Not available on STM795.
For STM704/806.
STM690/704/795/802/804/805/806
OPERATION
Reset Output
The STM690/704/795/802/804/805/806 Supervisor asserts a reset signal to the MCU whenever
VCC goes below the reset threshold (VRST), a
watchdog time-out occurs, or when the Push-button Reset Input (MR) is taken low. RST is guaranteed to be a logic low (logic high for STM804/805)
for 0V < VCC < VRST if VBAT is greater than 1V.
Without a back-up battery, RST is guaranteed valid down to VCC =1V.
During power-up, once VCC exceeds the reset
threshold an internal timer keeps RST low for the
reset time-out period, trec. After this interval RST
returns high.
If VCC drops below the reset threshold, RST goes
low. Each time RST is asserted, it stays low for at
least the reset time-out period (trec). Any time VCC
goes below the reset threshold the internal timer
clears. The reset timer starts when VCC returns
above the reset threshold.
Push-button Reset Input (STM704/806)
A logic low on MR asserts reset. Reset remains
asserted while MR is low, and for trec (see Figure
36., page 22) after it returns high. The MR input
has an internal 40kΩ pull-up resistor, allowing it to
be left open if not used. This input can be driven
with TTL/CMOS-logic levels or with open-drain/
collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is
not required. If MR is driven from long cables or
the device is used in a noisy environment, connect
a 0.1µF capacitor from MR to GND to provide additional noise immunity. MR may float, or be tied to
VCC when not used.
Watchdog Input (NOT available on STM704/
795/806)
The watchdog timer can be used to detect an outof-control MCU. If the MCU does not toggle the
Watchdog Input (WDI) within tWD (1.6sec typ), the
reset is asserted. The internal watchdog timer is
cleared by either:
1. a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high),
which can detect pulses as short as 50ns. If
WDI is tied high or low, a reset pulse is
triggered every 1.8sec (tWD + trec).
The timer remains cleared and does not count for
as long as reset is asserted. As soon as reset is released, the timer starts counting (see Figure
37., page 23).
Note: Input frequency greater than 20ns (50MHz)
will be filtered.
Back-up Battery Switchover
In the event of a power failure, it may be necessary
to preserve the contents of external SRAM
through VOUT. With a backup battery installed with
voltage VBAT, the devices automatically switch the
SRAM to the back-up supply when VCC falls.
Note: If back-up battery is not used, connect both
VBAT and VOUT to VCC.
This family of Supervisors does not always connect VBAT to VOUT when VBAT is greater than VCC.
VBAT connects to VOUT (through a 100Ω switch)
when VCC is below VSW (2.4V) or VBAT (whichever
is lower). This is done to allow the back-up battery
(e.g., a 3.6V lithium cell) to have a higher voltage
than VCC.
Assuming that VBAT > 2.0V, switchover at VSO ensures that battery back-up mode is entered before
VOUT gets too close to the 2.0V minimum required
to reliably retain data in most external SRAMs.
When VCC recovers, hysteresis is used to avoid
oscillation around the VSO point. VOUT is connected to VCC through a 3Ω PMOS power switch.
Note: The back-up battery may be removed while
VCC is valid, assuming VBAT is adequately decoupled (0.1µF typ), without danger of triggering a reset.
Table 4. I/O Status in Battery Back-up
Pin
Status
VOUT
Connected to VBAT through internal switch
VCC
Disconnected from VOUT
PFI
Disabled
PFO
Logic Low
E
High impedance
ECON
Logic High
WDI
Watchdog timer is disabled
MR
Disabled
RST
Logic Low
RST
Logic High
VBAT
Connected to VOUT
Vccsw
Logic High (STM795)
9/31
STM690/704/795/802/804/805/806
Chip-Enable Gating (STM795 only)
Internal gating of the chip enable (E) signal prevents erroneous data from corrupting the external
CMOS RAM in the event of an undervoltage condition. The STM795 uses a series transmission
gate from E to ECON (see Figure 12). During normal operation (reset not asserted), the E transmission gate is enabled and passes all E transitions.
When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting
the CMOS RAM. The short E propagation delay
from E to ECON enables the STM795 to be used
with most µPs. If E is low when reset asserts,
ECON remains low for typically 10µs to permit the
current WRITE cycle to complete.
Chip Enable Input (STM795 only)
The chip-enable transmission gate is disabled and
E is high impedance (disabled mode) while reset
is asserted. During a power-down sequence when
VCC passes the reset threshold, the chip-enable
transmission gate disables and E immediately becomes high impedance if the voltage at E is high.
If E is low when reset asserts, the chip-enable
transmission gate will disable 10µs after reset asserts (see Figure 13). This permits the current
WRITE cycle to complete during power-down.
Any time a reset is generated, the chip-enable
transmission gate remains disabled and E remains
high impedance (regardless of E activity) for the
first half of the reset time-out period (trec/2). When
the chip enable transmission gate is enabled, the
impedance of E appears as a 40Ω resistor in series with the load at ECON. The propagation delay
through the chip-enable transmission gate depends on VCC, the source impedance of the drive
connected to E, and the loading on ECON. The chip
enable propagation delay is production tested
from the 50% point on E to the 50% point on ECON
using a 50Ω driver and a 50pF load capacitance
(see Figure 35., page 22). For minimum propagation delay, minimize the capacitive load at ECON
and use a low-output impedance driver.
Chip Enable Output (STM795 only)
When the chip-enable transmission gate is enabled, the impedance of ECON is equivalent to a
40Ω resistor in series with the source driving E. In
the disabled mode, the transmission gate is off
and an active pull-up connects ECON to VOUT (see
Figure 12). This pull-up turns off when the transmission gate is enabled.
Figure 12. Chip-Enable Gating
VCC
trec
Generator
COMPARE
VRST
RST
VOUT
ECON OUTPUT
CONTROL
E
ECON
AI08802
Figure 13. Chip Enable Waveform (STM795)
VCC
ECON
VRST
VBAT
½ trec
½ trec
RST
trec
10µs
trec
E
AI08855b
10/31
STM690/704/795/802/804/805/806
Power-fail Input/Output (NOT available on STM795)
Figure 14., page 11). This occurs after VCC drops
The Power-fail Input (PFI) is compared to an interbelow VSW (2.4V). When power returns, the pownal reference voltage (independent from the VRST
comparator). If PFI is less than the power-fail
er-fail comparator is enabled and PFO follows PFI.
threshold (VPFI), the Power-Fail Output (PFO) will
If the comparator is unused, PFI should be congo low. This function is intended for use as an unnected to VSS and PFO left unconnected. PFO
may be connected to MR on the STM704/806 so
dervoltage detector to signal a failing power supthat a low voltage on PFI will generate a reset outply. Typically PFI is connected through an external
put.
voltage divider (see Figure 11., page 8) to either
the unregulated DC input (if it is available) or the
Applications Information
regulated output of the VCC regulator. The voltage
These Supervisor circuits are not short-circuit prodivider can be set up such that the voltage at PFI
tected. Shorting VOUT to ground - excluding powfalls below VPFI several milliseconds before the
er-up transients such as charging a decoupling
regulated VCC input to the STM690/704/795/802/
capacitor - destroys the device. Decouple both
804/805/806 or the microprocessor drops below
VCC and VBAT pins to ground by placing 0.1µF cathe minimum operating voltage.
pacitors as close to the device as possible.
During battery back-up, the power-fail comparator
is turned off and PFO goes (or remains) low (see
Figure 14. Power-fail Comparator Waveform (STM690/704/802/804/805/806)
VCC
VRST
VSW (2.4V)
trec
PFO
PFO follows PFI
PFO follows PFI
RST
AI08861a
11/31
STM690/704/795/802/804/805/806
Using a SuperCap™ as a Backup Power
Source
SuperCaps™ are capacitors with extremely high
capacitance values (e.g., order of 0.47F) for their
size. Figure 15 shows how to use a SuperCap as
a back-up power source. The SuperCap may be
connected through a diode to the VCC supply.
Since VBAT can exceed VCC while VCC is above
the reset threshold, there are no special precautions when using these supervisors with a SuperCap.
Figure 15. Using a SuperCap™
5V
VCC
VOUT
To external SRAM
STMXXX
VBAT
RST
To µP
GND
AI08805
12/31
Negative-Going VCC Transients
The STM690/704/795/802/804/805/806 Supervisors are relatively immune to negative-going VCC
transients (glitches). Figure 32., page 20 was generated using a negative pulse applied to VCC,
starting at VRST + 0.3V and ending below the reset
threshold by the magnitude indicated (comparator
overdrive). The graph indicates the maximum
pulse width a negative VCC transient can have
without causing a reset pulse. As the magnitude of
the transient increases (further below the threshold), the maximum allowable pulse width decreases. Any combination of duration and overdrive
which lies under the curve will NOT generate a reset signal. Typically, a VCC transient that goes
100mV below the reset threshold and lasts 40µs or
less will not cause a reset pulse. A 0.1µF bypass
capacitor mounted as close as possible to the VCC
pin provides additional transient immunity.
STM690/704/795/802/804/805/806
TYPICAL OPERATING CHARACTERISTICS
Note: Typical values are at TA = 25°C.
VBAT - to - VOUT ON-RESISTANCE [Ω]
Figure 16. VBAT-to-VOUT On-Resistance vs. Temperature
220
VCC = 0V
200
VBAT = 2V
180
VBAT = 3V
160
VBAT = 3.3V
140
VBAT = 5V
120
100
–60
–40
–20
0
20
40
60
80
100
120
TEMPERATURE [°C]
140
AI09140
Figure 17. Supply Current vs. Temperature (no load)
30
Supply Current [µA]
25
20
2.5V
3.3V
3.6V
15
5.0V
5.5V
10
5
0
–50
–40
–30
–20
–10
0
10
20
30
40
TEMPERATURE [°C]
50
60
70
80
90
100
AI09141
13/31
STM690/704/795/802/804/805/806
Figure 18. VPFI Threshold vs. Temperature
VPFI THRESHOLD [V]
1.255
1.250
VCC = 5V
1.245
VCC = 3.3V
1.240
1.235
VCC = 2.5V
1.230
VBAT = 3.0V
1.225
–50
–30
–10
10
30
50
70
90
110
TEMPERATURE [°C]
130
AI09142
PROPAGATION DELAY [µs]
Figure 19. Reset Comparator Propagation Delay vs. Temperature
24
22
VBAT = 3.0V
100mV OVERDRIVE
20
18
16
14
12
10
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE [°C]
AI09143
Figure 20. Power-up trec vs. Temperature
215
trec [ms]
210
205
200
195
–50
–30
–10
10
30
50
TEMPERATURE [°C]
14/31
70
90
110
130
AI09144
STM690/704/795/802/804/805/806
NORMALIZED RESET THRESHOLD
[V]
Figure 21. Normalized Reset Threshold vs. Temperature
1.002
1.000
0.998
0.996
VBAT = 3.0V
0.994
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE [°C]
120
140
AI09145
Figure 22. Watchdog Time-out Period vs. Temperature
WATCHDOG TIME-OUT
PERIOD [sec]
1.74
1.72
1.70
1.68
1.66
1.64
1.62
1.60
1.58
1.56
–50
–30
–10
10
30
50
70
90
110
TEMPERATURE [°C]
130
AI09146
E to ECON ON-RESISTANCE [Ω]
Figure 23. E to ECON On-Resistance vs. Temperature
90
80
70
VCC = 3V
60
50
40
30
–60
–40
–20
0
20
40
60
TEMPERATURE [°C]
80
100
120
140
AI09147
15/31
STM690/704/795/802/804/805/806
Figure 24. PFI to PFO Propagation Delay vs. Temperature
9
PROPAGATION DELAY [µs]
8
7
6
5
4
3
2
1
0
–60
–40
–20
0
20
40
60
TEMPERATURE [°C]
80
100
120
140
AI09148
Figure 25. RST Output Voltage vs. Supply Voltage
6
RST OUTPUT VOLTAGE [V]
5
4
VCC
3
VRST
2
1
0
500 ms/div
16/31
AI09149
STM690/704/795/802/804/805/806
Figure 26. RST Output Voltage vs. Supply Voltage
6
RST OUTPUT VOLTAGE [V]
5
VCC
4
3
2
VRST
1
0
500 ms/div
AI09150
Figure 27. RST Response Time (Assertion)
6
5
VCC LEVEL [V]
VCC
4
3
VRST
2
1
0
2 µs/div
AI09151
17/31
STM690/704/795/802/804/805/806
Figure 28. RESET Response Time (Assertion)
6
VCC
5
VCC LEVEL [V]
4
3
VRST
2
1
0
2µs/div
AI09152
6
1.45
5
1.40
4
1.35
PFO
3
1.30
PFI
2
1.25
1
1.20
0
1.15
2µs/div
18/31
VPFI LEVEL [V]
VPFO LEVEL [V]
Figure 29. Power-fail Comparator Response Time (Assertion)
AI09153
STM690/704/795/802/804/805/806
6
1.45
5
1.40
4
1.35
PFO
3
1.30
PFI
2
1.25
1
1.20
0
VPFI LEVEL (V)
VPFO LEVEL (V)
Figure 30. Power-fail Comparator Response Time (De-Assertion)
1.15
2 µs/div
AI09154
Figure 31. VCC to Reset Propagation Delay vs. Temperature
PROPAGATION DELAY [µs]
60
50
40
10V/ms
30
1V/ms
0.25V/ms
20
10
0
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE [°C]
AI09155
19/31
STM690/704/795/802/804/805/806
Figure 32. Maximum Transient Duration vs. Reset Threshold Overdrive
TRANSIENT DURATION [µs]
250
200
150
100
50
0
1
10
100
1000
10000
RESET COMPARATOR OVERDRIVE, VRST – VCC [mV]
AI09156
Figure 33. E to ECON Propagation Delay vs. Temperature
3.5
E to ECON PROPAGATION DELAY [ns]
E Rising
3.0
E Falling
2.5
2.0
1.5
1.0
0.5
0
–60
–40
–20
0
20
40
60
TEMPERATURE [°C]
20/31
80
100
120
140
AI09157
STM690/704/795/802/804/805/806
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 5. Absolute Maximum Ratings
Symbol
TSTG
TSLD(1)
VIO
Parameter
Value
Unit
–55 to 150
°C
260
°C
–0.3 to VCC +0.3
V
Storage Temperature (VCC Off)
Lead Solder Temperature for 10 seconds
Input or Output Voltage
VCC/VBAT
Supply Voltage
–0.3 to 6.0
V
IO
Output Current
20
mA
PD
Power Dissipation
320
mW
Note: 1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C for between 90 to 150
seconds).
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 6, Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 6. Operating and AC Measurement Conditions
STM690/704/795/
802/804/805/806
Unit
VCC/VBAT Supply Voltage
1.0 to 5.5
V
Ambient Operating Temperature (TA)
–40 to 85
°C
≤5
ns
Input Pulse Voltages
0.2 to 0.8VCC
V
Input and Output Timing Ref. Voltages
0.3 to 0.7VCC
V
Parameter
Input Rise and Fall Times
21/31
STM690/704/795/802/804/805/806
Figure 34. E to ECON Propagation Delay Test Circuit
VCC
VCC
VBAT
3.6V
STM690/704/
795/802/804/
805/806
25Ω Equivalent
Source Impedance
E
50Ω
ECON
50Ω Cable
50pF CL(1)
50Ω
GND
AI08854
Note: 1. CL includes load capacitance and scope probe capacitance.
Figure 35. AC Testing Input/Output Waveforms
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI02568
Figure 36. MR Timing Waveform
MR
tMLRL
RST
(1)
tMLMH
trec
AI07837a
Note: 1. RST for STM805.
22/31
STM690/704/795/802/804/805/806
Figure 37. Watchdog Timing
VCC
RST
trec
tWD
WDI
AI07891
Table 7. DC and AC Characteristics
Sym
VCC,
VBAT(2)
Alternative
Description
Operating Voltage
VOUT2
ILI
TA = –40 to +85°C
1.1(3)
Typ
Max
Unit
5.5
V
40
60
µA
Excluding IOUT (VCC < 3.6V)
35
50
µA
VCC Supply Current in
Battery Back-up Mode
Excluding IOUT
(VBAT = 2.3V,
VCC = 2.0V, MR = VCC)
25
35
µA
VBAT Supply Current in
Battery Back-up Mode
Excluding IOUT
(VBAT = 3.6V)
0.4
1.0
µA
ICC
VOUT1
Min
Excluding IOUT (VCC < 5.5V)
VCC Supply Current
IBAT(4)
Test Condition(1)
VOUT Voltage (Active)
VOUT Voltage (Battery
Back-up)
IOUT1 = 5mA(5)
VCC –
0.03
VCC –
0.015
V
IOUT1 = 75mA
VCC –
0.3
VCC –
0.15
V
IOUT1 = 250µA,
VCC > 2.5V(5)
VCC –
0.0015
VCC –
0.0006
V
IOUT2 = 250µA, VBAT = 2.3V
VBAT –
0.1
VBAT –
0.034
V
VBAT –
0.14
V
IOUT2 = 1mA, VBAT = 2.3V
VCC to VOUT On-resistance
3
VBAT to VOUT On-resistance
100
4
Ω
Ω
Input Leakage Current (MR)
STM704/806 only;
MR = 0V; VCC = 3V
20
75
350
µA
Input Leakage Current (PFI)
0V = VIN = VCC
–25
2
+25
nA
Input Leakage Current (WDI)
0V = VIN = VCC
–1
+1
µA
STM804/805/795;
0V = VIN = VCC(6)
–1
+1
µA
0.7VCC
ILO
Output Leakage Current
VIH
Input High Voltage (MR, WDI)
VRST (max) < VCC < 5.5V
VIL
Input Low Voltage (MR, WDI)
VRST (max) < VCC < 5.5V
V
0.3VCC
V
23/31
STM690/704/795/802/804/805/806
Sym
Alternative
Test Condition(1)
Description
VOHB
Max
Unit
VCC = VRST (max),
ISINK = 3.2mA
0.3
V
Output Low Voltage (ECON)
VCC = VRST (max),
IOUT = 1.6mA, E = 0V
0.2VCC
V
IOL = 40µA; VCC = 1.0V;
VBAT = VCC;
TA = 0°C to 85°C
0.3
V
IOL = 200µA;
VCC = 1.2V; VBAT = VCC
0.3
V
Output Low Voltage (RST)
Output High Voltage (RST,
RST)(7)
VOH
Typ
Output Low Voltage (PFO,
RST, RST, Vccsw)
VOL
VOL
Min
ISOURCE = 1mA,
VCC = VRST (max)
2.4
V
Output High Voltage (ECON)
VCC = VRST (max),
IOUT = 1.6mA, E = VCC
0.8VCC
V
Output High Voltage (PFO)
ISOURCE = 75µA,
VCC = VRST (max)
0.8VCC
V
VOH Battery Back-up (ECON,
Vccsw, RST)
ISOURCE = 100µA,
0.8VBAT
V
Power-fail Comparator (NOT available on STM795)
VPFI
PFI Input Threshold
PFI Hysteresis
tPFD
PFI to PFO Propagation
Delay
ISC
PFO Output Short to
GND Current
PFI Falling
(VCC < 3.6V)
STM802/
804/806
1.212
1.237
1.262
V
STM690/
704/805
1.187
1.237
1.287
V
10
20
mV
PFI Rising (VCC < 3.6V)
2
VCC = 3.6V, PFO = 0V
0.1
0.75
µs
2.0
mA
Battery Switchover
VBAT > VSW
VSW
V
VBAT < VSW
VBAT
V
VBAT > VSW
VSW
V
VBAT < VSW
VBAT
V
VSW
2.4
V
Hysteresis
40
mV
Power-down
Battery Back-up
Switchover Voltage (8,9)
VSO
24/31
Power-up
STM690/704/795/802/804/805/806
Sym
Alternative
Description
Test Condition(1)
Min
Typ
Max
Unit
Reset Thresholds
VRST(10)
Reset Threshold
trec
STM690T/
704T/795T/
805T
VCC Falling
3.00
3.075
3.15
V
VCC Rising
3.00
3.085
3.17
V
STM802T/
804T/806T
VCC Falling
3.00
3.075
3.12
V
VCC Rising
3.00
3.085
3.14
V
STM690S/
704S/795S/
805S
VCC Falling
2.85
2.925
3.00
V
VCC Rising
2.85
2.935
3.02
V
STM802S/
804S/806S
VCC Falling
2.88
2.925
3.00
V
VCC Rising
2.88
2.935
3.02
V
STM690R/
704R/795R/
805R
VCC Falling
2.55
2.625
2.70
V
VCC Rising
2.55
2.635
2.72
V
STM802R/
804R/806R
VCC Falling
2.59
2.625
2.70
V
VCC Rising
2.59
2.635
2.72
V
140
200
280
ms
100
20
VCC < 3.6V
RST Pulse Width
Push-button Reset Input (STM704/806)
tMLMH
tMR
MR Pulse Width
tMLRL
tMRD
MR to RST Output Delay
ns
60
500
ns
2.24
s
Watchdog Timer (NOT available on STM704/795/806)
tWD
Watchdog Timeout Period
VRST (max) < VCC < 3.6V
1.12
1.60
WDI Pulse Width
VRST (max) < VCC < 3.6V
100
20
ns
Ω
Chip-Enable Gating (STM795 only)
E-to-ECON Resistance
VCC = VRST (max)
46
E-to-ECON Propagation Delay
VCC = VRST (max)
2
Reset-to-ECON High Delay
ISC
ECON Short Circuit Current
7
10
VCC = 3.6V, Disable Mode,
ECON = 0V
0.1
0.75
ns
µs
2.0
mA
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = VRST (max) to 5.5V; and VBAT = 2.8V (except where noted).
2. VCC supply current, logic input leakage, Watchdog functionality, Push-button Reset functionality, PFI functionality, state of RST and
RST tested at VBAT = 3.6V, and VCC = 5.5V. The state of RST or RST and PFO is tested at VCC = VCC (min). Either VCC or VBAT
can go to 0V if the other is greater than 2.0V.
3. VCC (min) = 1.0V for TA = 0°C to +85°C.
4. Tested at VBAT = 3.6V, VCC = 3.5V and 0V.
5. Guaranteed by design.
6. The leakage current measured on the RST pin (STM804/805) or RST pin (STM795) is tested with the reset output not asserted
(output high impedance).
7. Not valid for STM795/804/805 (open drain).
8. When VBAT > VCC > VSW, VOUT remains connected to VCC until VCC drops below VSW.
9. When VSW > VCC > VBAT, VOUT remains connected to VCC until VCC drops below the battery voltage (VBAT) – 75mV.
10. The reset threshold tolerance is wider for VCC rising than for VCC falling due to the 10mV (typ) hysteresis, which prevents internal
oscillation.
25/31
STM690/704/795/802/804/805/806
PACKAGE MECHANICAL
Figure 38. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mech. Drawing
h x 45˚
A2
A
C
B
ddd
e
D
8
E
H
1
A1
α
L
SO-A
Note: Drawing is not to scale.
Table 8. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
–
1.35
1.75
–
0.053
0.069
A1
–
0.10
0.25
–
0.004
0.010
B
–
0.33
0.51
–
0.013
0.020
C
–
0.19
0.25
–
0.007
0.010
D
–
4.80
5.00
–
0.189
0.197
ddd
–
–
0.10
–
–
0.004
E
–
3.80
4.00
–
0.150
0.157
e
1.27
–
–
0.050
–
–
H
–
5.80
6.20
–
0.228
0.244
h
–
0.25
0.50
–
0.010
0.020
L
–
0.40
0.90
–
0.016
0.035
α
–
0°
8°
–
0°
8°
N
26/31
8
8
STM690/704/795/802/804/805/806
Figure 39. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline
D
8
5
c
E1
1
E
4
α
A1
A
L
A2
L1
CP
b
e
TSSOP8BM
Note: Drawing is not to scale.
Table 9. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
–
–
1.10
–
–
0.043
A1
–
0.05
0.15
–
0.002
0.006
A2
0.85
0.75
0.95
0.034
0.030
0.037
b
–
0.25
0.40
–
0.010
0.016
c
–
0.13
0.23
–
0.005
0.009
CP
–
–
0.10
–
–
0.004
D
3.00
2.90
3.10
0.118
0.114
0.122
e
0.65
–
–
0.026
–
–
E
4.90
4.65
5.15
0.193
0.183
0.203
E1
3.00
2.90
3.10
0.118
0.114
0.122
L
0.55
0.40
0.70
0.022
0.016
0.030
L1
0.95
–
–
0.037
–
–
α
–
0°
6°
–
0°
6°
N
8
8
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STM690/704/795/802/804/805/806
PART NUMBERING
Table 10. Ordering Information Scheme
Example:
STM690
T
M
6
E
Device Type
STM690/704/795/802/804/805/806
Reset Threshold Voltage
T = STM690/704/795/805 = VRST = 3.00V to 3.15V
STM802/804/806 = VRST = 3.00V to 3.12V
S = STM690/704/795/805 = VRST = 2.85V to 3.00V
STM802/804/806 = VRST = 2.88V to 3.00V
R = STM690/704/795/805 = VRST = 2.55V to 2.70V
STM802/804/806 = VRST = 2.59V to 2.70V
Package
M = SO8
DS(1) = TSSOP8
Temperature Range
6 = –40 to 85°C
Shipping Method
E = Tubes (Pb-Free - ECO
PACK®)
F = Tape & Reel (Pb-Free - ECO
PACK®)
Note: 1. Contact local ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
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STM690/704/795/802/804/805/806
Table 11. Marking Description
Part Number
Reset Threshold
STM690T
3.075
STM690S
2.925
STM690R
2.625
STM704T
3.075
STM704S
2.925
STM704R
2.625
STM795T
3.075
STM795S
2.925
STM795R
2.625
STM802T
3.075
STM802S
2.925
STM802R
2.625
STM804T
3.075
STM804S
2.925
STM804R
2.625
STM805T
3.075
STM805S
2.925
STM805R
2.625
STM806T
3.075
STM806S
2.925
STM806R
2.625
Package
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
Topside Marking
690T
690S
690R
704T
704S
704R
795T
795S
795R
802T
802S
802R
804T
804S
804R
805T
805S
805R
806T
806S
806R
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STM690/704/795/802/804/805/806
REVISION HISTORY
Table 12. Document Revision History
Date
Version
October 31, 2003
1.0
First Issue
22-Dec-03
2.0
Reformatted; update characteristics (Figure 1, 3, 4, 11, 13, 14, 36; Table 1, 3, 4, 7,
9, 11)
16-Jan-04
2.1
Add Typical Operating Characteristics (Figure 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
26, 27, 28, 29, 30, 31, 32, 33)
07-Apr-04
2.2
Update characteristics (Figure 13, 25, 26, 27, 28, 31; Table 1, 3, 7)
25-May-04
3.0
Update characteristics (Table 3, 7)
02-Jul-04
4.0
Update package availability, pin description; promote document (Figure 1, 14;
Table 3, 10)
29-Sep-04
5.0
Clarify root part numbers, pin descriptions, update characteristics (Figure 2, 3, 4, 5,
6, 7, 8, 9, 10, 11, 13, 14, 34; Table 1, 3, 6, 7, 10)
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Revision Details
STM690/704/795/802/804/805/806
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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All other names are the property of their respective owners
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