STP4NB50 STP4NB50FP N-CHANNEL 500V - 2.5Ω - 3.8A - TO-220/TO-220FP PowerMesh™ MOSFET PRELIMINARY DATA TYPE STP4NB50 STP4NB50FP ■ ■ ■ ■ ■ VDSS RDS(on) ID 500 V 500 V < 2.8 Ω < 2.8 Ω 3.8 A 2.5 A TYPICAL RDS(on) = 2.5 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED VERY LOW INTRINSIC CAPACITANCES GATE CHARGE MINIMIZED DESCRIPTION Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprieraty edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics. 3 1 3 2 1 TO-220 2 TO-220FP INTERNAL SCHEMATIC DIAGRAM APPLICATIONS HIGH CURRENT, HIGH SPEED SWITCHING ■ SWITH MODE POWER SUPPLIES (SMPS) ■ DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE ■ ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value STP4NB50 VDS VDGR VGS Unit STP4NB50FP Drain-source Voltage (VGS = 0) 500 V Drain-gate Voltage (RGS = 20 kΩ) 500 V Gate- source Voltage ±30 V ID Drain Current (continuous) at TC = 25°C 3.8 2.5 A ID Drain Current (continuous) at TC = 100°C 2.4 1.6 A Drain Current (pulsed) 15.2 15.2 A 80 35 W 0.28 W/°C IDM () PTOT Total Dissipation at TC = 25°C Derating Factor dv/dt Peak Diode Recovery voltage slope VISO Insulation Withstand Voltage (DC) Tstg Storage Temperature Tj Max. Operating Junction Temperature (•)Pulse width limited by safe operating area April 2003 0.64 4.5 - V/ns 2500 V –65 to 150 °C 150 °C (1)ISD ≤4 A, di/dt ≤200A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX 1/7 STP4NB50 - STP4NB50FP THERMAL DATA TO-220 TO-220FP 1.56 3.57 Rthj-case Thermal Resistance Junction-case Max Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W Maximum Lead Temperature For Soldering Purpose 300 °C Tl °C/W AVALANCHE CHARACTERISTICS Symbol Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Parameter 3.8 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 220 mJ ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Test Conditions Min. Typ. Max. 500 Unit Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 V Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 1 µA VDS = Max Rating, TC = 125 °C 50 µA Gate-body Leakage Current (VDS = 0) VGS = ±30V ±100 nA ON (1) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 1.9 A Min. Typ. Max. Unit 2 3 4 V 2.5 2.8 Ω Typ. Max. Unit DYNAMIC Symbol gfs (1) 2/7 Parameter Forward Transconductance Test Conditions VDS > ID(on) x RDS(on)max, ID = 1.9 A VDS = 25V, f = 1 MHz, VGS = 0 Min. 2.3 S 400 pF Ciss Input Capacitance Coss Output Capacitance 62 pF Crss Reverse Transfer Capacitance 7.5 pF STP4NB50 - STP4NB50FP ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Parameter Turn-on Delay Time Rise Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge Test Conditions Min. Typ. Max. Unit VDD = 250V, ID = 1.9 A RG = 4.7Ω VGS = 10V (see test circuit, Figure 3) 11 ns 8 ns VDD = 400V, ID = 3.8 A, VGS = 10V 15 21 nC 6.5 nC 5 nC SWITCHING OFF Symbol tr(Voff) Parameter Off-voltage Rise Time tf Fall Time tc Cross-over Time Test Conditions Min. VDD = 400V, ID = 3.8 A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 5) Typ. Max. Unit 8 ns 5 ns 14 ns SOURCE DRAIN DIODE Symbol ISD ISDM (2) VSD (1) Parameter Test Conditions Min. Typ. Source-drain Current Source-drain Current (pulsed) Forward On Voltage ISD = 3.8 A, VGS = 0 trr Reverse Recovery Time Qrr Reverse Recovery Charge ISD = 3.8 A, di/dt = 100A/µs, VDD = 100V, Tj = 150°C (see test circuit, Figure 5) IRRM Reverse Recovery Current Max. Unit 3.8 A 15.2 A 1.6 V 245 ns 980 nC 9 A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3/7 STP4NB50 - STP4NB50FP Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 4/7 STP4NB50 - STP4NB50FP TO-220 MECHANICAL DATA DIM. mm. MIN. TYP inch MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 b 0.61 0.88 0.024 0.034 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 D 15.25 15.75 0.60 0.620 E 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 F 1.23 1.32 0.048 0.052 H1 6.20 6.60 0.244 0.256 J1 2.40 2.72 0.094 0.107 L 13 14 0.511 0.551 L1 3.50 3.93 0.137 0.154 L20 16.40 L30 28.90 0.645 1.137 øP 3.75 3.85 0.147 0.151 Q 2.65 2.95 0.104 0.116 5/7 STP4NB50 - STP4NB50FP TO-220FP MECHANICAL DATA mm. DIM. MIN. inch TYP MAX. MIN. TYP. MAX. A 4.4 4.6 0.173 0.181 B 2.5 2.7 0.098 0.106 D 2.5 2.75 0.098 0.108 E 0.45 0.7 0.017 0.027 F 0.75 1 0.030 0.039 F1 1.15 1.7 0.045 0.067 F2 1.15 1.7 0.045 0.067 G 4.95 5.2 0.195 0.204 G1 2.4 2.7 0.094 0.106 H 10 10.4 0.393 0.409 L2 16 0.630 L3 28.6 30.6 1.126 1.204 L4 9.8 10.6 .0385 0.417 L5 2.9 3.6 0.114 0.141 L6 15.9 16.4 0.626 0.645 9 9.3 0.354 0.366 Ø 3 3.2 0.118 0.126 B D A E L7 L3 L6 F2 H G G1 F F1 L7 L2 6/7 L5 1 2 3 L4 STP4NB50 - STP4NB50FP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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