STP60NS04Z N - CHANNEL CLAMPED 10mΩ - 60A - TO-220 FULLY PROTECTED MESH OVERLAY MOSFET PRELIMINARY DATA TYPE STP60NS04Z ■ ■ ■ ■ V DSS R DS(on) CLAMPED <0.015 Ω ID 60 A TYPICAL RDS(on) = 0.010 Ω 100% AVALANCHE TESTED LOW CAPACITANCE AND GATE CHARGE 175 oC MAXIMUM JUNCTION TEMPERATURE 3 DESCRIPTION This fully clamped Mosfet is produced by using the latest advanced Company’s Mesh Overlay process which is based on a novel strip layout. The inherent benefits of the new technology coupled with the extra clamping capabilities make this product particularly suitable for the harshest operation conditions such as those encountered in the automotive environment. Any other application requiring extra ruggedness is also recommended. 1 2 TO-220 INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ABS, SOLENOID DRIVERS ■ MOTOR CONTROL ■ DC-DC CONVERTERS ■ ABSOLUTE MAXIMUM RATINGS Symbol Value Un it V DS Drain-source Voltage (VGS = 0) Parameter CLAMPED V V DG Drain- gate Voltage CLAMPED V V GS G ate-source Voltage CLAMPED V 60 A ID Drain Current (continuous) at Tc = 25 oC o ID Drain Current (continuous) at Tc = 100 C 42 A I DG Drain Gate Current (continuous) ± 50 mA I GS G ate Source Current (continuous) ± 50 mA I DM (•) P tot Drain Current (pulsed) 240 A T otal Dissipation at Tc = 25 o C 140 W Derating Factor 0.93 W /o C V ESD (G-S ) G ate-Source ESD (HBM - C= 100pF , R=1.5 kΩ) 2 kV V ESD (G-D) G ate-Drain ESD (HBM - C= 100pF, R=1.5 kΩ) 4 kV V ESD ( D-S) Drain-Source ESD (HBM - C= 100pF, R=1.5 kΩ) 4 Ts tg Tj kV Storage Temperature -65 to 175 o Max. Operating Junction Temperature -40 to 175 o (•) Pulse width limited by safe operating area December 1999 C C ( 1) ISD ≤60 A, di/dt ≤ 300 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX 1/8 STP60NS04Z THERMAL DATA R thj -case R thj -case R thj -amb R thc-sink Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-case Typ Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature F or Soldering Purpose o 1.07 0.85 62.5 0.5 300 C/W C/W o C/W o C/W o C o AVALANCHE CHARACTERISTICS Symbo l Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max, δ < 1%) 60 A E AS Single Pulse Avalanche Energy (starting Tj = 25 o C, ID = IAR , V DD = 30 V) 400 mJ ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbo l Parameter VCLAMP Drain-Gate Breakdown Voltage Test Con ditions I D = 1 mA V GS = 0 -40 < Tj < 175 o C I DSS V DS = 16 V Zero Gate Voltage Drain Current (V GS = 0) IGSS Gate-body Leakage Current (VDS = 0) V GS = ± 10 V V GS = ± 16 V V GSS Gate-Source Breakdown Voltage I G = 100 µA Min. Typ. Max. 33 Unit V T j = 175 o C 50 µA T j = 175 oC o T j = 175 C 50 150 µA µA 18 V ON (∗) Symbo l Parameter Test Con ditions V GS(th) Gate Threshold Voltage V DS =V GS ID = 1 mA -40 < Tj < 150 o C R DS(on) Static Drain-source On Resistance V GS = 10V V GS = 16V I D(o n) On State Drain Current V DS > ID(o n) x R DS(on )ma x V GS = 10 V Min. Typ. Max. Unit 1.7 3 4.2 V 11 10 15 14 mΩ mΩ ID = 30 A ID = 30 A 60 A DYNAMIC Symbo l g f s (∗) C iss C os s C rss 2/8 Parameter Test Con ditions Forward Transconductance V DS > ID(o n) x R DS(on )ma x Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 25 V f = 1 MHz I D =30 A V GS = 0 Min. Typ. 20 30 2500 800 150 Max. Unit S 3400 1100 200 pF pF pF STP60NS04Z ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbo l Qg Q gs Q gd Parameter Total G ate Charge Gate-Source Charge Gate-Drain Charge Test Con ditions V DD = 16 V I D = 60 A Min. V GS = 10 V Typ. Max. Unit 70 20 22 100 nC nC nC Typ. Max. Unit 25 110 150 35 150 200 ns ns ns Typ. Max. Unit 60 240 A A 1.5 V SWITCHING OFF Symbo l tr (Voff) tf tc Parameter Off-voltage Rise T ime Fall T ime Cross-over Time Test Con ditions Min. V CLAMP = 30 V I D = 60 A R G =4.7 Ω V GS = 10 V (see test circuit, figure 5) SOURCE DRAIN DIODE Symbo l Parameter Test Con ditions ISD I SDM (•) Source-drain Current Source-drain Current (pulsed) V SD (∗) Forward On Voltage I SD = 60 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 60 A di/dt = 100 A/µs Tj = 150 oC V r = 25 V (see test circuit, figure 5) t rr Q rr I RRM Min. V GS = 0 65 ns 0.15 µC 4.5 A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area Safe Operating Area Thermal Impedance 3/8 STP60NS04Z Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STP60NS04Z Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Zero Gate Voltage Drain Current vs Temperature Source-drain Diode Forward Characteristics 5/8 STP60NS04Z Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STP60NS04Z TO-220 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 D1 0.107 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 14.0 0.511 L2 16.4 L4 0.645 13.0 0.551 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 DIA. 3.75 3.85 0.147 0.151 D1 C D A E L5 H2 G G1 F1 L2 F2 F Dia. L5 L9 L7 L6 L4 P011C 7/8 STP60NS04Z Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibil ity for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specific ation mentioned in this publication are subjec t to change without notice. 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