STS1C1S250 N-CHANNEL 250V - 0.9Ω - 0.75A SO-8 P-CHANNEL 250V - 2.1Ω - 0.6A SO-8 MESH OVERLAY POWER MOSFET TYPE STS1C1S250(N-Channel) STS1C1S250(P-Channel) ■ ■ ■ ■ VDSS RDS(on) ID 250 V 250 V <1.4Ω <2.8Ω 0.80 A 0.60 A TYPICAL RDS(on) (N-Channel) = 0.9 Ω TYPICAL RDS(on) (P-Channel) = 2.1 Ω GATE-SOURCE ZENER DIODE STANDARD OUTLINE FOR EASY AUTOMATED SURFACE MOUNT ASSEMBLY DESCRIPTION This complementary pair uses the Company's proprietary high voltage MESH OVERLAY™ process based on advanced strip layout and efficient edge termination. Designed for high volume manufacturing capability, it is ideal in lighting converters such as CFL supplied from 120V mains. SO-8 INTERNAL SCHEMATIC DIAGRAM APPLICATIONS LIGHTING ■ ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS Parameter Value Unit N-CHANNEL P-CHANNEL Drain-source Voltage (VGS = 0) 250 250 V Drain-gate Voltage (RGS = 20 kΩ) 250 250 V Gate- source Voltage ±25 V ID Drain Current (continuous) at TC = 25°C 0.75 0.60 A ID Drain Current (continuous) at TC = 100°C 0.47 0.38 A 3 2.4 A IDM (1) PTOT Tstg Tj Drain Current (pulsed) Total Dissipation at TC = 25°C Single Operation Total Dissipation at TC = 25°C Dual Operation Storage Temperature Max. Operating Junction Temperature 1.6 2 W –65 to 150 °C 150 °C (1)Pulse width limited by safe operating area October 2003 1/10 STS1C1S250 THERMAL DATA Rthj-amb (2) Thermal Resistance Junction-ambient Max (Single Operating) (Dual Operating) 62.5 78 °C/W (2) Mounted on 0.5 in² pad of 2oz. copper. ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS Parameter Drain-source Breakdown Voltage Test Conditions Min. Typ. Max. Unit N-CHANNEL ID = 250 µA, VGS = 0 P-CHANNEL ID = 250 µA, VGS = 0 n-ch 250 V p-ch 250 V IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C n-ch p-ch n-ch p-ch 1 1 10 10 µA µA µA µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ±20V n-ch p-ch ±10 ±10 µA µA ON (1) Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Min. Typ. Max. Unit N-CHANNEL VDS = VGS, ID = 250µA P-CHANNEL VDS = VGS, ID = 250µA Test Conditions n-ch 2 3 4 V p-ch 2 3 4 V N-CHANNEL VGS = 10V, ID = 0.40A P-CHANNEL VGS = 10V, ID = 0.30A n-ch 0.9 1.4 Ω p-ch 2.1 2.8 Ω Typ. Max. Unit DYNAMIC Symbol Parameter Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Input Resistance (3) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2/10 Test Conditions N-CHANNEL VDS = 25V, f = 1 MHz, VGS = 0 P-CHANNEL VDS = 25V, f = 1 MHz, VGS = 0 f=1 MHz Gate DC Bias=0 Test Signal Level=20mV Open Drain Min. n-ch p-ch 325 260 pF pF n-ch p-ch 51 52 pF pF n-ch p-ch 24 25.5 pF pF n-ch p-ch 6 6 Ω Ω STS1C1S250 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Parameter Turn-on Delay Time Rise Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge Test Conditions Min. Typ. Max. Unit N-CHANNEL VDD = 125V, ID = 1.5A RG = 4.7Ω VGS = 10V P-CHANNEL VDD = 125V, ID = 1.5A RG = 4.7Ω VGS = 10V (Resistive, see Figure 3) n-ch p-ch 9 12 ns ns n-ch p-ch 11 22 ns ns N-CHANNEL VDD =200V, ID=1.5A, VGS = 10V P-CHANNEL VDD = 200V, ID= 1.5A, VGS = 10V n-ch p-ch n-ch p-ch n-ch p-ch 15 16 1.9 1.4 7 7.6 20 21 nC nC nC nC nC nC Typ. Max. Unit SWITCHING OFF Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions N-CHANNEL VDD = 125V, ID = 1.5A, RG = 4.7Ω, VGS = 10V P-CHANNEL VDD = 200V, ID = 1.5A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 5) Min. n-ch p-ch 31 29.5 ns ns n-ch p-ch 11 7 ns ns SOURCE DRAIN DIODE Symbol ISD Parameter Test Conditions Source-drain Current Min. Max. Unit n-ch p-ch n-ch p-ch 0.75 0.6 3 2.4 A A A A 1.5 1.5 V V ISDM (4) Source-drain Current (pulsed) VSD (5) Forward On Voltage ISD = 3A, VGS = 0 ISD = 3A, VGS = 0 n-ch p-ch trr Reverse Recovery Time Qrr Reverse Recovery Charge IRRM Reverse Recovery Curren N-CHANNEL ISD = 0.8A, di/dt = 100A/µs, VDD = 50V, Tj = 150°C P-CHANNEL ISD = 0.60A, di/dt = 100A/µs, VDD = 40V, Tj = 150°C (see test circuit, Figure 5) n-ch p-ch n-ch p-ch n-ch p-ch Typ. 127 143 450 806 7 11 ns ns nC nC A A GATE-SOURCE ZENER DIODE Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs=± 500 µA (Open Drain) Min. ± 25 Typ. Max. Unit V (4) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (5) Pulse width limited by safe operating area PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 3/10 STS1C1S250 Safe Operating Area n-ch Thermal Impedance for Complementary pair Output Characteristics n-ch Transfer Characteristics n-ch Transconductance n-ch 4/10 Static Drain-source On Resistance n-ch STS1C1S250 Gate Charge vs Gate-source Voltage n-ch Capacitance Variations n-ch Norm. Gate Thereshold Voltage vs Temp n-ch Norm. On Resistance vs Temperature n-ch Source-drainDiodeForwardCharacteristicsn-ch Normalized BVDSS vs Temperature n-ch 5/10 STS1C1S250 Safe Operating Area p-ch Thermal Impedance for Complementary pair Output Characteristics p-ch Transfer Characteristics p-ch Transconductance p-ch 6/10 Static Drain-source On Resistance p-ch STS1C1S250 Gate Charge vs Gate-source Voltage p-ch Capacitance Variations p-ch Norm. Gate Thereshold Voltage vs Temp p-ch NormalizedOnResistancevsTemperaturep-ch Source-drainDiodeForwardCharacteristicsp-ch Normalized BVDSS vs Temperature p-ch 7/10 STS1C1S250 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 8/10 STS1C1S250 SO-8 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.25 a2 MAX. 0.003 0.009 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 5.0 0.188 0.196 6.2 0.228 c1 45 (typ.) D 4.8 E 5.8 e 1.27 e3 0.244 0.050 3.81 0.150 F 3.8 4.0 0.14 0.157 L 0.4 1.27 0.015 0.050 M S 0.6 0.023 8 (max.) 0016023 9/10 STS1C1S250 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 10/10