STS2NF100 N-CHANNEL 100V - 0.23 Ω - 6A SO-8 STripFET™ II POWER MOSFET ■ ■ ■ ■ TYPE VDSS RDS(on) ID STS2NF100 100 V <0.26 Ω 6A TYPICAL RDS(on) = 0.23 Ω EXCEPTIONAL dv/dt CAPABILITY 100 % AVALANCHE TESTED APPLICATION ORIENTED CHARACTERIZATION SO-8 DESCRIPTION This MOSFET series realized with STMicroelectronics unique STripFET process has specifically been designed to minimize input capacitance and gate charge. It is therefore suitable as primary switch in advanced highefficiency, high-frequency isolated DC-DC converters for Telecom and Computer applications. It is also intended for any applications with low gate drive requirements. INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ HIGH-EFFICIENCY DC-DC CONVERTERS ■ UPS AND MOTOR CONTROL ABSOLUTE MAXIMUM RATINGS Symbol VDS Parameter Drain-source Voltage (VGS = 0) Unit 100 V Drain-gate Voltage (RGS = 20 kΩ) 100 V VGS Gate- source Voltage ± 20 V ID(•) Drain Current (continuous) at TC = 25°C 2 A ID Drain Current (continuous) at TC = 100°C 1.3 A VDGR IDM(••) Ptot Drain Current (pulsed) 8 A 2.5 W 0.016 W/°C Peak Diode Recovery voltage slope 40 V/ns Single Pulse Avalanche Energy 200 mJ -65 to 175 °C Total Dissipation at TC = 25°C Derating Factor dV/dt (1) EAS (2) Tstg Tj Storage Temperature Max. Operating Junction Temperature (••) Pulse width limited by safe operating area. (•) Current limited by the package October 2002 . Value (1) ISD ≤2A, di/dt ≤300A/µs, VDD ≤ V (BR)DSS, Tj ≤ T JMAX (2) Starting T j = 25 oC, ID = 3A, VDD = 50V 1/8 STS2NF100 THERMAL DATA Rthj-amb Tj Tstg (*)Thermal Resistance Junction-ambient Thermal Operating Junction-ambient Storage Temperature 50 -55 to 150 -55 to 150 °C/W °C °C (*) Mounted on FR-4 board (t [ 10 sec.) ELECTRICAL CHARACTERISTICS (Tcase = 25 °C unless otherwise specified) OFF Symbol Parameter Test Conditions Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating TC = 125°C IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20 V V(BR)DSS Min. Typ. Max. 100 Unit V 1 10 µA µA ±100 nA ON (*) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS ID = 250 µA RDS(on) Static Drain-source On Resistance VGS = 10 V ID = 1 A Min. Typ. Max. Unit 2 3 4 V 0.23 0.26 Ω Typ. Max. Unit DYNAMIC Symbol 2/8 Parameter Test Conditions Min. gfs (*) Forward Transconductance VDS>ID(on)xRDS(on)max ID = 1 A 0.5 S Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25V, f = 1 MHz, VGS = 0 280 45 20 pF pF pF STS2NF100 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time ID = 1 A VDD = 50 V RG = 4.7 Ω VGS = 10 V (Resistive Load, Figure 3) 6 10 ns ns Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD= 80V ID= 1A VGS=10V 10 2.5 4 nC nC nC SWITCHING OFF Symbol Parameter Test Conditions Min. Typ. Max. Unit td(off) tf Turn-off Delay Time Fall Time ID = 1 A VDD = 50 V RG = 4.7Ω, VGS = 10 V (Resistive Load, Figure 3) 20 3 ns ns tr(Voff) tf tc Off-Voltage Rise Time Fall Time Cross-over Time ID = 1 A Vclamp = 80 V RG = 4.7Ω VGS = 10 V (Inductive Load, Figure 5) 19 8 15 ns ns ns SOURCE DRAIN DIODE Symbol Parameter ISD ISDM (•) Source-drain Current Source-drain Current (pulsed) VSD (*) Forward On Voltage ISD = 2 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current di/dt = 100A/µs ISD = 2 A VDD = 10 V Tj = 150°C (see test circuit, Figure 5) trr Qrr IRRM Test Conditions Min. Typ. VGS = 0 70 175 5 Max. Unit 6 24 A A 1.3 V ns nC A (*)Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (•)Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/8 STS2NF100 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STS2NF100 Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature Source-drain Diode Forward Characteristics . . . 5/8 STS2NF100 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STS2NF100 SO-8 MECHANICAL DATA mm DIM. MIN. TYP. A a1 MAX. MIN. TYP. 1.75 0.1 0.003 0.009 1.65 0.65 MAX. 0.068 0.25 a2 a3 inch 0.064 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 c1 45 (typ.) D 4.8 5.0 0.188 0.196 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 F 3.8 4.0 0.14 0.157 L 0.4 1.27 0.015 0.050 M S 0.6 0.023 8 (max.) 0016023 7/8 STS2NF100 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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