STV0042A SATELLITE SOUND AND VIDEO PROCESSORS PRODUCT PREVIEW VIDEO COMPOSITE VIDEO 6-bit 0 to 12.7dB GAIN CONTROL COMPOSITE VIDEO SELECTABLE INVERTER TWO SELECTABLE VIDEO DE-EMPHASIS NETWORKS 4 x 2 VIDEO MATRIX HIGH IMPEDANCE MODE VIDEO OUTPUTS FOR TWIN TUNER APPLICATIONS MISCELLANEOUS 22kHz TONE GENERATIONFOR LNB CONTROL I2C BUS CONTROL : CHIP ADDRESSES = 06HEX LOW POWER STAND-BY MODE WITH ACTIVE AUDIO AND VIDEO MATRIXES DESCRIPTION The STV0042A BICMOS integrated circuit realizes all the necessary signal processing from the tuner to the Audio/Video input and output connectors regardless the satellite system. The STV0042 is intended for low cost satellite receiver application. March 1997 SHRINK42 (Plastic Package) ORDER CODE : STV0042A PIN CONNECTIONS FC R 1 42 A GND R PK IN 2 41 FC L SUM OUT 3 40 PK OUT VOL R 4 39 IREF S1 VID OUT 5 38 CPUMP R S2 VID OUT 6 37 U75 R VOL L 7 36 DET R S2 VID RTN 8 35 AMPLK R S2 OUT L 9 34 A 12V CLAMP IN 10 33 VREF S2 OUT R 11 32 A GND L UNCL DEEM 12 31 AGC R VIDEEM2/22kHz 13 30 AMPLK L V 12V 14 29 U75 L VIDEEM1 15 28 DET L V GND 16 27 CPUMP L B-BAND IN 17 26 GND 5V S2 RTN L 18 25 VDD 5V S2 RTN R 19 24 XTL FM IN 20 23 SDA AGC L 21 22 SCL 0042A-01.EPS .. . . .. . . . . . .. .. . SOUND TWO INDEPENDENT SOUND DEMODULATORS PLL DEMODULATION WITH 5-10MHz FREQUENCY SYNTHESIS PROGRAMMABLE FM DEMODULATOR BANDWIDTH ACCOMODATING FM DEVIATIONS FROM ±30kHz TILL ±400kHz PROGRAMMABLE 50/75µs OR NO DE-EMPHASIS DYNAMIC NOISE REDUCTION ONE OR TWO AUXILIARY AUDIO INPUTS AND OUTPUTS GAIN CONTROLLED AND MUTEABLE AUDIO OUTPUTS HIGH IMPEDANCE MODE AUDIO OUTPUTS FOR TWIN TUNER APPLICATIONS 1/24 STV0042A PIN ASSIGNMENT Pin Number Name 1 FC R 3 SUM OUT 2 PK IN Noise Reduction Peak Detector Input 4 VOL R Volume Controlled Audio Out Right 5 S1 VID OUT 6 S2 VID OUT 7 VOL L 8 S2 VID RTN 9 S2 OUT L Fixed Level Audio Output Left 10 CLAMP IN Sync-Tip Clamp Input 11 S2 OUT R Fixed Level Audio Output Right 12 UNCL DEEM 13 VIDEEM2/22kHz 2/24 V 12V 15 VIDEEM1 Noise Reduction Summing Output TV-Scart 1 Video Output VCR-Scart 2 Video Output Volume Controlled Audio Out Left VCR-Scart 2 Video Return Unclamped Deemphasized Video Output Video Deemphasis 2 or 22kHz Output Video 12V Supply Video Deemphasis 1 16 V GND 17 B-BAND IN Video Ground 18 S2 RTN L Auxiliary Audio Return Left 19 S2 RTN R Auxiliary Audio Return Right 20 FM IN FM Demodulator Input 21 AGC L AGC Peak Detector Capacitor Left 22 SCL I2C Bus Clock 23 SDA I C Bus Data 24 XTL 4/8MHz Quartz Crystal or Clock Input Base Band Input 2 25 VDD 5V 26 GND 5V Digital 5V Power Supply 27 CPUMP L 28 DET L FM PLL Filter Left 29 U75 L Deemphasis Time Constant Left 30 AMPLK L 31 AGC R 32 A GND L Digital Power Ground FM PLL Charge Pump Capacitor Left Amplitude Detector Capacitor Left AGC Peak Detector Capacitor Right Audio Ground 2.4V Reference 33 VREF 34 A 12V 35 AMPLK R 36 DET R FM PLL Filter Right 37 U75 R Deemphasis Time Constant Right 38 CPUMP R 39 IREF 40 PK OUT 41 FC L 42 A GND R Audio 12V Supply Amplitude Detector Capacitor Left FM PLL Charge Pump Capacitor Right Current Reference Resistor Noise Reduction Peak Detector Output Audio Roll-off Left Audio Ground 0042A-01.TBL 14 Function Audio Roll-off Right STV0042A PIN DESCRIPTION 1 - Sound Detection FMIN This is the input to the two FM demodulators. It feeds two AGC amplifiers with a bandwidth of at least 5-10MHz. There is one amplifier for each channel both with the same input. The AGC amplifiers have a 0dB to +40dB range. ZIN = 5kΩ, Min input = 2mVPP per subcarrier. Max input = 500mVPP (max when all inputs are added together, when their phases coincide). AGC L, AGC R AGC amplifiers peak detector capacitor connections. The output current has an attack/decayratio of 1:32. That is the ramp up current is approximately 5µA and decay current is approximately 160µA. 11V gives maximum gain. These pins are also driven by a circuit monitoring the voltage on AMPLK L and AMPLK R respectively. AMPLK L, AMPLK R The outputs of amplitude detectors LEFT and RIGHT. Each requires a capacitor and a resistor to GND. The voltage across this is used to decide whether there is a signal being received by the FM detector. The level detector output drives a bit in the detector I2C bus control block. AMPLK L and AMPLK R drive also respectively AGC L and AGC R. For instance when the voltage on AMPLK L is > (VREF + 1 VBE) it sinks current to VREF from pin AGCL to reduce the AGC gain. DET L, DET R Respectively the outputs of the FM phase detector left and right. This is for the connection of an external loop filter for the PLL. The output is a push-pull current source. CPUMP L, CPUMP R The output from the frequency synthesizer is a push-pullcurrent sourcewhich requiresa capacitor to ground to derive a voltage to pull the VCO to the target frequency. The output is ±100µA to achieve lockand ±2µA during lock to provide a trackingtime constant of approximately 10Hz. VREF This is the audio processor voltage reference used through out the FM/audio section of the chip. As such it is essential that it is well decoupled to ground to reduce as far as possible the risk of crosstalk and noise injection. This voltage is derived directly from the bandgap reference of 2.4V. The VREF output can sink up to 500µA in normal operation and 100µA when in stand-by. IREF This is a bufferedVREF outputto an off-chip resistor to produce an accurate current reference, within the chip, for the biasing of amplifiers with current outputs into filters. It is also required for the Noise reduction circuit to provide accurate roll-off frequencies. This pin should not be decoupled as it would inject current noise. The target current is 50µA ±2% thus a 47.5kΩ ±1% is required. A 12V Double bonded main power pin for the audio/FM section of the chip. The two bond connections are to the ESD and to power the circuit and on chip regulators/references. A GND L This ground pin is double bonded : 1) to channel LEFT : RF section & VCO, 2) to both AGC amplifiers, channel LEFT and RIGHT audio filter section. A GND R This ground pin is double bonded : 1) to the volume control, noise reduction system, ESD + Mux + VREF 2) to channel right : RF section & VCO 2 - Baseband Audio Processing PK OUT The noise reduction control loop peak detector output requires a capacitor to ground from this pin, and a resistor to VREF pin to give some accurate decaytimeconstant.An on chip5kΩ ±25 % resistor and external capacitor give the attack time. PK IN This pin is an input to a control loop peak detector and is connectedto the output of the offchip control loop band pass filter. SUM OUT The two audio demodulated signals are summed together by means of an amplifier with a gain of 0.5. If both inputs are 1V then the output is 1V. This amplifier has an input follower buffer which gives a VBE offset in the DC bias voltage. Thus the filter which this amplifier drives must include AC coupling to the next stage (PK IN Pin). FC L, FC R The variable bandwidth transconductance amplifier has a current output which is variable depending on the input signal amplitude as defined by the control loop of the noise reduction. The output current is then dumped into an off-chip capacitor which together with the accurate current reference define the min/max rolloff frequencies.A resistor in series with a capacitor is connected to ground from these two pins. 3/24 STV0042A PIN DESCRIPTION (continued) U75 L, U75 R External deemphasis networks for channels left and right. For each channel a capacitor and resistor in parallel of 75µs time constant are connectedbetween hereandVREF to provide 75µs de-emphasis.Internally selectable is an internal resistor that can be programmedtobeaddedin paralleltherebyconvertingthe networktoapprox50µs de-emphasis(see controlblock map).The value of theinternalresistors is30kΩ ±30%. Theamplifierforthisfilterisvoltageinput,currentoutput; with ±500mV input the outputwill be ±55µA. video at the clamp input is only 1VPP. This clamped video which is de-emphasised, filtered and clamped (energydispersalremoved) isnormal, negativesyncs, video. This signal drives the Video Matrix input called Normal Video. It has a weak (1.0µA ±15 %) stable current source pulling the input towards GND. Otherwise the input impedance is very high at DC to 1kHz ZIN > 2MΩ. Video bandwidth through this is -1dB at 5.5MHz. The CLAMP input DC restore voltageis then usedas a means forgettingthecorrect DC voltageon the SCART outputs. VOL L, VOL R Themainaudiooutputfromthevolumecontrolamplifier the signal to get output signals as high as 2VRMS (+12dB)on a DCbias of 4.8V.Controlis from +12dBto -26.75dB plus Mute with 1.25dB steps. This amplifier has short circuit protection and is intended to drive a SCART connector directly via AC coupling and meets thestandardSCARTdriverequirements.Theseoutputs featurehigh impedancemode for parallelconnection. S2 VID RTN External video input 1.0VPP AC coupled 75Ω source impedance. This input has a DC restoration clamp on its input. The clamp sink current is 1µA ±15% with the buffer ZIN > 1MΩ. This signal is an input to the Video Matrix. S2 OUT L, S2 OUT R These audio outputs are sourced directly from the audioMUX, andas a result do not includeany volume controlfunction.Theywill outputa1VRMS signalbiased at4.8V.They are shortcircuit protected.Theseoutputs feature high impedance mode for parallel connection and meetSCART drive requirement. S2 RTN L, S2 RTN R These pins allow auxiliary audio signals to be connected to the audio processor and hence makes use of the on-chip volume control. For additional details please refer to the audio switching table. 3 - Video Processing B-BAND IN AC-coupled video input from a tuner. ZIN > 10kΩ ±25%. This drives an on-chipvideo amplifier.TheotherinputofthisampisACgroundedbybeing connectedto an internal VREF. The videoamplifierhas selectablegain from 0dBto 12.7dBin 63 stepsand its output signalcan be selected normal or inverted. UNCL DEEM Deemphasized still unclamped output. It is also an input of the video matrix. VIDEEM1 Connected to an external de-emphasis network (for instance 625 lines PAL de-emphasis). VIDEEM2 / 22kHz Connected to an external de-emphasis network (for instance 525 lines NTSC or other video de-emphasis).Alternatively a precise 22kHz tone may be output by I2C bus control. CLAMP IN This pin clampsthemost negativeextremeof theinput (the sync tips) to 2.7VDC (orappropriatevoltage). The 4/24 S1 VID OUT, S2 VID OUT Videodrivers for SCART 1 and SCART 2. An external emitterfollowerbufferis required to drive a 150Ω load. The average DC voltage to be 1.5V on the O/P. The signalisvideo2.0VPP 5.5MHzBWwith synctip = 1.2V. These pins get signals from the Video Matrix. The signalselected from theVideo Matrix foroutputon this pin is controlled by a control register. This output also featureahighimpedancemodeforparallelconnection. V 12V +12V double bonded : ESD+guard rings and video circuit power. V GND Doubled bonded. Clean VID IN GND. Strategically placed video power ground connection to reduce video currents getting into the rest of the circuit. 4 - Control Block GND 5V The main power ground connection for the control logic, registers, the I2C bus interface, synthesizer & watchdog and XTLOSC. VDD 5V Digital +5V power supply. SCL This is the I2C busclock line. Clock = DC to 100kHz. Requires external pull up eg. 10kΩ to 5V. SDA This is the I2C bus data line. Requires external pull up eg. 10kΩ to 5V. XTL This pin allows for the on-chip oscillator to be either used with a crystal to ground of 4MHz or 8MHz, or to be driven by an external clock source. The external source can be either 4MHz or 8MHz. A programmablebit in the control block removes a ÷2 block when the 4MHz option is selected. STV0042A GENERAL BLOCK DIAGRAM B-BAND 2 Video Processing From Tuner 4x2 Video Matrix 2 From VCR/Decoder 2 1 To TV, VCR/Decoder FM Demodulation 2 Channels From Tuner Audio Matrix + Volume Noise Reduction + Deemphasis 2 22kHz to LNB 0042A-02.EPS I2C Bus Interface Active in Stand-by STV0042A VIDEO PROCESSING BLOCK DIAGRAM LPF NTSC PAL VIDEEM2/22kHz UNCL DEEM VIDEEM1 13 15 12 22kHz TONE ÷2 B-BAND IN 17 G Deemphasized ±1 Baseband S2 VID RTN 10 CLAMP 8 CLAMP Normal VCR / Decoder Return STV0042A 6 S2 VID OUT To Decoder or VCR 5 0042A-03.EPS CLAMP IN S1 VID OUT To TV 5/24 STV0042A AUDIO PROCESSING BLOCK DIAGRAM (CHANNEL RIGHT) STV0042A a K2 ANRS a AUDIO DEEMPHASIS a K1 b c MONO STEREO b K3 AUDIO R 5 b c K5 6dB U75 R 11 4 VOL R 37 S2 OUT R 1 41 FC L PK IN PK OUT 3 FC R PLL FILTER 19 40 2 S2 RTN R DET R 36 SUM OUT -6dB TV 0042A-04.EPS DECODER OR VCR AUDIO PROCESSING BLOCK DIAGRAM (CHANNEL LEFT) STV0042A a K2 ANRS a AUDIO DEEMPHASIS a K1 b c MONO STEREO b K3 AUDIO L 5 b c K5 6dB U75 L 9 7 VOL L 29 S2 OUT L 1 41 FC L PK IN PK OUT 3 FC R PLL FILTER 18 40 2 S2 RTN L DET L 28 SUM OUT -6dB DECODER OR VCR 6/24 0042A-05.EPS TV STV0042A AUDIO SWITCHING AUDIO DEEMPHASIS + ANRS K 1a K2 a b1 b2 a b1 b2 K 5b K 5c AUDIO PLL K 1c VOL OUT No ANRS, No De-emphasis No ANRS, 50µs No ANRS, 75µs ANRS, No De-emphasis ANRS, 50µs ANRS, 75µs K 5a AUX OUT 0042A-06.EPS AUX IN K3 ON ON ON OFF OFF OFF FM DEMODULATION BLOCK DIAGRAM SW1 FM IN AGC LEVEL DETECTOR 1 Phase Detect DET R AUDIO R FM dev. Select. Bias AGC R CPUMP R LEVEL DETECTOR 2 VREF Amp. Detect AMPLK R 90 VCO 0 SW2 WATCHDOG VREF Reg8 b4 SYNTHESIZER SW4 AUDIO L SW3 AGC LEVEL DETECTOR 1 Phase Detect DET L FM dev. Select. Bias AGC L CPUMP L LEVEL DETECTOR 2 VREF Amp. Detect AMPLK L 90 VCO 0 VREF Reg8 b0 0042A-07.EPS WATCHDOG STV0042A 7/24 STV0042A CIRCUIT DESCRIPTION 1 - Video Section The composite video is first set to a standard level by means of a 64 step gain controlled amplifier. In the casethat themodulationis negative,an inverter can be switched in. One of two different external video de-emphasis networks (for instance PAL and NTSC) is selectable by an integrated bus controlled switch. Then energy dispersal is removed by a sync tip clamping circuit, which is used on all inputs to a video switching matrix, thus making sure that no DC steps occur when switching video sources. The matrix can be used to feed video to and from decoders, VCR’s and TV’s. Additionaly all the video outputs are tristate type (high impedance mode is supported), allowing a simple parallel connections to the scarts (Twin tuner applications). 2 - Audio Section The two audio channels are totally independentexcept for the possibility given to output on both channels only one of the selected input audio channels. To allow a very cost effective application, each channel uses PLL demodulation. Neither external complex filter nor ceramic filters are needed. The frequency of the demodulated subcarrier is chosen by a frequency synthesizer which sets the frequency of the internal local oscillator by comparing its phase with the internally generated reference. When the frequency is reached, the microprocessor switches in the PLL and the demodulationstarts. Atany moment the microprocessor can read from the device (watchdog registers) the actual frequency to which the PLL is locked. It canalso verify that a carrier is present at the wanted frequency(by reading AMPLK status bit) thanks to a synchronous amplitude detector, which is also used for the audio input AGC. In order to maintain constant amplitude of the 8/24 recovered audio regardless of variations between satellites or subcarriers, the PLL loop gain may be programmed from 56 values. Any frequency deviation can be accomodated (from ±30kHz till ±400kHz). In the typical application, the STV0042A offers two audio de-emphasis 75µs and 50µs. When required a J17 de-emphasis can be implemented by using specific applicationdiagram (see Application Note : AN838, Chapter 4.2). A dynamic noise reduction system (ANRS) is integrated into the STV0042A using a lowpass filter, the cut-off frequency of which is controlled by the amplitude of the audio after insertion of a bandpass filter. Two types of audio outputs are provided : one is a fixed 1VRMS and the other is a gain controlled 2VRMS max. The control range being from +12dB to -26.75dBwith 1.25dB steps. This output canalso be muted. A matrix is implemented to feed audio to and from decoders VCR’s and TV’s. Noise reduction system and de-emphasis can be inserted or by-passed through bus control. Also all the audio outputs are tristate-type (high impedance mode is supported), allowing a simple parallel connections to the scarts (Twin tuner applications). 3 - Others A 22kHz tone is generated for LNB control. It is selectable by bus control and available on one of the two pins connected to the external video de-emphasis networks. By means of the I2C bus there is the possibility to drive the ICs into a low power consumption mode with active audio and video matrixes. Independantly from the main power mode, each individual audio and video output can be driven to high impedance mode. STV0042A Symbol Parameter VCC VDD Supply Voltage P tot Total Power Dissipation Toper Operating Ambient Temperature Tstg Storage Temperature Value Unit 15 7.0 V V 900 mW 0, + 70 o C -55, + 150 o C 0042A-02.TBL ABSOLUTE MAXIMUM RATINGS Symbol Rth(j-a) Parameter Value Thermal Resistance Junction-ambient Unit o C/W 60 0042A-03.TBL THERMAL DATA DC AND AC ELECTRICAL CHARACTERISTICS (VCC = 12V, VDD = 5V, Tamb = 25oC unless otherwise specified) Symbol Parameter VCC VDD Sypply Voltage IQ CC IQ DD Supply Current Supply Current at Low Power Mode IQLPCC IQLPDD Test Conditions Min. Typ. Max. Unit 11.4 4.75 12 5.0 12.6 5.25 V V All audio and all video outputs activated 55 8 70 15 mA mA All audio and all video outputs are in high impedance mode 27 6 35 9 mA mA 500 mVPP 3.30 V 5 MHz AUDIO DEMODULATOR FMIN FM Subcarrier Input Level (Pin FMIN for AGC action) VCO locked on carrier at 6MHz 560kΩ load on AMPLOCK Pins 180kΩ load on DET Pins DETH Detector 1 and 2 (AMPLOCK Pins) (Threshold for activating Level Detector 2) 8mVPP ≤ FMIN ≤ 500mVPP Carrier without modulation VCOMI VCO Mini Frequency VCC : 11.4 to 12.6V, Tamb : 0 to 70oC VCOMA VCO Maxi Frequency 5 2.90 3.10 10 MHz AP50 1kHz Audio Level at PLL output (DET Pins) 0.5VPP 50kHz dev. FM input, Coarse deviation set to 50kHz (Reg. 05 = 36HEX) 0.6 1 1.35 VPP APA50 1kHz Audio Level at PLL output (DET Pins) 0.5VPP 50kHz dev. FM input, Coarse and fine settings used 0.92 1 1.08 VPP FMBW FM Demodulator Bandwidth Gain at 12kHz versus 1kHz 180kΩ, 82kΩ 22pF on DET Pins 0 0.3 1 dB DPCO Digital Phase Comparator Output Current (CPUMP Pins) Average sink and source current to external capacitor µA 60 AUTOMATIC NOISE REDUCTION SYSTEM Output Level (Pin SUMOUT) 1VPP on left and right channel 0.9 1 1.1 VPP 4.0 5.4 6.8 kΩ Level Detector Output Resistance (Pins PK OUT) NDFT Level Detector Fall Time Constant (Pins PK OUT) External 22nF to GND and 1.2MΩ to VREF NDLL Bias Level (Pins PK OUT) No audio in 2.40 V LLCF Noise Reduction Cut-off Frequency at Low Level Audio 100mVPP on DET Pins, External capacitor 330pF (FC Pins) 0.85 kHz HLCF Noise Reduction Cut-off Frequency at High Level Audio 1VPP on DET Pins, External capacitor 330pF (FC Pins) 7 kHz 26.4 ms 9/24 0042A-04.TBL LRS LDOR STV0042A DC AND AC ELECTRICAL CHARACTERISTICS (continued) (VCC = 12V, VDD = 5V, Tamb = 25oC unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Unit AUDIO OUTPUT (Pins VOL OUT R, VOL OUT L) DCOL DC Output Level AOLN Audio Output Level with Reg 00 = 1A FM input as for APA50 No de-emphasis, No pre-emphasis No noise reduction 1.5 1.9 4.8 2.34 VPP AOL50 Audio Output Level with Reg 00 = 1A FM input as for APA50 50µs de-emphasis, 27kΩ//2.7nF load No pre-emphasis, No noise reduction 2.0 3.3 4.0 VPP AOL75 Audio Output Level with Reg 00 = 1A FM input as for APA50 75µs de-emphasis, 27kΩ//2.7nF load No pre-emphasis, No noise reduction 2.0 3.3 4.0 VPP AMA1 Audio Output Attenuation with Mute-on. Reg 00 = 00. 1VPP - 1kHz from S2 RTN Pins 60 65 dB MXAT Max Attenuation before Mute. Reg 00 = 01. 1kHz, from S2 RTN Pins 32.75 dB MXAG Audio Gain. Reg 00 = 1F. 1kHz, from S2 RTN Pins ASTP Attenuation of each of the 31 steps 1kHz 1.25 dB THDA1 THD with Reg 00 = 1A 1VPP -1kHz from S2 RTN Pins 0.15 % THDA2 THD with Reg 00 = 1A 2VPP -1kHz from S2 RTN Pins 0.3 1 % THDFM THD with Reg 00 = 1A FM input as for APA50 75µs de-emphasis, ANRS ON 0.3 1 % Audio Channel Separation 1VPP -1kHz on S2 RTN Pins 74 dB Audio Channel Separation at 1kHz - 0.5 VPP - 50kHz deviation FM input on one channel - 0.5VPP no deviation FM input on the other channel - Reg 05 = 36HEX - 75µs de-emphasis, no ANRS 60 dB SNFM Signal to Noise Ratio FM input as for APA50, 75µs de-emphasis, no ANRS, Unweighted 56 dB SNFMNR Signal to Noise Ratio FM input as for APA50 75µs de-emphasis, ANRS ON, Unweighted 69 dB Audio Output Impedance Low impedance mode High impedance mode ACS ACSFM ZOUT L ZOUT H 5 60 30 6 V 18 44 7 55 dB Ω kΩ AUXILIARY AUDIO OUTPUT (Pins S2 OUT R, S2 OUT L) DC output level Aux. input pins open circuit AOLNS Audio Output Level on S2 FM input as for APA50 No de-emphasis, No pre-emphasis No noise reduction 1.55 2 2.42 VPP AOL50S Audio Output Level on S2 FM input as for APA50 50µs de-emphasis, 27kΩ//2.7nF load No pre-emphasis, No noise reduction 2.0 3.4 4.0 VPP AOL75S Audio Output Level on S2 FM input as for APA50 75µs de-emphasis, 27kΩ//2.7nF load No pre-emphasis, No noise reduction 2.0 3.4 4.0 VPP 0.3 1 % 60 44 100 55 Ω kΩ THDAOFM THD on S2 ZOUT L ZOUT H 10/24 Audio Output Impedance 4.8 FM input as for APA50 75µs de-emphasis, no ANRS Low impedance mode High impedance mode 30 V 0042A-05.TBL DCOLAO STV0042A DC AND AC ELECTRICAL CHARACTERISTICS (continued) (VCC = 12V, VDD = 5V, Tamb = 25oC unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Unit RESET RTCCU End of Reset Threshold for VCC VDD = 5V, VCC going up 8.7 V RTCCD Start of Reset Threshold for VCC VDD = 5V, VCC going down 7.9 V RTDDU End of Reset Threshold for VDD VCC = 12V, VDD going up 3.8 V RTDDD Start of Reset Threshold for VDD VCC = 12V, VDD going down 3.5 V COMPOSITE SIGNAL PROCESSING VIDC ZVI VID IN External load current < 1µA VID IN Input Impedance DEODC DC Output Level (Pins VIDEEM) DEOMX Max AC Level before Clipping (Pins VIDEEM) GV = 0dB, Reg 01 = 00 DGV Gain error vs GV @ 100kHz GV = 0 to 12.7dB, Reg 01 = 00 → 3F INVG Inverter Gain 2.25 2.45 2.65 V 7 11 14 kΩ 2.25 2.45 2.65 V 2 VPP -0.5 0 0.5 -0.9 -1 -1.1 VISOG Video Input to SCART Output Gain De-emphasis amplifier mounted in unity gain, Normal video selected -1 0 1 DEBW Bandwidth for 1VPP input measured on Pins VIDEEM 10 DFG ITMOD @ - 3dB with GV = 0dB, Reg 01 = 00 dB MHz Differential Gain on Sync Pulses GV = 0dB, 1VPP CVBS + 0.5V PP measured on Pins VIDEEM 25Hz sawtooth (input : VID IN) 1 Intermodulation of FM subcarriers 7.02 and 7.2MHz sub-carriers, with chroma subcarrier 12.2dB lower than chroma dB -60 % dB CLAMP STAGES (Pins CLAMP IN, S2) ISKC Clamp Input Sink Current VIN = 3V 0.5 1 1.5 µA ISCC Clamp Input Source Current VIN = 2V 40 50 60 µA VIDEO MATRIX Output Level on any Output when 1VPP CVBS input is selected for any other output @ 5MHz BFG Output Buffer Gain (Pins S1 VID OUT, S2 VID OUT) @ 100kHz DC Output Level High impedance mode Video Output Impedance High impedance mode DCOLVH ZOUT HV VCL Sync Tip Level on Selected Outputs 1VPP CVBS through 10nF on input (Pins S1 VID OUT, S2 VID OUT) -60 dB 1.87 2 2.13 0 0.2 V 16 23 30 kΩ 1.05 1.3 1.55 V 11/24 0042A-06.TBL XTK STV0042A PIN INTERNAL CIRCUITRY S2 VID RTN, CLAMP IN 50µA source is active only when VIDIN < 2.7V. Figure 1 VIDEEM1 Ron of the transistor gate is ≈10kΩ. Figure 5 VDD 9V 6µ/2µ 10µ/2µ 50µA VIDEEM1 1 S2 VID RTN CLAMP IN 0042A-11.EPS 10kΩ 125µA 1 1µA VDD 5V GND 0V 0042A-08.EPS 1 VIDEEM2 / 22kHz Ron of the transistor gate is ≈10kΩ. Figure 6 6µ/2µ 10µ/2µ S1 VID OUT, S2 VID OUT Same as above but with no black level adjustment. Figure 3 VIDEEM2/22kHz 1 125µA 60Ω VCC 12V VDD 5V 4 100µ/2µ 2.3mA VID MUX GND 0V 22kHz 0042A-12.EPS S1 VID OUT S2 VID OUT 60µ/2µ 10kΩ 20kΩ 0042A-09.EPS VREF 2.4V 20kΩ GND 0V VID IN Figure 7 VREF 2.4V UNCL DEEM Same as above but with no black level adjustment and slightly different gain. 10kΩ VID IN 85µA GND 0V VCC 12V PK OUT 4 UNCL DEEM Figure 8 10kΩ 25kΩ VDD 9V VREF 2.4V GND 0V Audio 0042A-10.EPS 16.7kΩ Clamp 3.4V 1 1 Peak Detector 5kΩ PK OUT 0042A-14.EPS 2.3mA GND 0V 12/24 1 0.5pF 60Ω IN + 0042A-13.EPS 6.5kΩ Figure 4 STV0042A PIN INTERNAL CIRCUITRY (continued) FC L, FC R Ivar is controlled by the peak det audio level max. ±15µA (1VPP audio). FM IN The otherinput for each channelis internallybiased in the same way via 10kΩ to the 2.4V VREF. Figure 9 Figure 13 10kΩ VDD 9V Left Channel 2.4V FM IN 1 10kΩ 1 1 0042A-15.EPS 50µA Ivar 0042A-19.EPS FC L FC R 1 Right Channel 50µA IREF The optimum value if IREF is 50µA ±2% so an external resistor of 47.5kΩ ±1% is required. VOL OUT R, VOL OUT L Audio output with volume and scart driver with +12dB of gain for up to 2VRMS. The opamp has a push-pull output stage. Figure 14 Figure 10 VOL OUT R VOL OUT L 1 IREF 30kΩ 30kΩ 0042A-16.EPS 4.8V GND 0V Figure 15 205Ω S2 OUT L, S2 OUT R Same as above but with gain fixed at +6dB. Figure 11 Audio 2.4V Bias SCL This is the input to a Schmitt input buffer made with a CMOS amplifier. SCL 0042A-21.EPS 15kΩ 24µ/4µ ESD SDA Input same as above. Output pull down only : relies on external resistor for pull-up. S2 OUT L S2 OUT R 20kΩ Figure 16 SDA S2 RTN L, S2 RTN R 4.8V bias voltage is the same as the bias level on the audio outputs. 600µ/2µ ESD 0042A-22.EPS GND 0V 205Ω 24µ/4µ 0042A-17.EPS 20kΩ GND 0V U75 L, U75 R I1 - I2 = 2 x audio / 18kΩ. eg 1VPP audio : ±55µA. The are internal switches to match the audio level of the different standards. Figure 12 25kΩ Figure 17 4.8V I1 1 U75 L U75 R 0042A-23.EPS 50µA 0042A-18.EPS S2 RTN L S2 RTN R 0042A-20.EPS 2.4V Audio 2.4V Bias I2 13/24 STV0042A PIN INTERNAL CIRCUITRY (continued) XTL VREF The 400µA source is off during stand-by mode. Figure 22 Figure 18 VREF (2.4V) 460Ω 460Ω 2 Vbg 1.2V 3 4 10kΩ 2 400µA 5pF GND 0V 750µA 500µA 750µA 0042A-24.EPS XTL 10kΩ 0042A-28.EPS 3 GND 0V CPUMP L, CPUMP R An offset on the PLL loop filter will cause an offset in the two 1µA currents that will prevent the PLL from drifting-off frequency. Figure 19 SUMOUT Figure 23 V REF 2.4V SUMOUT Audio 49kΩ CPUMP L CPUMP R 49kΩ 50kΩ 100µA 1µA Dig Synth Loop Filter Tracking 0042A-29.EPS 1 100µA PK IN 1µA 0042A-25.EPS Figure 24 VCO Input 100µA VREF 2.4V 1 67kΩ I2 0042A-26.EPS DET L DET R I1 AMPLK L, AMPLK R, AGC L, AGC R I2 and I1 from the amplitude detecting mixer. Figure 21 I2 5µA AGC L AGC R 2 160µA VREF 2.4V 14/24 0042A-27.EPS I1 10kΩ 100µA V 12V Doubled bonded (two bond wires and two pads for one package pin) : - One pad is connected to all of the 12V ESD and video guard rings. - The second pad is connected to power up the video block. V GND Doubled bonded : - One pad is connectedto power-up all of the video mux and I/O. - The second pad is only as a low noise GND for the video input. To VCA AMPLK L AMPLK R To Peak Det PK IN VDD 5V, GND 5V Connected to XTL oscillator and the bulk of the CMOS logic and 5V ESD. 0042A-30.EPS DET L, DET R I2 - I1 = f (phase error). Figure 20 STV0042A PIN INTERNAL CIRCUITRY (continued) A 12V Doubled bonded : - One pad connected to the ESD and guard ring. - The second pad is connected to the main power for all of the audio parts. A GND R Boubled bonded : - One pad connected to the right VCO, dividers, mixers and guard ring. The guard connection is star connected directly to the pad. - The second pad is connected to the bias block, audio noise reduction, volume, mux and ESD. A third bond wire on this pin is connected directly to the die pad (substrate). Figure 25 V 12V Video Pads V GND VDD 5V 205Ω Vpp BIP 10vpl Vmm Digital Pads DZPN1 GND 5V DZPN1 A GND L DZPN1 A 12V Audio Pads Substrate + BIP 12V - 0042A-31.EPS A GND L Doubled bonded : - One pad connected to the left VCO, dividers, mixers and guard ring. the guard connection is star connected directly to the pad. - The second pad is connected to both AGC amps and the deemphasis amplifiers, frequency synthesis and FM deviation selection circuit for both channels. A GND R 15/24 STV0042A I2C PROTOCOL 1) WRITING to the chip S-Start Condition P-Stop Condition CHIP ADDR - 7 bits. 06H W-Write/Read bit is the 8th bit of the chip address. A-ACKNOWLEDGE after receiving 8 bits of data/adress. REG ADDR Address of register to be written to, 8 bits of which bits 3, 4, 5, 6 & 7 are ’X’ or don’t care ie only the first 3 bits are used. 8 bits of data being written to the register. All 8 bits must be written to at the same time. can be repeated, the write process can continue untill terminated with a STOP condition. If the REG ADDR is higher than 07 then IIC PROTOCOL will still be met (ie an A generated). DATA REG ADDR/A/DATA/A Example : S 06 W A 00 A 55 A 01 A 8F A P 2) READING from the chip When reading, there is an auto-incrementfeature. This means any read command always starts by reading Reg 8 and will continue to read the following registers in order after each acknowledge or until there is no acknowledge or a stop. This function is cyclic that is it will read the same set of registers without re-addressing the chip. There are two modes of operation as set by writing to bit 7 of register 0. Read 3 registers in a cyclic fashion or all 5 registers in a cyclic fashion. Note only the last 5 of the 11 registers can be read. Reg0 bit 7 = L ⇒ Start / chip add / R / A / Reg 8 / A/ Reg 9 / A / Reg 0A / A / Reg 8 / A / Reg 9 / A / Reg 0A /... / P / Reg0 bit 7 = H ⇒ Start / chip add / R / A / Reg 8 / A / Reg 9 / A / Reg 0A / A / Reg 7 / A / Reg 6 / A / Reg 8 / A / Reg 9 / A / Reg 0A / A / Reg 7 / A / Reg 6 / ... / P / CONTROL REGISTERS Reg 0 write only Bit (default 00HEX) 0 L Select 5 bits audio volume control 00H = MUTE 1 L Select 5 bits audio volume control 01H = -26.75dB 2 L Select 5 bits audio volume control : : : : : 3 L Select 5 bits audio volume control 1.25dB steps up to 4 L Select 5 bits audio volume control 1FH = +12dB 5 L Not to be used 6 L Audio mux switch K3 - ANRS select (L = no ANRS, H = ANRS) 7 L L = read 3 registers, H = read 5 registers Reg 1 write only Bit (default 00HEX) 0 L Select video gain bits 1 L Select video gain bits 00H = 0dB 2 L Select video gain bits 01H = +0.202dB 3 L Select video gain bits 02H = +0.404dB 4 L Select video gain bits n = + 0.202 dB * n 5 L Select video gain bits 3FH = + 12.73 dB 6 L Selected video invert (H = inverted, L = non inverted) 7 L Video deemphasis 1 / Video deemphasis 2 (L : VID De-em 1) 16/24 STV0042A CONTROL REGISTERS (continued) Reg 2 write only Bit (default F7HEX) 0 H Select video source for scart 1 O/P 1 H Select video source for scart 1 O/P 2 H Select video source for scart 1 O/P 3 L Select 4.000MHz or 8.000MHz clock speed (L = 8MHz) 4 H Select audio source for volume output (Switch K1) 5 H Select audio source for volume output (Switch K1) 6 H Select Left/Right/Stereo for volume output 7 H Select Left/Right/Stereo for volume output Reg 3 write only Bit (default F7HEX) 0 H Select video source for scart 2 O/P 1 H Select video source for scart 2 O/P 2 H Select video source for scart 2 O/P 3 L Video deemphais 2 / 22kHz (H : 22kHz) 4 H Select audio source for Scart 2 output (Switch K5) 5 H Select audio source for Scart 2 output (Switch K5) 6 H Audio deemphasis select (Switch K2) 7 H Audio deemphasis select (Switch K2) Reg 4 write only Bit (default BFHEX) 0 H Not to be used 1 H Not to be used 2 H Not to be used 3 H Stand-by or low power mode (H = low power) 4 H Not to be used 5 H Not to be used 6 L Not to be used 7 H Not to be used Reg 5 write only Bit (default B5HEX) 0 H FM deviation selection -- default value for 50kHz modulation 1 L FM deviation selection 2 H FM deviation selection 3 L FM deviation selection 4 H FM deviation selection 5 H FM deviation selection (L = double the FM deviation) 6 L Not to be used 7 H Not to be used Reg 6 write/read Bit (default 86HEX) 0 L Status of I/O 1 H Select data direction of I/O 1 ( H = output) 2 H Select frequency synthesizer 1 OFF/ON (L = OFF) 3 L Select frequency synthesizer 2 OFF/ON (L = OFF) 4 L Select RF source (L = OFF) to FM det 1 5 L Select RF source (L = OFF) to FM det 2 6 L Select frequency for PLL synthesizer - LSB (bit 0) of 10-bit value 7 H Select frequency for PLL synthesizer - bit 1 of 10-bit value 17/24 STV0042A CONTROL REGISTERS (continued) Reg 7 write/read Bit (default AFHEX) 0 H Select frequency for PLL synthesizer - bit 2 of 10-bit value 1 H Select frequency for PLL synthesizer 2 H Select frequency for PLL synthesizer 3 H Select frequency for PLL synthesizer 4 L Select frequency for PLL synthesizer 5 H Select frequency for PLL synthesizer 6 L Select frequency for PLL synthesizer 7 H Select frequency for PLL synthesizer - bit 9, MSB (10th bit) of 10-bit value Reg 8 Bit 0 1 2 3 4 5 6 7 read only Subcarrier detection (DET 1) (L = No subcarrier) Not used Read frequency of watchdog 1 - LSB (bit 0) of 10-bit value Read frequency of watchdog 1 - bit 1 of 10-bit value Subcarrier detection (DET 2) (L = No subcarrier) Not used Read frequency of watchdog 2 - bit 0 of 10-bit value Read frequency of watchdog 2 - bit 1 of 10-bit value Reg 9 read only Bit (default AFHEX) 0 Read frequency of watchdog 1 - bit 2 of 10-bit value 1 Read frequency of watchdog 1 2 Read frequency of watchdog 1 3 Read frequency of watchdog 1 4 Read frequency of watchdog 1 5 Read frequency of watchdog 1 6 Read frequency of watchdog 1 7 Read frequency of watchdog 1 - bit 9, MSB (10th bit) of 10-bit Reg 0A read only Bit 0 Read frequency of watchdog 2 - bit 2 of 10-bit value 1 Read frequency of watchdog 2 2 Read frequency of watchdog 2 3 Read frequency of watchdog 2 4 Read frequency of watchdog 2 5 Read frequency of watchdog 2 6 Read frequency of watchdog 2 7 Read frequency of watchdog 2 - bit 9, MSB (10th bit) of 10-bit 18/24 STV0042A CONTROL REGISTERS (continued) Video Mux Truth Tables Register 2 <0:2> ⇒ Scart 1 video output control Register 3 <0:2> ⇒ Scart 2 video output control The truth table for the three scart outputs are the same. Register 2/3 Bit<2> 0 0 0 0 1 1 1 1 Bit<1> 0 0 1 1 0 0 1 1 Video Output Bit<0> 0 1 0 1 0 1 0 1 Baseband video De-emphasized video Normal video Not to be used Scart 2 return Not to be used Nothing selected High Z or low power (default) Audio Mux Truth Tables Register 2 Bit <5> 0 1 0 1 Bit <4> 0 0 1 1 Switch K1/Audio Source Selection for Volume Output A C B - Volume Output Audio deemphasis (K2 switch O/P) Scart 2 return Not to be used High Z or low power (default) Register 3 Bit <7> 0 1 0 1 Bit <6> 0 0 1 1 Switch K2/Audio Deemphasis A C B B Audio Deemphasis No deemphasis Not to be used 50µs 75µs (default) A B A B ANRS I/O Select Noise reduction OFF Noise reduction ON (default) Not to be used Not to be used C A B - Aux Audio Output PLL output Not to be used Audio deemphasis (K2 switch O/P) High Z or low power state (default) Register 0 Bit <6> 0 1 X X Bit <5> X X 0 1 Switch K3 & K4 Register 3 Bit <5> 0 1 0 1 Bit <4> 0 0 1 1 Register 2 Bit <7> 0 1 1 Bit <6> 0 0 1 Switch K5/Audio Source Selection for Scart 2 Left / Right / Stereo on Volume Output Mono left / channel 1 Mono right / channel 2 Stereo left & right (default) 19/24 STV0042A CONTROL REGISTERS (continued) Register 5 : FM Deviation Selection 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Selected Nominal Carrier Modulation Bit 5 = 0 Do not use Do not use Do not use Cal. set. (2V) 592kHz 534kHz 484kHz 436kHz 396kHz 358kHz 322kHz 292kHz 266kHz 240kHz 218kHz 196kHz 179kHz 161kHz 146kHz 122kHz 120kHz 109kHz 98kHz 89kHz 78kHz 71kHz 65kHz 58kHz 53kHz 48.6kHz 43.8kHz 39.6kHz Bit 5 = 1 cal : do not use = 0.3373V offset on VCO cal : do not use = 0.3053V offset on VCO cal : do not use = 0.2763V offset on VCO calibration setting (1V offset on VCO) 296kHz modulation 267kHz modulation 242kHz 218kHz 198kHz 179kHz 161kHz 146kHz 133kHz 120kHz 109kHz 98.3kHz 89.7kHz 80.9kHz 73.1kHz 66.0kHz 60.0kHz 54.4kHz = default power up state 49.1kHz 44.3kHz 39.8kHz 35.9kHz 32.4kHz 29.1kHz 26.7kHz 24.3kHz 21.9kHz 19.7kHz Example : Default power up state 54.4kHz ⇒ ±54.4kHz. Register 1 Bit <7> Register 3 Bit <3> 0 0 1 1 0 1 0 1 Video Deemphasis/22kHz Deemphasis Deemphasis Deemphasis Deemphasis 1 (default) 1 + 22kHz (Pin 13) 2 2 FM DEMODULATION SOFTWARE ROUTINE With the STV0042A circuit, for each channel, three steps are required to acheive a FM demodulation : - 1st step :To set the demodulation parameters : • FM deviation selection, • Subcarrier frequency selection. - 2nd step : To implement a waiting loop to check the actual VCO frequency. - 3rd step :To close the demodulationphase locked loop (PLL). Refering to the FM demodulation block diagram (page 12), the frequency synthesis block is common to both channels (left and right) ; consequently 20/24 two completesequenceshave to be done one after the other when demodulating stereo pairs. Detailed Description Conventions : - R = Stands for Register - B = Stands for Bit Example : R05 B2 = Register 05, Bit 2 For clarity, the explanations are based on the following e xa mp le : st ere o p air 7 .0 2MHz /L 7.20MHz/R, deviation ±50kHz max. STV0042A FM DEMODULATION SOFTWARE ROUTINE (continued) 1st Step (Left): SettingtheDemodulationParameters A. The FM deviation is selected by loading R5 with the appropriate value. (see R5 truth table). NB : Very wide deviations (up to ±592kHz) can be accomodated when R5 B5 is low. Corresponding bandwidth can be calculated as follows : Bw ≈ 2 (FM deviation + audio bandwidth) Bw ≈ 2 (value given in table + audio bandwidth) In the example : R5Bits 7 6 5 4 3 2 1 0 X X 1 1 0 1 1 0 B. The subcarrier frequency is selected by launching afrequencysynthesis(theVCOisdriventothewanted frequency).This operationrequires two actions : - To connect the VCO to the frequency synthesis loop. Refering to the FM block diagram (page 12): • SW4 closed ⇒ R6 B2 = H • SW3 to bias ⇒ R6 B4 = L • SW2 to bias ⇒ R6 B3 = L • SW1 opened ⇒ R6 B5 = L - To load R7 and R6 B6 B7 with the value corresponding to the left channel frequency. This 10 bits value is calculated as follows : Subcarrier frequency = coded value x 10kHz (10kHz is the minimum step of the frequency synthesis function) . Considering that the tunning range is comprised between 5 to 10MHz, the coded value is a number between 500 and 1000 (210 = 1024) then 10 bits are required. Example : 7.02MHz = 702 x 10kHz 702 ⇒ 1010 1111 10 ⇒ AF + 10 R7 is loaded with AF and R6 B6 : L, R6 B7 : H. The Table 1 gives the setting for the most common subcarrier frequencies. 2nd Step (Left) : VCO FrequencyChecking (VCO) This secondstepis actually a waiting loopin which the actualrunning frequencyof the VCO is measured. To exit of this loop is allowed when : Subcarrier Frequency - 10kHz ≤ Measured Frequency ≤ Subcarrier Frequency+10kHz(± 10kHz is the maximum dispersion of the frequencysynthesisfunction). Inpractice,R8 B2 B3 and R9 are readand compared to the value loaded in R6 B6 B7 and R7 ±1 bit. Note : The duration of this step depends on how large is frequency difference between the start frequency and the targeted frequency. Typically : - the rate of change of the VCO frequencyis about 3.75MHz/s (Cpump = 10µF) - In addition to this settling time, 100ms must be added to take into account the sampling period of the watchdog. 3rd Step (Left) The FM demodulationcan be startedbyconnecting the VCO to the phase locked loop (PLL). In practice : - SW3 closed ⇒ R6 B4 = H - SW4 opened ⇒ R6 B2 = L After this sequence of 3 steps for left channel, a similar sequence is needed for the right channel. Note : In thesequenceforthe right,thereisnoneedtoagain select the FM deviation(once is enoughfor the pair). General Remark Before to enable the demodulated signal to the audio output, it is recommandedto keep the muting and to check whether a subcarrier is present at the wanted frequency. Such an informationis available in R8 B0 and R8 B4 which can be read. Two different strategies can be adoptedwhen enabling the output : - Eitherbothleftandrightdemodulatedsignalsare simultaneouslyauthorizedwhenbothchannelare ready. - Or while the right channel sequence is running, the already ready left signal is sent to the left and right outputsandtherealstereosoundL/Risoutputwhen both channels are ready. This second option gives sound a few hundredsof ms before the first one. Table 1 : Frequency Synthesis Register Setting for the Most Common Subcarrier Frequencies Subcarrier Freq. (MHz) 5.58 5.76 5.8 5.94 6.2 6.3 6.4 6.48 6.5 6.6 6.65 6.8 6.85 7.02 7.20 7.25 7.38 7.56 7.74 7.85 7.92 8.2 8.65 Register 7 (Hex) 8B 90 91 94 9B 9D A0 A2 A2 A5 A6 AA AB AF B4 B5 B8 BD C1 C4 C6 CD D8 Register 6 Bit 7 Bit 6 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 0 0 0 1 21/24 22/24 R48 75Ω JP2 JP1 C34 100nF + C35 220µF 16V VDD 23 VCCA 24 19 C11 8.2nF C7 2.2µF 20 R16 1kΩ VCCV C30 100nF 22 21 3 C32 100nF + C31 220µF 16V C65 JP6 47pF C56 100nF L4 47µH 2 C23 8.2nF 1 + C33 220µF 16V L1 22µH C66 47pF J13 L2 22µH 12V 1 GND 1 J14 J11 5V 1 GND 1 J12 J10 5V 1 SDA 2 SCL 3 GND 4 C24 27pF R18 1kΩ C25 100pF R17 470Ω J8 I/O 1 CLOCK 1 INPUT J9 J7 0042A-32.EPS TUNER INPUT R15 1kΩ 5MHz LPF made by TDK / Japan SEL5618 : TDK FILTER SEL5618 A second video deemphasis network R13, R12, C15, R14, C14 is shown for 525 lines systems. Optionally : 26 17 R32 82kΩ C37 22pF C38 22pF 4MHz or 8MHz Crystal C29 22pF VDD 25 18 C6 2.2µF C8 2.2µF 3 4 6 28 15 C41 10µF 16V R33 180kΩ + 27 9 10 12 13 14 15 16 R14 5.6kΩ 11 29 14 VCCV 12 17 18 20 11 19 21 10 J2 C39 2.7nF 30 R34 27kΩ R36 560kΩ 31 C42 100nF C43 100nF 32 + 33 STV0042A 13 C12 100pF C15 10µF C14 150pF 16V + R9 5.1kΩ 8 + C13 10µF 16V R11 1.5kΩ R10 10kΩ R12 1.8kΩ 16 7 C5 2.2µF 5 R13 10kΩ 2 C26 10µF 16V 1 VCR/DECODERSCART C40 470µF 16V VCCA 34 9 R6 75Ω R39 27kΩ C45 100nF 35 8 37 C46 2.7nF 6 5 6 C2 2.2µF 4 7 8 1 9 11 12 13 R3 470Ω 10 14 15 16 + 38 5 R40 180kΩ 40 C47 22pF R51 560kΩ C50 10µF 16V 39 4 JP11 C3 2.2µF R41 82kΩ C48 22pF 42 JP7 C58 100nF 41 2 JP9 C66 100nF R60 1.2MΩ JP5 JP8 JP10 17 C60 1.5nF R53 43kΩ R59 1.2MΩ C65 100nF 20 21 J1 R56 10kΩ Q4 BC557 R58 43kΩ C64 1.5nF 19 VCCA 18 R2 68Ω Q1 BC547 3 Q2 BC547 3 2 VCCV 1 VCCV R50 47.5kΩ 1% R4 470Ω R5 68Ω R37 560kΩ 36 7 C4 220nF TV SCART C62 8.2nF C63 220nF R57 24kΩ V L R C61 1.5nF R55 1.5kΩ R54 3.3kΩ J4 J5 J6 STV0042A TYPICAL APPLICATION (with 2 video deemphasis network) 0042A-33.EPS TUNER INPUT 22kHz TONE R48 75Ω J14 C66 47pF + C31 220µF 16V 220µF 16V + C35 2 JP2 JP1 C23 8.2nF 1 C34 100nF C32 100nF C30 100nF 23 20 VCCA 24 19 C11 8.2nF C7 2.2µF VDD R16 1kΩ VCCV 22 21 3 TDK FILTER SEL5618 C65 JP6 47pF C56 100nF L4 47µH + C33 220µF 16V L1 22µH J13 L2 22µH 12V 1 GND 1 J12 J11 5V 1 GND 1 J10 5V 1 SDA 2 SCL 3 GND 4 C24 27pF R18 1kΩ C25 100pF R17 470Ω J8 I/O 1 CLOCK 1 INPUT J9 J7 R15 1kΩ 5MHz LPF made by TDK / Japan 26 17 R32 82kΩ C37 22pF C38 22pF 4MHz or 8MHz Crystal C29 22pF VDD 25 18 C6 2.2µF C8 2.2µF C5 2.2µF 5 28 15 C41 10µF 16V R33 180kΩ + 27 16 7 9 29 14 13 14 30 13 11 10 32 8.2nF C43 100nF C42 100nF 31 C45 100nF VCCA 34 9 R6 75Ω + C40 470µF 16V 33 STV0042A C12 100pF 12 16 18 20 15 17 19 21 J2 R9 5.1kΩ 11 VCCV + C13 10µF 16V R11 1.5kΩ R10 10kΩ 3 C26 10µF 16V 1 R36 560k Ω 4.7kΩ SEL5618 : 27kΩ 12 36kΩ 10 2.7nF 8 4.7kΩ 6 27kΩ 4 35 8 36 7 C4 220nF 2.7nF 2 4.7kΩ R37 560kΩ 36kΩ 4.7kΩ VCR/DECODER SCART 75/J17 VCCV + 38 5 1 R40 180kΩ R51 560kΩ 39 4 JP11 C3 2.2µF Q2 BC547 8.2nF C50 10µF 16V 37 6 R4 470Ω R5 68Ω R50 A second video deemphasis network R13, R12, C15, R14, C14 is shown for 525 lines systems. 4.7kΩ 47.5kΩ - 1% Optionally : 5 6 C47 22pF 7 1 9 42 8 R41 82kΩ C48 22pF JP7 C58 100nF 41 40 C2 2.2µF 4 2 3 3 2 12 VCCV R53 43kΩ C60 1.5nF C66 100nF R59 1.2MΩ C65 100nF R2 68Ω VCCA Q4 BC557 R56 10kΩ R58 43kΩ C64 1.5nF 16 18 20 15 17 19 21 J1 R60 1.2MΩ JP5 JP8 JP10 14 Q1 BC547 13 R3 470Ω 11 JP9 10 TV SCART C62 8.2nF C63 220nF R57 24k Ω V L R C61 1.5nF R55 1.5kΩ R54 3.3kΩ J4 J5 J6 STV0042A TYPICAL APPLICATION (with 22kHz tone and three audio de-emphasis 50µs, 75µs, J17) 23/24 STV0042A PACKAGE MECHANICAL DATA 42 PINS - PLASTIC SHRINK DIP E A2 A L A1 E1 B B1 e e1 e2 D c E 42 22 .015 0,38 e3 21 e2 SDIP42 Dimensions A A1 A2 B B1 c D E E1 e e1 e2 e3 L Min. 0.51 3.05 0.38 0.89 0.23 36.58 15.24 12.70 2.54 Millimeters Typ. 3.81 0.46 1.02 0.25 36.83 13.72 1.778 15.24 3.30 Max. 5.08 4.57 0.56 1.14 0.38 37.08 16.00 14.48 18.54 1.52 3.56 Min. 0.020 0.120 0.0149 0.035 0.0090 1.440 0.60 0.50 0.10 Inches Typ. 0.150 0.0181 0.040 0.0098 1.450 0.540 0.070 0.60 0.130 Max. 0.200 0.180 0.0220 0.045 0.0150 1.460 0.629 0.570 0.730 0.060 0.140 Information furni shed is believed to be accurate and reliable. However, SGS-THOMSON Micr oelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise und erany patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This pu blication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1997 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I 2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips 2 2 I C Patent. Rights to use these components in a I C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 24/24 SDIP42.TBL 1 PMSDIP42.EPS Gage Plane