STV5348 STV5348/H - STV5348/T MONOCHIP TELETEXT AND VPS DECODER WITH 8 INTEGRATED PAGES FEATURES SUMMARY ■ COMPLETE TELETEXT AND VPS DECODER INCLUDING AN 8 PAGE MEMORY ON A SINGLE CHIP ■ UPWARD SOFTWARE COMPATIBLE WITH PREVIOUS ST’s MULTICHIP SOLUTIONS (SAA5231, SDA5243, STV5345) ■ PERFORM PDC SYSTEM A (VPS) AND PDC SYSTEM B (8/30/2) DATA STORAGE SEPARATELY ■ DEDICATED "ERROR FREE" OUTPUT FOR VALID PDC DATA ■ INDICATION OF LINE 23 FOR EXTERNAL USE ■ SINGLE +5V SUPPLY VOLTAGE ■ SINGLE 13.875MHz CRYSTAL ■ REDUCED SET OF EXTERNAL COMPONENTS, NO EXTERNAL ADJUSTMENT ■ OPTIMIZED NUMBER OF DIGITAL SIGNALS REDUCING EMC RADIATION ■ HIGH DENSITY CMOS TECHNOLOGY ■ DIGITAL DATA SLICER AND DISPLAY CLOCK PHASE LOCK LOOP ■ 28 PIN DIP & SO PACKAGE DESCRIPTION The STV5348 decoder is a computer-controlled teletext device including an 8 page internal memory. Data slicing and capturing extracts the teletext information embedded in the composite video signal. Control is accomplished via a two wire serial I2C bus ®. Chip address is 22h. Internal ROM provides a character set suitable to display text using up to seven national languages. Hardware and software features allow selectable master/slave synchronization configurations. The STV5348 also supports facilities for reception and display of current level protocol data. Figure 1. Package PDIP28 (Plastic Package) SO28 (Plastic Package) Figure 2. Pin Connections CVBS 1 28 CBLK MA/SL 2 27 TEST VDDA 3 26 VSSA POL 4 25 VSSO STTV/LFB 5 24 XTI FFB 6 23 XTO VSSD 7 22 VDDD R 8 21 VCR/TV G 9 20 RESERVED B 10 19 DV RGB REF 11 18 L23 BLAN 12 17 SDA COR 13 16 SCL ODD/EVEN 14 15 Y REV. 2 May 2004 1/30 STV5348 - STV5348/H - STV5348/T Table 1. Pin Description Pin No Symbol Function Description Figure 1 CVBS Input Composite Video Signal Input through Coupling Capacitor 12 2 MA/SL Input Master/Slave Selection Mode 14 3 VDDA Analog Supply 4 POL Input 5 STTV/LFB Output / Input 6 FFB Input 7 VSSD Ground Digital Ground 8 R Output Video Red Signal 16 9 G Output Video Green Signal 16 10 B Output Video Blue Signal 16 11 RGBREF Supply DC Voltage to define RGB High Level 16 12 BLAN Output Fast Blanking Output TTL Level 18 13 COR Output Open Drain Contrast Reduction Output 18 14 ODD/EVEN Output 25Hz Output Field synchronized for non-interlaced display 18 15 Y Output Open Drain Foreground Information Output 18 16 SCL Input Serial Clock Input 19 17 SDA Input/ Output Serial Data Input/Output 20 18 L23 Output Line 23 Identification 18 19 DV Output VPS Data Valid 18 20 RESERVED Test To be connected to VSSD through a resistor 18 21 VCR/TV Input PLL Time Constant Selection 18 22 VDDD Digital Supply +5V 23 XTO Crystal Output Oscillator Output 13.875MHz 17 24 XTI Crystal Input Oscillator Input 13.875MHz 17 25 VSSO Ground Oscillator Ground - 26 VSSA Ground Analog Ground - 27 TEST Test 28 CBLK Input / Output 2/30 +5V - STTV / LFB / FFB Polarity Selection 15 Composite Sync Output, Line Flyback Input 18 Field Flyback Input 15 - - Grounded to VSSA 14 To connect Black Level Storage Capacitor 13 STV5348 - STV5348/H - STV5348/T Figure 3. Block Diagram STTV/LFB FFB MA/SL POL L23 CLAMPING SYNCHRONIZING DATA EXTRACTION 18 Data Clock XTO 23 Data OSCILLATOR FREQUENCY SYNTHETIZER TIME BASE SCL 16 SDA 17 19 DV 20 TEST 8 PAGES MEMORY Data VSSO 25 3 DATA DECODING DATA PROCESSING VCR/TV 21 XTI 24 22 Address CBLK 28 4 CTRL 1 2 2 I C BUS INTERFACE Address CVBS 6 VDDA 12 BLAN CTRL 5 V DDD 13 COR DISPLAY INTERFACE 8 RED 9 GREEN 10 BLUE 15 Y STV5348 7 V SSD 26 27 VSSA TEST 11 14 RGB REF ODD/EVEN Table 2. Absolute Maximum Ratings Symbol VDD Parameter Positive Supply Voltage on VDDD and VDDA Value Unit –0.3, 6.0 V VI Input Voltage (any input) –0.3, VDD + 0.5 V VO Output Voltage (any output) –0.3, VDD + 0.5 V ∆VDD Difference between VDDD, VDDA 0.25 V Toper Operating Ambient Temperature 0, +70 °C Tstg Storage Temperature –40, +150 °C 3/30 STV5348 - STV5348/H - STV5348/T ELECTRICAL CHARACTERISTICS (VDD = 5V, VSS = 0V, TA = 25°C) Table 3. Supplies Symbol Parameter Min. Typ. Max. Unit 4.75 5.0 5.25 V VDD Supply Voltage IDDD VDDD Pin Supply Current 30 mA IDDA VDDA Pin Supply Current 5 mA Table 4. Inputs Symbol Parameter Min. Typ. Max. Unit 4.75 5.0 5.25 V CBLK IBLKO Source Current (VCBLK = 2V, VCVBS = 0V) IBLKI Sink Current (VCBLK = 2V, VCVBS = 1V)) 30 mA CVBSI Video Input Amplitude (peak to peak) 1 V CVBSC Input Capacitance CVBS 10 200 ns Clamping Level at Synchro Pulse 0 mV ICLPH High Level Clamp Current (CVBS = VCLAMP + 1V) 5 µA ICLPL Low Level Clamp Current (CVBS = VCLAMP – 0.3V) –400 µA tSYNC VCLAMP Delay from CVBS to TCS Output from STTV Pin pF MA/SL, POL, LFB, FFB, VCR/TV VIL Input Voltage Low Level –0.3 +0.8 V VIH Input Voltage High Level 2 VDD V IIL Input Leakage Current (VI = 0 to VDDD) –10 +10 µA CI Input Capacitance 10 pF SCL, SDA VIL Input Voltage Low Level –0.3 +1.5 V VIH Input Voltage High Level 3 VDD V IIL Input Leakage Current (VI = 0 to VDD) –10 +10 µA 100 kHz fSCL Clock Frequency (SCL) tR, tF Input Rise and Fall Time (10 to 90%) 2 µs Input Capacitance 10 pF VDD+0.3V V 50 mA CI RGB REF 4/30 VI Input Voltage II Input Current VDD–0.5V VDD STV5348 - STV5348/H - STV5348/T Table 5. Outputs Symbol Parameter Min. Typ. Max. Unit 0.4 V RGB REF V Load Capacitance 50 pF Rise and Fall Time (10 to 90%) 20 ns 0.4 V RGB VOL Output Low Voltage (IOL = 2mA) VOH Output High Voltage (IOH = –2mA, RGB REF = VDD/2) CL tR, tF RGB REF – 0.5 BLAN VOL Output Low Voltage (IOL = 2mA) VOH Output High Voltage (IOH = –0.2mA) CL tR, tF 0 VDD – 0.5 V Load Capacitance 50 pF Rise and Fall Time (10 to 90%) 20 ns 0 0.5 V VDD – 0.8 VDD V Load Capacitance 50 pF Rise and Fall Time (10 to 90%) 20 ns 0.5 V ODD/EVEN, STTV, L23, DV VOL Output Low Voltage (IOL = 2mA) VOH Output High Voltage (IOH = –0.2mA) CL tR, tF COR AND COR AND Y (with Pull up to VDDD) VOL Output Low Voltage (IOL = 2mA) CL Load Capacitance 25 V tF Fall Time (RL = 1.2kΩ, VDDD – 0.5V to 1.5V) 50 ns –10 +10 µs 0 0.5 V IOLL Output Leakage Current 0 SDA VOL Output Low Voltage (IOL = 3mA) tF Fall Time (3.0 to 1.0V) 200 ns CL Load Capacitance 400 pF Max. Unit Table 6. Crystal Oscillator Symbol Parameter fXTAL Crystal Frequency RBIAS Internal Bias Resistance CI Input Capacitance Min. Typ. 13.875 0.4 1 MHz 3 MΩ 7 pF 5/30 STV5348 - STV5348/H - STV5348/T Table 7. Timing Symbol Parameter Min. Typ. Max. Unit SERIAL BUS (referred to VIH = 3V, VIL = 1.5V) tLOW tHIGH Clock: ● Low Period ● High Period 4 4 µs µs tSU, DAT Data Set-up Time 250 ns tHD, DAT Data Hold Time 170 ns tSU, STO Stop Set-up Time from Clock High 4 µs tBUF Start Set-up Time following a Stop 4 µs tHD, STA Start Hold Time 4 µs tSU, STA Start Set-up Time following Clock Low to High Transition 4 µs Figure 4. Display Output Timing LSP (TCS) 40µs 0 4.66 64 R.G.B.Y (1) 0 16.67 56.67 (a) LINE RATE all timings in µss lines 42 to 291 inclusive (and 355 to 604 inclusive interlaced) R.G.B.Y (1) 0 41 291 312 (b) FIELD RATE 6/30 line numbers STV5348 - STV5348/H - STV5348/T Figure 5. Serial Bus Timing SDA t BUF t LOW tF SCL t HD,STA tR t HD,DAT t HIGH t SU,DAT SDA t SU,STA t SU,STO VIH = 3V , VIL = 1.5V Figure 6. Master Synchronization Mode - Hardware Configuration Output signal on STTV Pin : 1 Synchro Extractor Line PLL POL grounded Line PLL VCS when R1D2 = 0 TCS when R1D2 = 1 MA/SL 2 VCS R1D2 = "0" +5V TCS R1D2 = "1" Bit R1D2 4 POL to VDD I2C Control VCS when R1D2 = 0 TCS when R1D2 = 1 POL STTV 7/30 STV5348 - STV5348/H - STV5348/T Figure 7. Master Synchronization Mode - Delivered Composite Synchronization Signal VCS, TCS (interlaced) 621 (308) 622 (309) 623 (310) 624 (311) 309 310 311 312 308 309 625 (312) 1 2 3 4 5 6 316 (3) 317 (4) 318 (5) 319 (6) 3 4 5 6 VCS, TCS (interlaced) 313 314 (1) 312 1 315 (2) TCS (non-interlaced) 310 311 2 The number positions indicate the end of lines. Internal signals : - VCS composite synchro from CVBS signal, - TCS Teletext composite synchro. Figure 8. Slave Synchronization Mode MA/SL 2 +5V LFB 5 SCS POL +5V 4 6 FFB POL grounded, Inputs Signals : POL to VDD, Inputs Signals : are LFB line flyback synchro on Pin 5 FFB field flyback synchro on Pin 6 are LFB line flyback synchro on Pin 5 FFB field flyback synchro on Pin 6 or SCS synchro composite signal on Pins 5 and 6 or SCS synchro composite signal on Pins 5 and 6 Figure 9. Data Valid Timing (DV) Field 0 DV for VPS Data Line 16 8/30 Field 1 Field 0 STV5348 - STV5348/H - STV5348/T FUNCTIONAL DESCRIPTION Displayable Page Memory Map The organization of a page memory is shown in Figure 10. The display area consists of 25 rows of 40 characters per row. The organization is as follows: – Row zero contains the page header: – The first seven characters (0 - 6) are used for messages regarding the operational status. – The eighth character is an alphanumeric control character either "white" or "green" defining the "search" status of the page. When it is "white" the operational state is normal and the header appears white; when it is "green" the operational state corresponds to the "search mode" and the header appears green. – The following twenty-four characters give the header of the requested page when the system is in search mode. – The last eight characters display the time of day. – Row number twenty-four is used by the microprocessor for the display of information, or used to display X/24 colored key data according to R0D7 bit. – Row twenty-five comprises ten bytes of control data concerning the received page (see Table 9) and fourteen free bytes which can be used by the microprocessor. Figure 10. Page Memory Organization 7 Status Characters Fixed characters Alphanumerics white for normal, green on search 7 24 characters from page header rolling on page search 8 scrolling time characters ROW 24 8 0 1 1 2 3 4 5 6 7 8 9 10 11 MAIN PAGE DISPLAY AREA 12 13 14 15 16 17 18 19 20 21 22 23 row free for status (R0D7 = 0) or packet X/24 (R0D7 = 1) 10 14 10 bytes for received page information 14 bytes free for use by µC 24 25 9/30 STV5348 - STV5348/H - STV5348/T Table 8. Ghost Row Storage Organization Row Address of Stored Data Designation Code 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 11 1011 12 1100 13 1101 14 1110 15 0010 16 0000 17 0001 18 0100 19 0101 Row (Packet) Number X / 26 Function Enhanced display facilities Page related data stored in chapter corresponding to level 1 data, i.e. For 0 goes in 4 " 1 " " 5 " 2 " " 6 " 3 " " 7 X / 28 Conditional access Editorial X / 27 Linked pages Composition 20 X / 24 Page extension stored here if R0D7 = 0 21 X / 25 Page extension Color definition 22 0000 X / 28 23 XXXX 8 / 30 (1) 24 0001 X/28 25 (2) Note: 1. Packet 8/30 storage: Broadcasting service data packet Character set designation Not used 8/30/0,1: 8/30/2,3: 8/30/4 to 15: 2. See Table 10 for VPS data storage. 10/30 (1) chapter 4, row23 chapter 5, row23 chapter 6, row23 STV5348 - STV5348/H - STV5348/T Table 9. Row 25 Received Page Control Data Format D0 PU0 PT0 MU0 MT0 HU0 HT0 C7 C11 MAG0 0 D1 PU1 PT1 MU1 MT1 HU1 HT1 C8 C12 MAG1 0 D2 PU2 PT2 MU2 MT2 HU2 C5 C9 C13 MAG2 0 D3 PU3 PT3 MU3 C4 HU3 C6 C10 C14 0 0 D4 HAM HAM HAM HAM HAM HAM HAM HAM FOUND 0 D5 0 0 0 0 0 0 0 0 0 PBLF D6 0 0 0 0 0 0 0 0 0 0 D7 0 0 0 0 0 0 0 0 0 0 COLUMN 0 1 2 3 4 5 6 7 8 9 Page number : - MAG = magazine, PU = page units, PT = page tens. Page sub-code : - MU = minutes units, MT = minutes tens, HU = hours units, HT = hours tens. PBLF = page being looked for, FOUND = low for page found, HAM = hamming error in byte, C4-14 = control bits. VPS DATA (see Table 10) VPS data are stored in row 25 chapter 5 as shown in Table 10 when VPS enable bit (D4 of R8 register) is set. VPS data bits are decoded and stored in a received area with biphase error bit. 8/30/2 data are stored as received (without hamming decoding) in Row 23 chapter 5 according to Table 10. 8/30 packet and VPS data decoding is the responsibility of the control software. The decoder simply stores transmitted data. I2C Bus Register Map (see Table 11) Registers R0 to R10 are write only whilst R11A is a read/write and R11B is read only. The automatic succession on a byte by byte basis is indicated by the arrows in Table 10. In the normal operating mode TB should be set to logic level 0. After power-up the contents of the registers are as follows: all bits in registers R0 to R11A are cleared to zero with the exception of bits D0 and D1 in registers R5 and R6 which are set to logical one. After power-up all the memory bytes are preset to hexadecimal value 20H (space) with the exception of the byte corresponding to row 0 of column 7 of chapter 0 which is set to the value corresponding to "alpha white" hexadecimal value 07H. Table 10. PDC Data Storage Column 0 1 2 3 8/30/2 (Row 23) D VPS (Row 25) Column 5 6 7 8 9 20 21 22 23 24 10 11 12 13 14 15 16 17 18 19 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25 Received Page Information 8/30/2 (Row 23) VPS (Row 25) 4 Initial Page 25 26 27 B11 28 29 30 31 B12 32 33 B13 34 35 B14 36 37 B15 38 39 Status Display B4 B5 11/30 STV5348 - STV5348/H - STV5348/T Table 11. Register Specification D7 D6 D5 D4 D3 D2 D1 D0 X24 FREE 0 POSITION RUNNING PLL DISABLE ROLLING HEADER (1) EVEN OFF (1) SEL 11B (1) 7 + P/ 8 BIT ACQ. ON/OFF GHOST ROW ENABLE DEW/ FULL FIELD TCS ON T1 T0 (1) BANK SELECT A2 ACQ. CCT A1 ACQ. CCT A0 TB START COLUMN SC2 START COLUMN SC1 START COLUMN SC0 R2 Page request address (1) (1) (1) PRD4 PRD3 PRD2 PRD1 PRD0 R3 Page request data (1) (1) (1) (1) (1) A2 A1 A0 R4 Display chapter BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PON OUT PON IN R5 Display control (normal) BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PON OUT PON IN R6 Display control (newsflash / subtitle) STATUS ROW BTM/TOP CURSOR ON/OFF CONCEAL/ TOP/ REVEAL BOTTOM SINGLE/ DOUBLE HEIGHT BOX ON 24 BOX ON 1-23 BOX ON 0 R7 Display mode (1) (1) (1) VPS ENABLE CLEAR MEM. A2 A1 A0 R8 Active chapter (1) (1) (1) R4 R3 R2 R1 R0 R9 Active row (1) (1) C5 C4 C3 C2 C1 C0 R10 Active column D7 (R/W) D6 (R/W) D5 (R/W) D4 (R/W) D3 (R/W) D2 (R/W) D1 (R/W) D0 (R/W) R11A Active data 60Hz 0 0 0 0 0 DATA QUAL VCS QUAL R11B Status Note (1). Reserved register bits: must be set to 0. 12/30 R0 Mode 0 R1 Mode 1 STV5348 - STV5348/H - STV5348/T Table 12. Registers Functions Register Function Bit(s) SEL 11B (D0) EVEN OFF (D2) R0 Address 00H R11 addressing and pin functions control DISABLE ROLLING HEADER FREE RUNNING PLL (D6) X/24 POSITION (D7) T1 (D1) 0 0 1 1 T0 (D0) 0 1 0 1 TCS ON (D2) R1 Address 01H Operating mode controls DEW / FULLFIELD (D3) Control of ODD/EVEN pin: EVEN signal output (D2 = 0) or grounded (D2 = 1) D4 = 1, Disable rolling header D4 = 0, Normal operation D6 = 0, PLL locks on line frequency D6 = 1, to force free running mode D7 = 0, packet X/24 stored to chapter 4 to 7/row 20 D7 = 1, packet X/24 stored to chapter 0 to 3/row 24 Character display line control: 312.5/312.5 line MIX - mode with interlace 312/313 line TEXT - mode without interlace 312/312 line Terminal mode without interlace External synchronization. SCS mode (scan field synchro) Master Mode (MA/SL Pin 2 = 0) case POL Pin 4 = 0 D2 = 0, Pin 5 = VCS D2 = 1, Pin 5 = TCS Slave Mode (MA/SL Pin 2 = VDD) No effect Selection of field flyback mode or full channel mode (D3 = 1) for recovering of Teletext data. Selection of ghost row mode (D4 = 1) ACQUISITION ON / OFF (D5) Control of acquisition operation (D5 = 0 enables acquisition) SC0, SC1, SC2 (D0, D1, D2) Addressing information for a page request Selection of register 11B (D0 = 1) or 11A (D0 = 0) GHOST ROW ENABLE (D4) 7 bits + parity or 8 bits without parity (D6) R2 Address 02H Description TB (D3) A0, A1 (D4, D5) Selection of received data format either 7 bits with parity (D6 = 0) or 8 bits without parity (D6 = 1). Address the first column of the on chip page request RAM to be written. Test bit equal to "0" in the normal working mode. Address a group of four consecutive pages currently used for data acquisition. A2 (D6) Address of one of the two groups of four pages for acquisition in normal mode. Written data in the page request RAM, starting with the columns addressed by SC0, SC1, SC2. R3 Address 03H Data relative to the requested page (see Table 10) PRD0 - PRD4 (D0 - D4) R4 Address 04H Selection of one of eight pages to display A0, A1, A2 (D0, D1, D2) Chapter selection. 13/30 STV5348 - STV5348/H - STV5348/T Register R5 Address 05H Function Display control for normal operation Bit(s) PON (D0, D1) Picture on (IN: D0, OUT: D1) TEXT (D2, D3) Text on (IN: D2, OUT: D3) COR (D4, D5) Contrast reduction on (IN: D4, OUT: D5) BKGND (D6, D7) Background color on (IN: D6, OUT: D7) IN / OUT R6 Address 06H Display control for news-flash subtitle generation See R5 BOX ON 0, 1-23,24 (D0, D1, D2) R7 Address 07H Display mode Enable inside/outside the box See R5 The "boxing" function is enabled on row 0,1-23 and 24 by D0, D1 and D2 set to one. TOP / BOTTOM X0 = Normal Single / Double Height 01 = double height Rows 0 to 11 11 = double height Rows 12 to 23 (D4/D3) Conceal / Reveal (D5) Conceal Reveal Function Cursor ON/OFF (D6) Cursor position given by row/column value of R9/R10 STATUS ROW BTM / TOP (D7) The row 24 is displayed before the "Main text Area" (lines 0-23) or after (D7 = 0). VPS Enable (D4) D4 = 1 Enable VPS acquisition and DV signal output. Clear Memory (D3) R8 Description Memory access Chapter Address (D2, D1, D0) D4 = 1 Clear memory. Chapter selected with A2A1A0 (D2, D1, D0) R4. Chapter selection R9 to R11A Active row address (R9), active column address (R10). Address Data contained in R11A read (written) from (to) memory by microprocessor via I2C. 08H to 0BH (1) R11B Address 0BH (1) Status VCS QUAL (D0) Good VCS quality signal detected (D0 = 1). Bad VCS quality signal detected (D0 = 0). DATA QUAL (D1) Good TELETEXT signal (D1 = 1). Bad TELETEXT signal (D1 = 0). 50/60Hz (D7) If D1 = 0 frame frequency is 50Hz (only valid with good VCS) Note: 1. Reading of R11A or R11B is determined by register 0, bit D0. However, write operation is always performed on R11A register. 14/30 STV5348 - STV5348/H - STV5348/T Table 13. Register R3 START COLUMN 0 PRD4 PRD3 PRD2 PRD1 PRD0 Do care magazine HOLD MAG2 MAG1 MAG0 1 Do care page tens PT3 PT2 PT1 PT0 2 Do care page units PU3 PU2 PU1 PU0 3 Do care hours tens X X HT1 HT0 4 Do care hours units HU3 HU2 HU1 HU0 5 Do care minutes tens X MT2 MT1 MT0 6 Do care minutes units MU3 MU2 MU1 MU0 The abbreviations have the same significance as in Table 9 with the exception of the "DO CARE" entries. It is only when this bit is "1" that the corresponding digit is taken into consideration on page request. For example, a page defined as "normal" or one defined as "timed" may be selected. 2 If "HOLD" is low the page is held. The addressing of successive bytes via the I C is automatic. Character Sets The complete character set with 8-bit decoding is given in Table 12. Characters in columns 0 and 1 are normally displayed as blanks. Black dots represent the character shape whereas white dots represent the background. Each character can be identified by a pair of corresponding row and column integers: for example the character "3" may be indicated by 3/3. A rectangle may be represented as follows: The characters 8/6, 8/7, 9/5, 9/7 are used as special characters, always in conjunction with 8/5. The 13 national characters are placed in columns with bit 8 = 0. 15/30 * ** 16/30 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Case using C12 C13 C14 = 001 (German Set) These control characters are reserved for compatibility with other data codes. These control characters are presumed before each row begins 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 B I T S b4 b3 b2 b1 b8 b7 b6 b5 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 r o w graphics magenta graphics cyan graphics white alphanumerics magenta alphanumerics cyan ** alphanumerics white SI SO double height normal height start box end box steady * * ** ** ** graphics blue alphanumerics blue * release graphics hold graphics ** ** new background ** black background ESC separated graphics ** continuous graphics conceal display graphics yellow alphanumerics yellow flash graphics green alphanumerics green 1 graphics re d 0 alphanumerics red 0 graphics black 0 0 alphanumerics black 0 1 0 0 column 0 2 1 0 or 1 0 0 0 1 2a 0 0 3 1 0 or 1 0 1 0 1 3a 0 1 0 1 4 0 0 0 1 5 0 1 6 0 1 1 6a 0 7 0 1 1 7a 1 1 0 8 0 0 1 0 9 0 1 1 0 12 1 0 1 0 13 1 1 1 1 14 1 0 1 1 15 1 1 STV5348 - STV5348/H - STV5348/T Table 14. STV5348 Complete Character Set (with 8 bit codes) - West European Languages * ** Case using C12 C13 C14 = 001 (Rumanian Set) These control characters are reserved for compatibility with other data codes. These control characters are presumed before each row begins 8-??.EPS 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 b 4 b3 b2 b1 B I T S graphics blue graphics magenta graphics cyan graphics white alphanumerics blue alphanumerics magenta alphanumerics cyan ** alphanumerics white 4 5 flash steady end box start box normal height double height SO SI 9 10 11 12 13 14 15 7 * * ** ** ** graphics yellow alphanumerics yellow 3 * release graphics hold graphics ** ** new background ** black background ESC separated graphics ** continuous graphics conceal display graphics green alphanumerics green 2 6 graphics red alphanumerics red 1 1 0 graphics black 0 alphanumerics black 0 0 0 0 1 0 2 column 0 8 r o w b8 b7 b6 b5 2 0 or 1 0 1 0 0 1 2a 0 0 3 0 or 1 0 1 0 0 1 3a 0 0 0 1 4 0 0 0 1 5 0 1 6 0 1 1 6a 0 7 0 1 1 7a 1 1 0 8 0 0 1 0 9 0 1 1 0 12 1 0 1 0 13 1 1 1 1 14 1 0 1 1 15 1 1 STV5348 - STV5348/H - STV5348/T Table 15. STV5348/H Complete Character Set (with 8 bit codes) - East European Languages 17/30 * ** 18/30 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Case using C12 C13 C14 = 001 (German Set) These control characters are reserved for compatibility with other data codes. These control characters are presumed before each row begins 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 B I T S b4 b3 b 2 b 1 b8 b7 b6 b5 graphics yellow graphics blue graphics magenta graphics cyan graphics white alphanumerics yellow alphanumerics blue alphanumerics magenta alphanumerics cyan ** alphanumerics white 3 4 5 flash steady end box start box normal height double height SO SI 9 10 11 12 13 14 15 7 * * ** ** ** graphics green alphanumerics green 2 1 * ** release graphics hold graphics ** ** new background ** black background ESC separated graphics continuous graphics conceal display graphics red alphanumerics red 1 6 graphics black alphanumerics black 0 0 0 0 1 0 0 2 0 8 r o w column 0 2 0 or 1 0 1 0 0 1 2a 0 0 3 0 or 1 0 1 0 0 1 3a 0 0 0 1 4 0 0 0 1 5 0 1 6 0 1 1 6a 0 7 0 1 1 7a 1 1 0 8 0 0 1 0 9 0 1 1 0 12 1 0 1 0 13 1 1 1 1 14 1 0 1 1 15 1 1 STV5348 - STV5348/H - STV5348/T Table 16. STV5348/T Complete Character Set (with 8 bit codes) - Turkish European Languages STV5348 - STV5348/H - STV5348/T The basic set of the 96 characters is shown in Table 17. The location of the 13 national characters are shown in Table 17 whilst full national character sets are depicted in Table 18, 19 and 20. Table 17. Basic character set. 2/0 3/0 4/0 2/1 3/1 2/2 National National 5/0 6/0 4/1 5/1 6/1 7/1 3/2 4/2 5/2 6/2 7/2 3/3 4/3 5/3 6/3 7/3 3/4 4/4 5/4 6/4 7/4 2/5 3/5 4/5 5/5 6/5 7/5 2/6 3/6 4/6 5/6 6/6 7/6 2/7 3/7 4/7 5/7 6/7 7/7 2/8 3/8 4/8 5/8 6/8 7/8 2/9 3/9 4/9 5/9 6/9 7/9 2/10 3/10 4/10 5/10 6/10 7/10 2/11 3/11 4/11 5/11 6/11 7/11 2/12 3/12 4/12 5/12 6/12 7/12 2/13 3/13 4/13 5/13 6/13 7/13 2/14 3/14 4/14 5/14 6/14 7/14 2/15 3/15 4/15 5/15 6/15 7/15 2/3 2/4 National Character National Character Character National Character National Character National Character National Character National Character Character 7/0 National Character National Character National Character National Character 19/30 STV5348 - STV5348/H - STV5348/T 1 1 SPANISH 0 0 1 FRENCH 0 1 0 ITALIAN 1 0 0 SWEDISH 1 1 0 GERMAN 0 0 0 0 ENGLISH LANGUAGE C12 C13 PHCB (1) C14 2/3 2/4 4/0 5/11 5/12 5/13 5/14 5/15 CHARACTER POSITION (COLUMN/ROW) 6/0 7/11 7/12 7/13 7/14 Table 18. STV5348 Character Set - West European Languages Note: 1. Where PHCB are the Page Header Control bits. Other Combinations default to English. Only the above characters change with the PHCB. All others characters in the basic set are shown in Table 14. 20/30 STV5348 - STV5348/H - STV5348/T Table 20. STV5348/T Character Set Turkish European Languages 6/0 5/12 5/13 5/14 5/15 CHARACTER POSITION (COLUMN/ROW) Note: 1. Where PHCB are the Page Header Control bits. Other Combinations default to German. Only the above characters change with the PHCB. All others characters in the basic set are shown in Table 16. 0 0 1 1 FRENCH SPANISH 1 1 0 ITALIAN 0 0 1 1 TURKISH 1 1 0 0 GERMAN 0 0 0 ENGLISH C14 C13 PHCB (1) LANGUAGE C12 1 1 1 RUMANIAM 0 1 1 CZECHOSLOVAK 1 0 1 SERBO-CROAT 0 1 0 SWEDISH 1 0 0 GERMAN 0 0 0 POLISH LANGUAGE C12 C13 PHCB (1) C14 2/3 2/3 2/4 2/4 4/0 4/0 5/11 5/11 5/12 5/13 5/14 5/15 CHARACTER POSITION (COLUMN/ROW) 6/0 7/11 7/11 7/12 7/12 7/13 7/13 7/14 7/14 Table 19. STV5348/H Character Set East European Languages Note: 1. Where PHCB are the Page Header Control bits. Other Combinations default to Turkish. Only the above characters change with the PHCB. All others characters in the basic set are shown in Table 16. 21/30 STV5348 - STV5348/H - STV5348/T Figure 11. Character Format Alphanumerics and Graphics 'space' character 2/0 Contiguous graphics character 7/6 Alphanumerics character 2/13 Separated graphics character 7/6 Alphanumerics or blast-through alphanumerics character 4/8 Separated graphics character 7/15 = 22/30 Background Color Alphanumerics character 7/15 Contiguous graphics character 7/15 = Display Color STV5348 - STV5348/H - STV5348/T I/O PIN ELECTRICAL SCHEMATICS Figure 15. Input D Figure 12. Analog 1 (CVBS) VDDA VDDD CVBS 450Ω Pins 4, 6 POL, FFB 250Ω 1 VSSD VSSA Figure 16. PRGB Figure 13. Analog 2 (CBLK) VDDA VDDD RGB REF CBLK 11 250Ω 28 450Ω Pins 8, 9, 10 R, G, B VSSD VSSA Figure 17. Figure 14. Input A VDDD Pins 2, 27 MA/SL, TEST 450Ω XTI 450Ω 750kΩ VDDA 24 XTO 450Ω 23 VSSD VSSA 23/30 STV5348 - STV5348/H - STV5348/T Figure 18. INOUT Figure 20. PSDA VDDD VDDD Pins 5, 12, 13, 14, 15, 18, 19, 20, 21 STTV/LFB, BLAN, COR, ODD/EVEN, Y, L23, DV, RESERVED, VCR/TV 450Ω Figure 19. PSCL VDDD 450Ω 16 VSSD 24/30 450Ω 17 VSSD SCL SDA VSSD STV5348 - STV5348/H - STV5348/T Figure 21. Application Diagram 0.1µF 0.1µF +5V 1 CVBS CBLK 28 2 MA/SL TEST 27 3 VDDA VSSA 26 4 POL VSSO 25 5 STTV/LFB 6 FFB 7 VSSD SL MA 1µF +5V +5V C1* 8 9 +5V R G XTI 24 S T V 5 3 4 8 13.875MHz C2* XTO 23 +5V VDDD 22 TV VCR/TV 21 +5V VCR 1µF 10nF 20 47kΩ** 10 B 19 11 RGB REF 18 0.1µF 12 BLAN SDA 17 13 COR SCL 16 14 ODD/EVEN Y 15 * Value according to used crystal, C1 = C2 = 2 * CLOAD Example : C1 = C2 = 56pF, CLOAD = 30pF. ** Depending on application. Please refer to our video application lab. Remark: all the power supply inputs must be switched on at the same time (connected to the same source). 25/30 STV5348 - STV5348/H - STV5348/T PART NUMBERING Table 21. Order Codes 26/30 Part Number Package Temperature Range STV5438 PDIP28 West European 0 to 70 °C STV5438/H PDIP28 East European 0 to 70 °C STV5348/T PDIP28 Turkish and European 0 to 70 °C STV5348D SO28 West European 0 to 70 °C STV5348D/T SO28 Turkish and European 0 to 70 °C STV5348 - STV5348/H - STV5348/T PACKAGE MECHANICAL Table 22. PDIP28 - 28 Pins - Plastic Dip - Mechanical Data millimeters inches Symbol Min Typ Max Min Typ a1 0.63 0.025 b 0.45 0.018 b1 0.23 b2 0.31 1.27 D E 0.009 0.012 0.050 37.4 15.2 16.68 1.470 0.598 0.657 e 2.54 0.100 e3 33.02 1.300 F Max 14.1 0.555 I 4.445 0.175 L 3.3 0.130 Figure 22. PDIP28 - 28 Pins - Plastic Dip - Package Dimensions Note: Drawing is not to scale 27/30 STV5348 - STV5348/H - STV5348/T Table 23. SO28 - 28 Pins, Plastic Micropackage - Mechanical Data millimeters inches Symbol Min Typ A Max Min 2.65 Max 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 0.020 c1 45° (Typ) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 S 8° (Max) Figure 23. SO28 - 28 Pins, Plastic Micropackage - Package Dimensions Note: Drawing is not to scale 28/30 Typ STV5348 - STV5348/H - STV5348/T REVISION HISTORY Table 24. Revision History Date Revision Description of Changes September-1998 1 First Issue 28-May-2004 2 Stylesheet update. No content change. 29/30 STV5348 - STV5348/H - STV5348/T Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 30/30