STV7610A PLASMA DISPLAY PANEL DATA DRIVER FEATURE ■ ■ ■ ■ ■ ■ ■ ■ ■ 96 OUTPUTS PLASMA DISPLAY DRIVER 100 V ABSOLUTE MAXIMUM SUPPLY 5 V SUPPLY FOR LOGIC 60/50 mA SOURCE/SINK OUTPUT MOS 60/50 mA SOURCE/SINK OUTPUT DIODE 6 bit CASCADABLE DATA BUS (20 MHz) BLANK, POLARITY CONTROL BCD TECHNOLOGY PACKAGING TQFP144 OR DICE DIE ORDER CODE: STV7610A/WAF(1) (1): Unsawn tested wafer DESCRIPTION The STV7610A is a BCD data driver for Plasma Display Panel (PDP). Using a 6-bit wide cascadable data bus, it addresses 96 high current & high voltage outputs. By serially connecting several STV7610A, any horizontal pixel definition can be performed. The 20 MHz shift clock gives an equivalent 120 MHz shift register. The STV7610A is supplied with a separated 90 V power output supply and a 5 V logic supply. All command inputs are CMOS compatible. TQFP144 (20 x 20 x 1.4 mm) (Thin Plastic Quad Flat Pack) ORDER CODE: STV7610A Version 4.2 June 2000 This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice. 1/17 1 STV7610A PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 PIN LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PAD COORDINATES (IN MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 NOTE 1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 NOTE 4 THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 NOTE 4 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 NOTE 5 AC TIMINGS REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 NOTE 5 AC TIMINGS CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 FIGURE 2. INPUT/OUTPUT SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 FIGURE 6. PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/16 2 STV7610A PIN CONNECTIONS OUT34 OUT35 OUT36 OUT37 OUT38 OUT39 OUT40 OUT41 OUT42 OUT43 OUT44 OUT45 OUT46 OUT47 OUT48 OUT49 OUT50 OUT51 OUT52 OUT53 OUT54 OUT55 OUT56 OUT57 OUT58 OUT59 OUT60 OUT61 OUT62 OUT63 (DIE Pinout) VSSP VSSP VPP VPP VPP VPP OUT64 OUT33 OUT65 OUT32 OUT66 OUT31 OUT67 OUT30 OUT68 OUT29 OUT69 OUT28 STV7610A Bare Die OUT70 OUT71 OUT72 OUT73 OUT27 OUT26 OUT25 OUT24 OUT74 OUT23 OUT75 OUT22 Y OUT76 OUT21 OUT77 OUT20 OUT78 OUT19 OUT79 OUT18 OUT80 OUT17 (0,0) OUT81 OUT16 X VSSP VPP A6 A5 A4 A3 A2 A1 STB OUT1 CLK OUT2 OUT96 VSSSUB OUT3 OUT95 VSSLOG OUT4 OUT94 VCC OUT5 OUT93 F/R OUT6 OUT92 POL OUT7 OUT91 BLK OUT8 OUT90 B1 OUT9 OUT89 B2 OUT10 OUT88 B3 OUT11 OUT87 B4 OUT12 OUT86 B5 OUT13 OUT85 B6 OUT14 OUT84 VPP OUT15 OUT83 VSSP OUT82 3/17 3 STV7610A PIN CONNECTIONS VSSP NC NC OUT63 OUT62 OUT61 OUT60 OUT59 OUT58 OUT57 OUT56 OUT55 OUT54 OUT53 OUT52 OUT51 OUT50 OUT49 OUT48 OUT47 OUT46 OUT45 OUT44 OUT43 OUT42 OUT41 OUT40 OUT39 OUT38 OUT37 OUT36 OUT35 OUT34 NC NC VSSP 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VPP 1 108 VP P VPP 2 107 VP P NC 3 106 NC OUT64 4 105 OUT33 OUT65 5 104 OUT32 OUT66 6 103 OUT31 OUT67 7 102 OUT30 OUT68 8 101 OUT29 OUT69 9 100 OUT28 OUT70 10 99 OUT27 OUT71 11 98 OUT26 OUT72 12 97 OUT25 OUT73 13 96 OUT24 OUT74 14 95 OUT23 OUT75 15 94 OUT22 OUT76 16 93 OUT21 OUT77 17 92 OUT20 OUT78 18 91 OUT19 OUT79 19 90 OUT18 OUT80 20 89 OUT17 OUT81 21 88 OUT16 OUT82 22 87 OUT15 OUT83 23 86 OUT14 OUT84 24 85 OUT13 OUT85 25 84 OUT12 OUT86 26 83 OUT11 OUT87 27 82 OUT10 OUT88 28 81 OUT9 OUT89 29 80 OUT8 OUT90 30 79 OUT7 OUT91 31 78 OUT6 OUT92 32 77 OUT5 OUT93 33 76 OUT4 OUT94 34 75 OUT3 OUT95 35 74 OUT2 OUT96 36 73 OUT1 4/17 3 144 (TQFP Pinout) 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 NC NC NC VSSP NC VPP NC B6 B5 B4 B3 B2 B1 BLK POL F/R VCC VSSLOG VSSSUB CLK STB NC A1 A2 A3 A4 A5 A6 NC VPP NC VSSP NC NC NC NC STV7610A TQFP144 STV7610A PIN LIST (TQFP144) Pin N° Symbol Type Description 3-37-38-39-41-43-48-65-67-6970-71-72-106-110-111-142-143 - 1-2-42-66-107-108 VPP Supply High Voltage Supply of Power Outputs 53 V CC Ground 5V Logic Supply 40-68-109-144 V SSP Ground Ground of Power Outputs 54 V SSLOG Ground Logic Ground 55 VSSSUB Output Substrate Ground 73 to 105 OUT 1 to OUT 33 Output Power Output 112 to 141 OUT 34 to OUT 63 Input Power Output 4 to 36 OUT 64 to OUT 96 Input Power Output 50 BLK Input Blanking Input 51 PO L Input Polarity Input 52 FOR/ REV Input Selection of Shift Direction 56 CLK Input Clock of data Shift Register 57 STB Input Latch of data to Outputs 59 to 64 A1 to A6 Input/Output Forward Shift Register Input 44 to 49 B6 to B1 Input/Output Forward Shift Register Output NC PIN LIST (Power outputs) Output N° Pin N° Output N° Pin N° Output N° Pin N° Output N° Pin N° 1 73 25 97 49 127 73 13 2 74 26 98 50 128 74 14 3 75 27 99 51 129 75 15 4 76 28 100 52 130 76 16 5 77 29 101 53 131 77 17 6 78 30 102 54 132 78 18 7 79 31 103 55 133 79 19 8 80 32 104 56 134 80 20 9 81 33 105 57 135 81 21 10 82 34 112 58 136 82 22 11 83 35 113 59 137 83 23 12 84 36 114 60 138 84 24 13 85 37 115 61 139 85 25 14 86 38 116 62 140 86 26 15 87 39 117 63 141 87 27 5/17 3 STV7610A Output N° Pin N° Output N° Pin N° Output N° Pin N° Output N° Pin N° 16 88 40 118 64 4 88 28 17 89 41 119 65 5 89 29 18 90 42 120 66 6 90 30 19 91 43 121 67 7 91 31 20 92 44 122 68 8 92 32 21 93 45 123 69 9 93 33 22 94 46 124 70 10 94 34 23 95 47 125 71 11 95 35 24 96 48 126 72 12 96 36 PAD COORDINATES (in ΜM) Pad positions from the middle of the top side Center Name X Y X Y OUT 48 74.0 3034.0 80.0 90.0 OUT 47 210.0 3034.0 80.0 90.0 OUT 46 346.0 3034.0 80.0 90.0 OUT 45 482.0 3034.0 80.0 90.0 OUT 44 618.0 3034.0 80.0 90.0 OUT 43 754.0 3034.0 80.0 90.0 OUT 42 890.0 3034.0 80.0 90.0 OUT 41 1026.0 3034.0 80.0 90.0 OUT 40 1162.0 3034.0 80.0 90.0 OUT 39 1298.0 3034.0 80.0 90.0 OUT 38 1434.0 3034.0 80.0 90.0 OUT 37 1570.0 3034.0 80.0 90.0 OUT 36 1706.0 3034.0 80.0 90.0 OUT 35 1842.0 3034.0 80.0 90.0 OUT 34 1993.0 3034.0 80.0 90.0 Pad positions along the right side Center Name 3 Size X Y X Y VSSP 2116.0 2795.0 90.0 80.0 VPP 2029.8 2496.5 90.0 90.0 VPP 2041.5 1843.0 90.0 80.0 6/17 Center Size Name Size X Y X Y OUT 33 2117.0 1580.0 90.0 80.0 OUT 32 2117.0 1444.0 90.0 80.0 OUT 31 2117.0 1308.0 90.0 80.0 OUT 30 2117.0 1172.0 90.0 80.0 OUT 29 2117.0 1036.0 90.0 80.0 OUT 28 2117.0 900.0 90.0 80.0 OUT 27 2117.0 764.0 90.0 80.0 OUT 26 2117.0 628.0 90.0 80.0 OUT 25 2117.0 492.0 90.0 80.0 OUT 24 2117.0 356.0 90.0 80.0 OUT 23 2117.0 220.0 90.0 80.0 OUT 22 2117.0 84.0 90.0 80.0 OUT 21 2117.0 2117.0 90.0 80.0 OUT 20 2117.0 2117.0 90.0 80.0 OUT 19 2117.0 -324.0 90.0 80.0 OUT 18 2117.0 -460.0 90.0 80.0 OUT 17 2117.0 -596.0 90.0 80.0 OUT 16 2117.0 -732.0 90.0 80.0 OUT 15 2117.0 -868.0 90.0 80.0 OUT 14 2117.0 -1004.0 90.0 80.0 OUT 13 2117.0 -1140.0 90.0 80.0 OUT 12 2117.0 -1276.0 90.0 80.0 OUT 11 2117.0 -1412.0 90.0 80.0 STV7610A Center Name Center Size Name Size X Y X Y A3 1049.0 -3034.0 80.0 90.0 80.0 A2 899.0 -3034.0 80.0 90.0 90.0 80.0 A1 749.0 -3034.0 80.0 90.0 -1956.0 90.0 80.0 STB 449.0 -3034.0 80.0 90.0 2117.0 -2092.0 90.0 80.0 CLK 299.0 -3034.0 80.0 90.0 OUT 5 2117.0 -2228.0 90.0 80.0 GNDsub 156.5 -3034.0 80.0 90.0 OUT 4 2117.0 -2364.0 90.0 80.0 GND 3.0 -3034.0 80.0 90.0 OUT 3 2117.0 -2500.0 90.0 80.0 VCC -158.0 -3034.0 80.0 90.0 OUT 2 2117.0 -2636.0 90.0 80.0 F/R -299.0 -3034.0 80.0 90.0 OUT 1 2117.0 -2832.0 90.0 80.0 POL -449.0 -3034.0 80.0 90.0 BLK -599.0 -3034.0 80.0 90.0 B1 -749.0 -3034.0 80.0 90.0 B2 -899.0 -3034.0 80.0 90.0 B3 -1049.0 -3034.0 80.0 90.0 B4 -1199.0 -3034.0 80.0 90.0 B5 -1349.0 -3034.0 80.0 90.0 B6 -1499.0 -3034.0 80.0 90.0 VPP -1698.0 -3034.0 80.0 90.0 VSSP -1904.0 -3034.0 80.0 90.0 X Y X Y OUT 10 2117.0 -1548.0 90.0 80.0 OUT 9 2117.0 -1684.0 90.0 OUT 8 2117.0 -1820.0 OUT 7 2117.0 OUT 6 Pad positions along the bottom side Center Size Name X Y X Y VSSP 1904.0 -3034.0 80.0 90.0 VPP 1698.0 -3034.0 80.0 90.0 A6 1499.0 -3034.0 80.0 90.0 A5 1349.0 -3034.0 80.0 90.0 A4 1199.0 -3034.0 80.0 90.0 7/17 3 STV7610A Pad Positions along the left side Name Size Size X Y X Y OUT 69 -2117.0 900.0 90.0 80.0 OUT 68 -2117.0 1036.0 90.0 80.0 OUT 67 -2117.0 1172.0 90.0 80.0 OUT 66 -2117.0 1308.0 90.0 80.0 OUT 65 -2117.0 1444.0 90.0 80.0 OUT 64 -2117.0 1580.0 90.0 80.0 80.0 VPP -2041.5 1843.0 90.0 80.0 90.0 80.0 VPP -2029.8 2496.5 90.0 80.0 -1820.0 90.0 80.0 VSSP 2116.0 2795.5 90.0 80.0 -2117.0 -1684.0 90.0 80.0 OUT 87 -2117.0 -1548.0 90.0 80.0 OUT 86 -2117.0 -1412.0 90.0 80.0 OUT 85 -2117.0 -1276.0 90.0 80.0 OUT 84 -2117.0 -1140.0 90.0 80.0 OUT 83 -2117.0 -1004.0 90.0 OUT 82 -2117.0 -868.0 OUT 81 -2117.0 OUT 80 Name X Y X Y OUT 96 -2117.0 -2832.0 90.0 80.0 OUT 95 -2117.0 -2636.0 90.0 80.0 OUT 94 -2117.0 -2500.0 90.0 80.0 OUT 93 -2117.0 -2364.0 90.0 80.0 OUT 92 -2117.0 -2228.0 90.0 80.0 OUT 91 -2117.0 -2092.0 90.0 OUT 90 -2117.0 -1956.0 OUT 89 -2117.0 OUT 88 Pad Positions along the top side Center Name Size X Y X Y OUT 63 -1980.0 3034.0 80.0 90.0 80.0 OUT 62 -1830.0 3034.0 80.0 90.0 90.0 80.0 OUT 61 -1694.0 3034.0 80.0 90.0 -732.0 90.0 80.0 OUT 60 -1558.0 3034.0 80.0 90.0 -2117.0 -596.0 90.0 80.0 OUT 59 -1422.0 3034.0 80.0 90.0 OUT 79 -2117.0 -460.0 90.0 80.0 OUT 58 -1286.0 3034.0 80.0 90.0 OUT 78 -2117.0 -324.0 90.0 80.0 OUT 57 -1150.0 3034.0 80.0 90.0 OUT 77 -2117.0 -188.0 90.0 80.0 OUT 56 -1014.0 3034.0 80.0 90.0 OUT 76 -2117.0 -52.0 90.0 80.0 OUT 55 -878.0 3034.0 80.0 90.0 OUT 75 -2117.0 84.0 90.0 80.0 OUT 54 -742.0 3034.0 80.0 90.0 OUT 74 -2117.0 220.0 90.0 80.0 OUT 53 -606.0 3034.0 80.0 90.0 OUT 73 -2117.0 356.0 90.0 80.0 OUT 52 -470.0 3034.0 80.0 90.0 OUT 72 -2117.0 492.0 90.0 80.0 OUT 51 -334.0 3034.0 80.0 90.0 OUT 71 -2117.0 628.0 90.0 80.0 OUT 50 -198.0 3034.0 80.0 90.0 OUT 70 -2117.0 764.0 90.0 80.0 OUT 49 -62.0 3034.0 80.0 90.0 8/17 3 Center Center STV7610A BLOCK DIAGRAM CLK FOR/REV 56 52 VCC 16-BIT SHIFT REGISTER A1 59 P1 49 B1 P91 16-BIT SHIFT REGISTER A2 60 P2 48 B2 P92 16-BIT SHIFT REGISTER A3 61 P3 47 B3 P93 16-BIT SHIFT REGISTER A4 62 P4 46 B4 P94 16-BIT SHIFT REGISTER A5 63 P5 P95 16-BIT SHIFT REGISTER A6 64 P6 P1 44 B6 P96 P6 P95 P96 54 VSSLOG Q95Q96 55 VSSSUB LATCH STB 57 45 B5 Q1 Q2 VCC POL 50 53 VCC VCC VSSP Pins 40-68-109-144 LOGIC BLK 51 VPP Pins 1-2-42-66-107-108 73 36 OUT1 OUT96 STV7610A 9/17 3 STV7610A CIRCUIT DESCRIPTION The STV7610A contains all the logic and the power circuits necessary to drive the columns of a Plasma Display Panel (P. D. P.). The binary value of each pixel of the displayed line is loaded into the shift register. Data are input in a 6-bit wide data bus to A1 - A6 input (case of forward shift mode). Data are shifted at each low to high transition of the CLK shift clock. After 16 shifts the first data are available on B1 - B6 outputs. These B1 - B6 outputs can be used to cascade several drivers to perform any horizontal resolution. The forward/ reverse (FOR/ REV ) input is used to select the direction of the shift register, A1 - A6 and B1 - B6 data bus input/output status is set according to the selected direction. FOR/ REV = H, A is an input and B is an output. VSSSUB and VSSLOG must be connected as close as possible to the logical reference ground of the application. Serial inputs, CLK, STB inputs are Smith trigger inputs. If not used in the application, Blanking ( BLK ), Polarity (POL are internaly pulled to level ”H”. The maximum frequency of the shift clock is 20 MHz. This leads to an equivalent 120 MHz serial shift register. On low level of STB, data is transferred from shift register to the latch stage. Data will not be refreshed as long as STB is kept high. Blanking input ( BLK ) forces the power outputs to low level when pulled low. All the power outputs are set at high level when the Polarity command ( POL) is pulled low and the Blanking ( BLK ) input is at high level. Power Output Truth Table 10/17 3 Shift Register Truth Table Input Shift Register Function Input/Outp ut FOR/ REV CLK A B Output Q H Rise IN OUT Forward shift H H or L IN OUT Steady L Rise OUT IN Reverse shift L H or L OUT IN Steady Qn STB BL K PO L Driver Output X X L X L Output low X X H L H Output high X H H H Qn Data latched L L H H L Data copied H L H H H Data copied Comments Note 1 Qn+1 = A1, Qn + 2 = A2, Qn + 3 = A3, Qn + 4 = A4, Qn + 5 = A5, Qn + 6 = A6, n = [0,6,12,18,...,90] STV7610A ABSOLUTE MAXIMUM RATINGS Symbol Parameter VCC Logic Supply Range (Pin 53) OUTi Output Pins (4 to 36, 73 to 105, 112 to 141) VIN Value Unit -0.3, +7 V -0.3, +100 V Logic Input Voltage (Pins 50, 51, 52, 56, 57, 59 to 64) -0.3, +VCC +0.3 V -0.3, +VCC + 0.3 V V OUT Logic Output Voltage (Pin 44 to 49) IPOUT Driver Output Current ( Note 2) ( Note 4) -60/ +50 mA IDOUT Diode Output Current ( Note 3) ( Note 4) -50/ +60 mA +150 °C Tj Junction Temperature Toper Operating Temperature -20, +85 °C Tstg Storage Temperature -50, +150 °C Note 2 Through one power output (all power outputs). Note 3 Through one power output for all power outputs (see Test Diagram) with Junction temperature lower or equal than Tjmax. Note 4 These parameters are measured during ST’s internal qualification which includes temperature characterisation on standard batches and on corners batches of the process. These parameters are not tested on the parts. THERMAL DATA Symbol R th(j-a) Parameter Junction-ambient Thermal Resistance Typ. Value Unit 41 °C/W 11/17 3 STV7610A ELECTRICAL CHARACTERISTICS (VCC = 5 V, VPP = 90 V, VSSP = 0 V, VSSLOG = 0 V, VSSSUB = 0 V, Tamb = 25°C, fCLK = 20 MHz, unless otherwise specified) Symbol Parameter Test Conditio ns Min. Typ. Max. Unit 4.5 5 5.5 V - - 100 µA - 26 - mA SUPPLY VCC Logic Supply Voltage ICCH Logic Supply Current (all inputs high) ICCL Logic Dynamic Supply Current VPP Power Output Supply Voltage 15 - 90 V IPPH Power Output Supply Current (steady outputs) - - 100 µA fCLK = 20 MHz OUTPUT (VPP = 15 V to 90 V) OUT 1- OUT 96 VPOUTH Power Output Voltage Drop (High Level) (versus VPP) IPOUTH = - 30 mA IPOUTH = - 45mA - 4.0 4.5 6.0 6.5 V V VPOUTL Power Output Voltage Drop (Low Level) IPOUTL = + 30 mA - 1.6 4 V VDOUTH Output Diode Voltage (High Level) IDOUTH = +45 mA ( Note 5) - 1.05 4 V VDOUTL Output Diode Low Level IDOUTL = - 30mA ( Note 5) - -0.95 -4 V A1-A6, B1-B6 VOH Logic Output (High Level) IOH = -1 mA 4 4.2 - V VOL Logic Output (Low Level) IOL = +1 mA - 0.12 0.4 V INPUT CLK, FOR/ REV , STB, PO L , BLK , A1-A6, B1-B6 VIH Input Voltage (High Level) 0.8 VCC - - V VIL Input Voltage (Low Level) - - 0.2VCC V IIH High Level Input Current VIH = VCC - - 10 µA I IL Low Level Input Current CLK, A1-A6, B1-B6, STB, FOR/ REV , BLK , PO L VIL = 0 V - - -10 -40 µA µA Note 5 See test diagram page 14. 12/17 3 STV7610A AC TIMINGS REQUIREMENTS (VCC = 4.5 V to 5.5 V, Tamb = -20 to +85°C, input signals max leading edge & trailing edge (tR, tF) = 10 ns) Symbol Parameter Min. Typ. Max. Unit tWHCLK Duration of clock (CLK) pulse at high level 15 - - ns tWLCLK Duration of clock (CLK) pulse at low level 15 - - ns tSDAT Set-up Time of data input before clock (low to high) transition 10 - - ns tHDAT Hold Time of data input after clock (low to high) transition 10 - - ns tSFR Forward/ reverse (FOR/ REV ) Set-up Time before clock (low to high) transition 100 tDSTB Minimum Delay to latch ( ST B ) after clock (low to high) transition 10 - - ns tSSTB Minimum Delay to latch ( ST B ) before clock (low to high) transition 10 - - ns 20 - - ns tSTB Latch ( ST B ) Low Level Pulse Duration tBLK Blanking ( BLK ) Pulse Duration 500 - - ns tPOL Polarity ( PO L ) Pulse Duration 500 - - ns AC TIMINGS CHARACTERISTICS (VCC = 5 V, VPP = 90 V, VSPP = 0 V, VSSLOG = 0 V, VSSSUB = 0 V, Tamb = 25°C) (VIL(Max.) = 0.2 Vcc, VIH(Min.) = 0.8 VCC , VOH = 4.0V, V OL = 0.4 V, unless otherwise specified) Symbol Parameter tCLK Data clock Period tRDAT Min. Typ. Max. Unit 50 - - ns Logical Data Output Rise Time (CL=10pF) - 12 20 ns tFDAT Logical Data Output Fall Time (CL=10pF) - 11 20 ns tPHL1 tPLH1 Delay of logic data output (high to low transition) after clock (CLK) transition Delay of logic data output (low to high transition) after clock (CLK) transition - 30 30 50 50 ns ns tPHL2 tPLH2 Delay of power output change (high to low transition) after clock (CLK) transition Delay of power output change (low to high transition) after clock (CLK) transition - 135 80 180 180 ns ns tPHL3 tPLH3 Delay of power output change (high to low transition) after Latch (STB) transition Delay of power output change (low to high transition) after Latch (STB) transition - 115 70 165 165 ns ns tPHL4 - 100 160 ns tPLH4 Delay of power output change (high to low transition) to Blank or Polarity ( BLK , PO L ) transition Delay of power output change (low to high transition) to Blank or Polarity ( BLK , PO L ) transition - 55 160 ns tROUT Power Output Rise Time ( Note 6) - 50 150 ns tFOUT Power Output Fall Time ( Note 6) - 80 200 ns Note 6 One output among 96, loading capacitor CL = 50pF, other outputs at low level. 13/17 3 STV7610A Figure 1. : AC Characteristics Waveform tCLK tWHCLK tWLCLK “1” 50% CLK 50% 50% “0” tHDAT tSDAT “1” 50% 50% A INPUT “0” tFDAT tPHL1 “1” 90% 90% B OUTPUT 10% 10% “0” tRDAT tSTB tPLH1 tDSTB “1” STB 50% 50% “0” tSSTB tSFR “1” F/R “0” tPHL3 tPHL2 “1” OUTn 90% 90% 10% 10% tPLH2 tPLH3 “0” tBLK “1” BLK (POL=#0#) 50% 50% “0” tPHL4 OUTn tPLH4 90% 90% 10% tF OUT 14/17 3 10% “1” “0” tR OUT STV7610A Figure 2. : Test Configuration V PP=VSSP VPP=V SSP VDOUTH IDOUTH VDOUTL IDOUTL VSSP VSSP Output sinking current as positive value, sourcing current as negative value INPUT/OUTPUT SCHEMATICS Figure 3. : PO L , BLK , F/ R Input Figure 5. : A1 to A6, B1 to B6 VCC VCC VCC VCC A1 to A6, B1 to B6 Pins 59 to 64, 49 to 44 VCC POL, BLK, F/R Pins 51, 50, 52 GNDLOG GNDLOG GNDSUB GNDSUB Figure 4. : CLK, STB Input Figure 6. : Power Output VPP VCC VCC CLK, STB Pins 56, 57 OUT1 to OUT 96 Pins 73 to 105, 112 to 141, 4 to 36 GNDLOG GNDSUB VSSP 15/17 3 STV7610A PACKAGE MECHANICAL DATA 144 PINS - THIN PLASTIC QUAD FLAT PACK (TQFP) A A2 A1 e 144 109 0,076 mm 0.03 inch SEATING PLANE 108 36 73 E3 E1 E B 1 c 72 L1 D3 D1 D L 37 K Millimeters 0,25 mm .010 inch GAGE PLANE Inches Dimensions Min. Typ. A Min. Typ. 1.60 A1 0.05 A2 1.35 B 0.17 C 0.09 0.15 0.002 0.006 1.40 1.45 0.053 0.055 0.057 0.22 0.27 0.0067 0.0087 0.011 0.20 0.0035 0.008 22.00 0.866 D1 20.00 0.787 D3 17.50 0.689 e 0.50 0.020 E 22.00 0.866 E1 20.00 0.787 E3 17.50 0.689 L1 K 0.45 Max. 0.063 D L 16/17 Max. 0.60 0.75 0.018 1.00 0.024 0.039 0° (Min.), 7° (Max.) 0.030 STV7610A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibili ty for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This public ation supersedes and replaces all information previously suppl ied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics. 2000 STMicroelectronics - All Rights Reserved 2 Purchase of I C Components of STMicroelectronics, conveys a license under the Philip s I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www .st.com 17/17 4