Revised February 1999 MM74HC273 Octal D-Type Flip-Flops with Clear General Description The MM74HC273 edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flipflops. They possess high noise immunity, low power, and speeds comparable to low power Schottky TTL circuits. This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the LOW-to-HIGH transition of the CLOCK input. The CLEAR input when LOW, sets all outputs to a low state. Each output can drive 10 low power Schottky TTL equivalent loads. The MM74HC273 is functionally as well as pin compatible to the 74LS273. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Features ■ Typical propagation delay: 18 ns ■ Wide operating voltage range ■ Low input current: 1 µA maximum ■ Low quiescent current: 80 µA (74 Series) ■ Output drive: 10 LS-TTL loads Ordering Code: Order Number MM74HC273M MM74HC273SJ MM74HC273MTC MM74HC273N Package Number Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-153, 0.300” Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC20 N20A 20-Lead thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Top View © 1999 Fairchild Semiconductor Corporation DS005331.prf www.fairchildsemi.com MM74HC273 Octal D-Type Flip-Flops with Clear September 1983 MM74HC273 Truth Table Logic Diagram (Each Flip-Flop) Inputs Outputs Clear Clock D L X X Q L H ↑ H H H ↑ L L H L X Q0 H = HIGH Level (Steady State) L = LOW Level (Steady State) X = Don’t Care ↑ = Transition from LOW-to-HIGH level Q0 = The level of Q before the indicated steady state input conditions were established www.fairchildsemi.com 2 Recommended Operating Conditions −0.5 to +7.0V Supply Voltage (VCC) DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT) −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK) ±20 mA DC Output Current, per pin (IOUT) ±25 mA (VIN, VOUT) Operating Temperature Range (TA) 600 mW 500 mW Symbol VIH VIL VOH Parameter Conditions 0 VCC V −40 +85 °C 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Note 2: Unless otherwise specified all voltages are referenced to ground. 260°C DC Electrical Characteristics V Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Lead Temperature (TL) (Soldering 10 seconds) Units 6 (tr, tf) VCC = 2.0V Power Dissipation (PD) S.O. Package only Max 2 Input Rise or Fall Times −65°C to +150°C (Note 3) Min DC Input or Output Voltage ±50 mA DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Supply Voltage (VCC) Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. (Note 4) VCC TA = 25°C Typ TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Units Minimum HIGH Level 2.0V 1.5 1.5 1.5 V Input Voltage 4.5V 3.15 3.15 3.15 V 6.0V 4.2 4.2 4.2 V Maximum LOW Level 2.0V 0.5 0.5 0.5 V Input Voltage 4.5V 1.35 1.35 1.35 V 6.0V 1.8 1.8 1.8 V Minimum HIGH Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V |IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V |IOUT| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V VIN = VIH or VIL VOL Maximum LOW Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V |IOUT| ≤ 4 mA 4.5V 0.2 0.26 0.33 0.4 V |IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA 6.0V 8 80 160 µA VIN = VIH or VIL IIN Maximum Input ICC Maximum Quiescent VIN = VCC or GND Supply Current IOUT = 0 µA Current Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC273 Absolute Maximum Ratings(Note 1) (Note 2) MM74HC273 AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol fMAX Parameter Conditions Guaranteed Typ Maximum Operating Limit Units 50 30 MHz 18 27 ns 18 27 ns 10 20 ns 10 20 ns −2 0 ns 10 16 ns Frequency tPHL, tPLH Maximum Propagation Delay, Clock to Output tPHL Maximum Propagation Delay, Clear to Output tREM Minimum Removal Time, Clear to Clock ts Minimum Setup Time Data to Clock tH Minimum Hold Time Clock to Data tW Minimum Pulse Width Clock or Clear AC Electrical Characteristics CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol fMAX tPHL, tPLH tPHL Parameter Conditions ts tH tW tr, tf TA = 25°C Typ CPD Guaranteed Limits Units 2.0V 16 5 4 3 MHz Frequency 4.5V 74 27 21 18 MHz 6.0V 78 31 24 20 MHz Maximum Propagation 2.0V 38 135 170 205 ns Delay, Clock to Output 4.5V 14 27 34 41 ns 6.0V 12 23 29 35 ns 2.0V 42 135 170 205 ns Maximum Propagation 4.5V 19 27 34 41 ns 6.0V 18 23 29 35 ns Minimum Removal Time 2.0V 0 25 32 37 ns Clear to Clock 4.5V 0 5 6 7 ns 6.0V 0 4 5 6 ns Minimum Setup Time 2.0V 26 100 125 150 ns Data to Clock 4.5V 7 20 25 30 ns 6.0V 5 17 21 25 ns Minimum Hold Time 2.0V −15 0 0 0 ns Clock to Data 4.5V −6 0 0 0 ns 6.0V −4 0 0 0 ns Minimum Pulse Width 2.0V 34 80 100 120 ns Clock or Clear 4.5V 11 16 20 24 ns 6.0V 10 14 18 20 ns Maximum Input Rise and 2.0V 1000 1000 1000 ns Fall Time, Clock 4.5V 500 500 500 ns 400 400 400 ns 75 95 110 ns 6.0V tTHL, tTLH TA = −40 to 85°C TA = −55 to 125°C Maximum Operating Delay, Clear to Output tREM VCC Maximum Output Rise 2.0V 28 and Fall Time 4.5V 11 15 19 22 ns 6.0V 9 13 16 19 ns Power Dissipation (per flip-flop) 45 pF Capacitance (Note 5) CIN Maximum Input 7 10 10 10 Capacitance Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. www.fairchildsemi.com 4 pF MM74HC273 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Package Number M20B 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com MM74HC273 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 6 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N20A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM74HC273 Octal D-Type Flip-Flops with Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued)