STMICROELECTRONICS STV7699

STV7699
PLASMA DISPLAY PANEL DATA DRIVER
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..
..
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PRODUCT PREVIEW
64 OUTPUTS PLASMA DISPLAY DRIVER
170V ABSOLUTE MAXIMUM SUPPLY
5V SUPPLY FOR LOGIC
50/40mA SOURCE / SINK OUTPUT
60/60mA SOURCE / SINK OUTPUT DIODE
64-BIT SHIFT REGISTER (20MHz)
BLK, POLARITY AND HIZ CONTROL
BCD TECHNOLOGY
DIE or 100-PIN PQFP PACKAGE
PQFP100 (14 x 20 x 2.80mm)
(Full Plastic Quad Flat Pack)
DESCRIPTION
The STV7699 is a Plasma Display Panel (PDP)
data driver implemented in ST’s proprietary BCD
technology. Using a 4-bit wide cascadable shift
register, it drives 64 high current & high voltage outputs. By serialy connecting several STV7699, any horizontal pixel definition can be performed. The 20MHz
shift clock gives an equivalent 80MHz shift register.
The STV7699 is supplied with a separated 170V
power output supply and a 5V logic supply.
ORDER CODE : STV7699
All command inputs are CMOS compatible.
The STV7699 package is a 100-pin PQFP. It is also
available as die.
OUT2
OUT1
VPP
2
1
OUT25
31
100
VCC
OUT26
32
99
A1
OUT27
33
98
A2
OUT28
34
97
A3
VSSP
35
96
A4
OUT29
36
95
CLK
OUT30
37
94
STB
OUT31
38
93
OUT32
39
92
VSSLOG
VSSLOG
91
VSSLOG
90
VSSLOG
89
F/R
88
BLK
STV7699
VSSP
40
VSSSUB
41
OUT33
42
OUT34
43
OUT35
44
87
POL
OUT36
45
86
HIZ
VSSP
46
85
B4
OUT37
47
84
B3
OUT38
48
83
B2
OUT39
49
82
B1
OUT40
50
81
VSSSUB
PQFP100
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
VPP
VPP
OUT41
OUT42
OUT43
OUT44
VSSP
OUT45
OUT46
OUT47
OUT48
OUT49
OUT50
OUT51
OUT52
VSSP
OUT53
OUT54
OUT55
OUT56
OUT57
OUT58
OUT59
OUT60
VSSP
OUT61
OUT62
OUT63
OUT64
VPP
(Top View)
January 1999
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
7699-01.EPS
OUT3
3
OUT5
4
OUT6
7
VSSP
OUT7
8
OUT4
OUT8
9
5
OUT9
10
6
OUT10
11
OUT13
16
OUT11
OUT14
17
12
OUT15
18
13
OUT16
19
VSSP
OUT17
20
OUT12
OUT18
21
14
OUT19
22
15
VSSP
OUT21
25
OUT20
OUT22
26
23
OUT23
27
24
VPP
OUT24
28
VPP
29
30
PIN CONNECTIONS
1/9
STV7699
PIN ASSIGNMENT (PQFP100)
Pin Number
Symbol
Type
Function
100
VCC
Supply
5V Logic Supply
High Voltage Supply of power outputs
1 - 29 - 30 - 51 - 52 - 80
VPP
Supply
6 - 15 - 24 - 35 - 40
46 - 57 - 66 - 75
VSSP
Ground Ground of power outputs
90 to 93
VSSLOG
Ground Logic Ground
41 - 81
VSSSUB
Ground Substrate Ground
Power Output
95
CLK
Input
Clock of data shift register
Low to High transition makes the data enter into the shift
register and available at the output stage and at the output
of the shift register.
94
STB
Input
Latch of data to outputs
When the STB signal is set to low level, data are transferred
into the latch stage. When STB is set at high level, data are
held in the latch stage.
88
BLK
Input
Power Output Blanking Control
87
POL
Input
Power Output Polarity Control
86
HIZ
Input
Power Output High Impedance Control
89
F/R
Input
Selection of shift direction
96 to 99
A4 to A1
Input
82 to 85
B1 to B4
Output
Shift register data input and output according to F/R value.
When set to low, Ai = input and Bi = output.
7699-01.TBL
2 to 5 - 7 to 14 - 16 to 23
OUT1 to OUT 64 Output
25 to 28 - 31 to 34 - 36 to 39
42 to 45 - 47 to 50 - 53 to 56
58 to 65 - 67 to 74 - 76 to 79
Output N°
Pin N°
Output N°
Pin N°
Output N°
Pin N°
Output N°
Pin N°
1
2
17
20
33
42
49
62
2
3
18
21
34
43
50
63
3
4
19
22
35
44
51
64
4
5
20
23
36
45
52
65
5
7
21
25
37
47
53
67
6
8
22
26
38
48
54
68
7
9
23
27
39
48
55
69
8
10
24
28
40
50
56
70
9
11
25
31
41
53
57
71
10
12
26
32
42
54
58
72
11
13
27
33
43
55
59
73
12
14
28
34
44
56
60
74
13
16
29
36
45
58
61
76
14
17
30
37
46
59
62
77
15
18
31
38
47
60
63
78
16
19
32
39
48
61
64
79
2/9
7699-02.TBL
PIN ASSIGNMENT (Power Outputs)
STV7699
PAD DIMENSIONS (in µm)
The reference is the center of the die (x = 0, y = 0).
LEFT SIDE from top to bottom
Name
VPP
OUT1
OUT2
OUT3
OUT4
VSSP
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
VSSP
OUT13
OUT14
OUT15
OUT16
OUT17
OUT18
OUT19
OUT20
VSSP
OUT21
OUT22
OUT23
OUT24
VPP
Center : X Center : Y Size : x
-1738.0
2867.5
90.0
-1738.0
2703.0
90.0
-1738.0
2570.5
90.0
-1738.0
2411.0
90.0
-1738.0
2228.5
90.0
-1738.0
2093.0
90.0
-1738.0
1952.0
90.0
-1738.0
1813.5
90.0
-1738.0
1631.0
90.0
-1738.0
1453.0
90.0
-1738.0
1235.5
90.0
-1738.0
1046.5
90.0
-1738.0
862.0
90.0
-1738.0
712.5
90.0
-1738.0
566.0
90.0
-1738.0
431.0
90.0
-1738.0
293.0
90.0
-1738.0
82.5
90.0
-1738.0
-109.5
90.0
-1738.0
-277.0
90.0
-1738.0
-471.0
90.0
-1738.0
-691.5
90.0
-1738.0
-822.5
90.0
-1738.0
-953.0
90.0
-1738.0
-1096.0
90.0
-1738.0
-1335.5
90.0
-1738.0
-1569.0
90.0
-1738.0
-1697.5
90.0
-1715.0
-2045.0
90.0
Size : y
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
200.0
BOTTOM SIDE from left to right
Name
OUT25
OUT26
OUT27
OUT28
VSSP
OUT29
OUT30
OUT31
OUT32
VSSP
VSSSUB
OUT33
OUT34
OUT35
OUT36
VSSP
OUT37
OUT38
OUT39
OUT40
Center : X Center : Y Size : x
-1443.5
-3077.0
75.0
-1249.0
-3077.0
75.0
-1049.5
-3077.0
75.0
-889.0
-3077.0
5.0
-753.0
-3077.0
75.0
-614.0
-3077.0
75.0
-467.5
-3077.0
75.0
-332.0
-3077.0
75.0
-186.5
-3077.0
75.0
-54.0
-3077.0
75.0
78.0
-3077.0
75.0
209.5
-3077.0
75.0
342.5
-3077.0
75.0
467.5
-3077.0
75.0
607.5
-3077.0
75.0
752.0
-3077.0
75.0
892.5
-3077.0
75.0
1045.5
-3077.0
75.0
1252.0
-3077.0
75.0
1433.5
-3077.0
75.0
Right SIDE from bottom to top
Name
VPP
OUT41
OUT42
OUT43
OUT44
VSSP
OUT45
OUT46
OUT47
OUT48
OUT49
OUT50
OUT51
OUT52
VSSP
OUT53
OUT54
OUT55
OUT56
OUT57
OUT58
OUT59
OUT60
VSSP
OUT61
OUT62
OUT63
OUT64
VPP
Center : X Center : Y Size : x
1600.5
-2087.0
90.0
1737.5
-1646.0
90.0
1737.5
-1507.0
90.0
1737.5
-1328.0
90.0
1737.5
-1096.0
90.0
1737.5
-953.0
90.0
1737.5
-822.5
90.0
1737.5
-691.5
90.0
1737.5
-471.0
90.0
1737.5
-277.0
90.0
1737.5
-109.5
90.0
1737.5
82.5
90.0
1737.5
293.0
90.0
1737.5
431.0
90.0
1737.5
566.0
90.0
1737.5
712.5
90.0
1737.5
862.0
90.0
1737.5
1046.5
90.0
1737.5
1235.5
90.0
1737.5
1453.0
90.0
1737.5
1631.0
90.0
1737.5
1813.5
90.0
1737.5
1952.0
90.0
1737.5
2093.0
90.0
1737.5
2228.5
90.0
1737.5
2411.0
90.0
1737.5
2570.5
90.0
1737.5
2703.0
90.0
1737.5
2873.5
90.0
Size : y
200.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
75.0
TOP SIDE from right to left
Size : y
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
Name
VSSSUB
B1
B2
B3
B4
HIZ
POL
BLK
F/R
VSSLOG
VSSLOG
STB
CLK
A4
A3
A2
A1
VCC
Center : X Center : Y Size : x
1628.5
3073.5
75.0
1478.5
3073.5
75.0
1228.5
3077.0
75.0
978.5
3077.0
75.0
847.5
3077.0
75.0
716.5
3077.0
75.0
486.5
3077.0
75.0
355.5
3077.0
75.0
224.5
3077.0
75.0
31.0
3077.0
200.0
-354.5
3077.0
200.0
-582.0
3077.0
75.0
-713.0
3077.0
75.0
-844.0
3077.0
75.0
-975.0
3077.0
75.0
-1106.0
3077.0
75.0
-1471.5
3077.0
75.0
-1629.0
3077.0
75.0
Size : y
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
3/9
STV7699
BLOCK DIAGRAM
CLK 95
89 F/R
16-BIT SHIFT REGISTER
A1 99
P1
82 B1
P61
16-BIT SHIFT REGISTER
A2 98
P2
83 B2
P62
16-BIT SHIFT REGISTER
A3 97
P3
84 B3
P63
16-BIT SHIFT REGISTER
A4 96
P4
P1
85 B4
P64
100
P63 P64
P4
LATCH
STB 94
Q1 Q2
Q63Q64
VCC
VSSLOG
Pins 90 to 93
BLK 88
VSSSUB
Pins 41-81
VSSP
Pins 6-15-24-35
40-46-57-66-75
POL 87
VPP
Pins 1-29-30
51-52-80
STV7699
2
79
OUT1
OUT64
7699-02.EPS
HIZ 86
CIRCUIT DESCRIPTION
The STV7699 contains all the logic and the power
circuits necessary to drive the colums of a Plasma
Display Panel (P.D.P.). Data are shifted at each low
to high transition of the (CLK) shift clock. Data are
input in a 4-bit wide data bus to A1 - A4 input (case
of forward shift mode ; F/R = low). After 16 shifts,
the first nibble is available at the serial outputs
B1 - B4. These outputs can be used to cascade
several drivers to performed any horizontal resolution. CLK, Ai and Bi inputs are Smith trigger inputs
to improve the noise margin.
The Forward/Reverse (F/R) input is used to select
the direction of the shift register.
The maximum frequency of the shift clock is
20MHz.
All the output data are held and memorized into the
latch stage when the Latch input (STB) is high.
When it is at low level, data are transferred from
the shift register to the latch and to the output power
stage.
Output state can be forced to high impedance by
pulling low HIZ input.
When BLK is Low, all the outputs are forced to low
level or high level according to POL signal value.
Output state copy data that was input, with the
4/9
same polarity, when BLK, HIZ and POL are High.
VSSLOG, VSSSUB and VSSP are not internally connected.
VSSLOG and VSSSUB must be connected as close as
possible to the logical reference ground of the
application.
Table 1 : Power Output Truth Table
Data STB POL BLK HIZ Driver
Output
x
x
x
x
L
HIZ
x
x
L
x
H
L
x
x
H
L
H
H
x
H
H
H
H Qn (1)
L
L
H
H
H
L
H
L
H
H
H
H
Comments
High impedance
Forced to low
Forced to high
Latched data
Copy data
Copy data
Note 1 : Qn is the value memorised in the latch stage ; it is the value
of the parallel shift register output stage after n Clock
pulses.
A data loaded in the shift register is read on the
output power stage without inversion of its polarity.
Table 2 : Control Table
F/R
L
H
Ai
Input
Output
Bi
Output
Input
Comments
Forward shift
Reverse shift
STV7699
Symbol
VCC
VIN
VOUT
VPOUT
VPP
IPOUT
IDOUT
Tjmax
Toper
Tstg
Parameter
Logic Supply
Logic Input Voltage
Logic Output Voltage
Driver Output Voltage
Driver Power Supply
Driver Output Current (2)
Diode Output Current (2)
Junction Temperature
Operating Temperature
Storage Temperature
Value
-0.3, +7
-0.3, VCC + 0.3
-0.3, VCC + 0.3
-0.3, +170
-0.3, +170
±60
+40/-50
+150
-20, +85
-50, +150
Unit
V
V
V
V
V
mA
mA
°C
°C
°C
Value
50
2
+125
Unit
°C/W
W
°C
7699-03.TBL
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Rth(j-a)
Junction-ambient Thermal Resistance (1)
Poper
Operating Power Dissipation (Tamb = 25°C)
Tjoper
Operating Junction Temperature (1)
Max.
Max.
Max.
7699-04.TBL
THERMAL DATA
Notes : 1. For PQFP100 packaging.
2. Through all power outputs : with power dissipation lower or equal than Ptot and junction temperature lower or equal than Tjmax.
ELECTRICAL CHARACTERISTICS
(VCC = 5V, VPP = 160V, VSSP = 0V, VSSLOG = 0V, VSSSUB = 0V, Tamb = 25°C, fCLK = 20MHz,
unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
4.5
-
5
12
-
5.5
100
TBD
160
100
V
µA
mA
V
µA
55
TBD
-
60
2
12
-
5
TBD
3
-3
±10
V
V
V
V
V
V
µA
4
-
0.1
0.3
V
V
0.8 VCC
-
-
0.2 VCC
1
-1
V
V
µA
µA
SUPPLY
VCC
ICCH
ICCL
VPP
IPPH
Logic Supply Voltage
Logic Supply Current
Logic Supply Current
fCLK = 20MHz
Power Output Supply Voltage
Power Output Supply Current (steady outputs)
OUTPUT
OUT1-OUT64
VPOUTH Power Output High Level
VPOUTL
Power Output Low Level
VDOUTH
VDOUTL
IOUTHIZ
IPOUTH = - 10mA, VPP = 65V
IPOUTH = - 40mA, VPP = 65V
IPOUTL = + 10mA
IPOUTL = + 30mA
IDOUTH = + 25mA (3)(4)
IDOUTL = - 25mA (3)(4)
Output Diode High Level
Output Diode Low Level
Output Stage Leakage Current on HIZ State
SHIFT REGISTER OUTPUT (Ai or Bi according to F/R Status)
VOH
Logic Output High Level
IOH = - 0.5mA
VOL
Logic Output Low Level
IOL = + 0.5mA
VIH
VIL
IIH
IIL
Input High Level
Input Low Level
High Level Input Current
Low Level Input Current
VIH = VCC
VIL = 0V
Notes : 3. Compatible with power dissipation and Tjoper ≤ 125°C.
4. See test diagram.
5/9
7699-05.TBL
INPUT (CLK, STB, BLK, HIZ, Ai, Bi)
STV7699
AC TIMINGS REQUIREMENTS
(VCC = 4.5V to 5.5V, Tamb = -20 to +85°C, input signals max leading edge & trailing edge (tR, tF) = 10ns)
Parameter
Min.
Typ. Max. Unit
Data Clock Period
50
-
-
ns
tWHCLK
Duration of clock (CLK) pulse at high level
15
-
-
ns
tWLCLK
Duration of clock (CLK) pulse at low level
15
-
-
ns
tSDAT
Set-up Time of data input before clock (low to high) transition
0
-
-
ns
tHDAT
Hold Time of data input after clock (low to high) transition
15
-
-
ns
tDSTB
Minimum Delay to latch (STB) after clock (low to high) transition
20
-
-
ns
tSTB
Latch (STB) Low Level Pulse Duration
10
-
-
ns
tBLK
Blanking (BLK) Pulse Duration
100
-
-
ns
tPOL
Polarity (POL) Pulse Duration
100
-
-
ns
tHIZ
High Impedance (HIZ) Pulse Duration
100
-
-
ns
tSFR
Set-up Time of Forward/Reverse Signal before Clock (low to high) transition
100
-
-
ns
tCLK
7613-06.TBL
Symbol
AC TIMING CHARACTERISTICS
(VCC = 5V, VPP = 65V, VSSP = 0V, VSSLOG = 0V, VSSSUB = 0V, Tamb = 25°C, VILMax. = 0.2VCC, VIHMin. = 0.8VCC,
VOH = 4.0V, VOL = 0.4V, CL = 10pF, unless otherwise specified)
Parameter
tCLK
Data Clock Period
tRDAT
Min.
Typ. Max. Unit
50
-
-
ns
Logical Data Output Rise Time
-
TBD
30
ns
tFDAT
Logical Data Output Fall Time
-
TBD
30
ns
tPHL1
tPLH1
Delay of logic data output (high to low transition) after clock (CLK) transition
Delay of logic data output (low to high transition) after clock (CLK) transition
-
40
40
TBD
TBD
ns
ns
tPHL2
tPLH2
Delay of power output change (high to low transition) after clock (CLK) transition
Delay of power output change (low to high transition) after clock (CLK) transition
-
TBD
TBD
120
120
ns
ns
tPHL3
tPLH3
Delay of power output change (high to low transition) after Latch (STB) transition
Delay of power output change (low to high transition) after Latch (STB) transition
-
TBD
TBD
110
110
ns
ns
tPHL4
Delay of power output change (high to low transition) to Blank (BLK) or Polarity
(POL) transition
Delay of power output change (low to high transition) to Blank (BLK) or Polarity
(POL) transition
-
TBD
100
ns
-
TBD
100
ns
tPHZ5
tPLZ5
Delay of power output change (high to Hi-Z transition) after high impedance (HIZ) (5)
Delay of power output change (low to Hi-Z transition) after high impedance (HIZ) (5)
-
TBD
TBD
100
100
ns
ns
tPZH5
tPZL5
Delay of power output change (Hi-Z to high transition) after high impedance (HIZ) (5)
Delay of power output change (Hi-Z to low transition) after high impedance (HIZ) (5)
-
TBD
TBD
100
100
ns
ns
tROUT
Power Output Rise Time (6)
-
-
150
ns
tFOUT
Power Output Fall Time (6)
-
-
150
ns
tPLH4
Notes : 5. See test diagram.
6. One output among 64, loading capacitor COUT = 50pF, other outputs at low level.
6/9
7613-07.TBL
Symbol
STV7699
Figure 1 : AC Characteristics Waveform
tCLK
tWHCLK
tWLCLK
"1"
CLK
50%
50%
50%
"0"
tSDAT
tHDAT
"1"
SIN
50%
50%
"0"
tPHL1
tFDAT
"1"
90%
SOUT
50%
10%
"0"
tPLH1
tRDAT
tSTB
tDSTB
STB
"1"
50%
50%
"0"
tSFR
"1"
F/R
50%
"0"
tPHL3
tPHL2
"1"
90%
10%
OUTn
90%
10%
90%
10%
"0"
tPLH3
tPLH2
tPOL
"1"
POL
50%
50%
"0"
tPLH4
tPHL4
"1"
90%
OUTn
10%
"0"
tHIZ
"1"
HIZ
50%
50%
"0"
tROUT
90%
10%
tPZH5
90%
10%
90%
tPLZ5
tPZL5
"1"
10%
"0"
tFOUT
7699-03.EPS
OUTn
90%
10%
tPHZ5
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STV7699
INPUT/OUTPUT SCHEMATICS
Figure 2 : F/R, BLK, POL, HIZ
Figure 3 : CLK, STB
VCC (Pin 100)
VCC (Pin 100)
F/R, BLK, POL, HIZ
(Pins 89, 88, 87, 86)
CLK, STB
(Pins 95, 94)
7699-04.EPS
VSSSUB
(Pins 41-81)
Figure 4 : Ai, Bi
VSSLOG
(Pins 90 to 93)
VSSSUB
(Pins 41-81)
7699-05.EPS
VSSLOG
(Pins 90 to 93)
Figure 5 : Power Output
VCC (Pin 100)
VPP
(Pins 1, 29, 30, 51, 52, 80)
A4 to A1
(Pins 96 to 99)
B1 to B4
(Pins 82 to 85)
8/9
VSSP
(Pins 6, 15, 24, 35, 40, 46, 57, 66, 75)
7699-07.EPS
VSSLOG
(Pins 90 to 93)
VSSLOG
(Pins 90 to 93)
7699-06.EPS
VSSSUB
(Pins 41-81)
OUTi
(Pins 2 to 5, 7 to 14, 16 to 23,
25 to 28, 31 to 34, 36 to 39,
42 to 45, 47 to 50, 53 to 56,
58 to 65, 67 to 74, 76 to 79)
STV7699
PACKAGE MECHANICAL DATA
100 PINS - PLASTIC QUAD FLAT PACK (PQFP)
A
A2
A1
e
80
51
0,10 mm
.004 inch
SEATING PLANE
50
100
31
E3
E1
E
B
81
L1
PMPQF100.EPS
c
30
D3
D1
D
L
1
K
A
A1
A2
B
c
D
D1
D3
e
E
E1
E3
L
L1
K
Min.
0.25
2.55
0.22
0.13
22.95
19.90
16.95
13.90
0.65
Millimeters
Typ.
2.80
23.20
20.00
18.85
0.65
17.20
14.00
12.35
0.80
1.60
Max.
3.40
Min.
3.05
0.38
0.23
23.45
20.10
0.010
0.100
0.0087
0.005
0.903
0.783
17.45
14.10
0.667
0.547
0.95
0.026
Inches
Typ.
0.110
0.913
0.787
0.742
0.026
0.677
0.551
0.486
0.031
0.063
Max.
0.134
0.120
0.015
0.009
0.923
0.791
0.687
0.555
0.037
5F.TBL
Dimensions
0o (Min.), 7o (Max.)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems
without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 1999 STMicroelectronics - All Rights Reserved
Purchase of I2C Components of STMicroelectronics, conveys a license under the Philips I2C Patent.
Rights to use these components in a I2C system, is granted provided that the system conforms to
the I2C Standard Specifications as defined by Philips.
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