STMICROELECTRONICS STW14NC50

STW14NC50
N-CHANNEL 500V - 0.31Ω - 14A TO-247
PowerMesh™II MOSFET
TYPE
STW14NC50
■
■
■
■
■
VDSS
RDS(on)
ID
500V
< 0.38Ω
14 A
TYPICAL RDS(on) = 0.31Ω
EXTREMELY HIGH dv/dt CAPABILITY
100% AVALANCHE TESTED
NEW HIGH VOLTAGE BENCHMARK
GATE CHARGE MINIMIZED
3
2
1
DESCRIPTION
The PowerMESH™II is the evolution of the first
generation of MESH OVERLAY™. The layout refinements introduced greatly improve the Ron*area
figure of merit while keeping the device at the leading edge for what concerns switching speed, gate
charge and ruggedness.
TO-247
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
SWITCH MODE POWER SUPPLIES (SMPS)
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
■
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Drain-source Voltage (VGS = 0)
500
V
Drain-gate Voltage (RGS = 20 kΩ)
500
V
Gate- source Voltage
±30
V
ID
Drain Current (continuos) at TC = 25°C
14
A
ID
Drain Current (continuos) at TC = 100°C
8.7
A
VDS
VDGR
VGS
IDM (●)
PTOT
dv/dt(1)
Tstg
Tj
Parameter
Drain Current (pulsed)
56
A
Total Dissipation at TC = 25°C
190
W
Derating Factor
1.5
W/°C
Peak Diode Recovery voltage slope
Storage Temperature
Max. Operating Junction Temperature
(•)Pulse width limited by safe operating area
May 2001
3.5
V/ns
–65 to 150
°C
150
°C
(1)ISD ≤14A, di/dt ≤100A/µs, V DD ≤ V(BR)DSS, Tj ≤ T JMAX.
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STW14NC50
THERMAL DATA
Rthj-case
Thermal Resistance Junction-case Max
Rthj-amb
Tl
0.66
°C/W
Thermal Resistance Junction-ambient Max
30
°C/W
Maximum Lead Temperature For Soldering Purpose
300
°C
AVALANCHE CHARACTERISTICS
Symbol
Max Value
Unit
IAR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tj max)
Parameter
14
A
EAS
Single Pulse Avalanche Energy
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)
800
mJ
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
Symbol
V(BR)DSS
Parameter
Drain-source
Breakdown Voltage
IDSS
Zero Gate Voltage
Drain Current (VGS = 0)
IGSS
Gate-body Leakage
Current (VDS = 0)
Test Conditions
ID = 250 µA, VGS = 0
Min.
Typ.
Max.
500
Unit
V
VDS = Max Rating
1
µA
VDS = Max Rating, TC = 125 °C
50
µA
±100
nA
VGS = ±30V
ON (1)
Symbol
Parameter
Test Conditions
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
RDS(on)
Static Drain-source On
Resistance
VGS = 10V, ID = 7A
Min.
Typ.
Max.
Unit
2
3
4
V
0.31
0.38
Ω
Typ.
Max.
Unit
DYNAMIC
Symbol
2/8
Parameter
gfs
Forward Transconductance
Test Conditions
VDS > ID(on) x RDS(on)max,
ID =7A
VDS = 25V, f = 1 MHz, VGS = 0
Min.
13
S
Ciss
Input Capacitance
2000
pF
Coss
Output Capacitance
300
pF
Crss
Reverse Transfer
Capacitance
43
pF
STW14NC50
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
Symbol
td(on)
tr
Parameter
Turn-on Delay Time
Rise Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
Test Conditions
Min.
VDD = 250V, ID = 7 A
RG = 4.7Ω, VGS = 10V
(see test circuit, Figure 3)
VDD = 400V, ID = 14 A,
VGS = 10V, RG = 4.7Ω
Typ.
Max.
Unit
20
ns
23
ns
75
90
nC
10
nC
38
nC
SWITCHING OFF
Symbol
tr(Voff)
Parameter
Off-voltage Rise Time
tf
Fall Time
tc
Cross-over Time
Test Conditions
Min.
VDD = 400V, ID = 14 A,
RG = 4.7Ω, VGS = 10V
(see test circuit, Figure 5)
Typ.
Max.
25
Unit
ns
30
ns
62
ns
SOURCE DRAIN DIODE
Symbol
ISD
Parameter
Test Conditions
Min.
Typ.
Source-drain Current
ISDM (2)
Source-drain Current (pulsed)
VSD (1)
Forward On Voltage
ISD = 14 A, VGS = 0
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
ISD = 14 A, di/dt = 100A/µs,
VDD = 100V, Tj = 150°C
(see test circuit, Figure 5)
IRRM
Reverse Recovery Current
Max.
Unit
14
A
56
A
1.6
V
670
ns
6.7
µC
20
A
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
Safe Operating Area
Thermal Impedance
3/8
STW14NC50
Output Characteristics
Transconductance
Gate Charge vs Gate-source Voltage
4/8
Transfer Characteristics
Static Drain-source On Resistance
Capacitance Variations
STW14NC50
Normalized Gate Thereshold Voltage vs Temp.
Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
5/8
STW14NC50
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuit For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/8
STW14NC50
TO-247 MECHANICAL DATA
DIM.
mm.
MIN.
MAX.
MIN.
A
4.85
5.15
0.19
D
2.20
2.60
0.08
0.10
E
0.40
0.80
0.015
0.03
F
1
1.40
0.04
0.05
TYP.
MAX.
0.20
F1
3
0.11
F2
2
0.07
F3
2
2.40
0.07
0.09
F4
3
3.40
0.11
0.13
G
10.90
0.43
H
15.45
15.75
0.60
0.62
L
19.85
20.15
0.78
0.79
L1
3.70
4.30
0.14
L2
L3
18.50
14.20
0.17
0.72
14.80
0.56
0.58
L4
34.60
1.36
L5
5.50
0.21
M
2
3
0.07
0.11
V
5º
5º
V2
60º
60º
Dia
7/8
TYP
inch
3.55
3.65
0.14
0.143
STW14NC50
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granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
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