STY60NM50 N-CHANNEL 500V - 0.045Ω - 60A Max247 Zener-Protected MDmesh™Power MOSFET TYPE STY60NM50 n n n n n n n VDSS RDS(on) ID 500V < 0.05Ω 60 A TYPICAL RDS(on) = 0.045Ω HIGH dv/dt AND AVALANCHE CAPABILITIES IMPROVED ESD CAPABILITY LOW INPUT CAPACITANCE AND GATE CHARGE LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL INDUSTRY’S LOWEST ON-RESISTANCE DESCRIPTION The MDmesh™ is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company’s PowerMESH™ horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company’s proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competition’s products. 2 3 1 Max247 INTERNAL SCHEMATIC DIAGRAM APPLICATIONS The MDmesh™ family is very suitable for increasing power density of high voltage converters allowing system miniaturization and higher efficiencies. ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Drain-source Voltage (VGS = 0) 500 V Drain-gate Voltage (RGS = 20 kΩ) 500 V Gate- source Voltage ±30 V ID Drain Current (continuous) at TC = 25°C 60 A ID Drain Current (continuous) at TC = 100°C 37.8 A Drain Current (pulsed) 240 A Total Dissipation at TC = 25°C 560 W 6 KV 4.5 W/°C VDS VDGR VGS IDM (l) PTOT VESD(G-S) Parameter Gate source ESD(HBM-C=100pF, R=15KΩ) Derating Factor dv/dt (1) Tstg Tj Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature (•)Pulse width limited by safe operating area August 2002 15 V/ns –65 to 150 °C 150 °C (1)ISD ≤60A, di/dt ≤400A/µs, V DD ≤ V(BR)DSS, Tj ≤ T JMAX 1/8 STY60NM50 THERMAL DATA Rthj-case Thermal Resistance Junction-case Max 0.22 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 30 °C/W 300 °C Tl Maximum Lead Temperature For Soldering Purpose AVALANCHE CHARACTERISTICS Symbol Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Parameter 30 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 35 V) 1.4 J ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol Parameter Test Conditions Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating IGSS Gate-body Leakage Current (VDS = 0) V(BR)DSS Min. Typ. Max. 500 Unit V 10 µA VDS = Max Rating, TC = 125 °C 100 µA VGS = ± 20V ± 10 µA ON (1) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 30A Min. Typ. Max. Unit 3 4 5 V 0.045 0.05 Ω Typ. Max. Unit DYNAMIC Symbol gfs (1) Parameter Forward Transconductance Test Conditions VDS > ID(on) x RDS(on)max, ID = 30A VDS = 25V, f = 1 MHz, VGS = 0 35 S Ciss Input Capacitance 7500 pF Coss Output Capacitance 980 pF Crss Reverse Transfer Capacitance 200 pF RG Gate Input Resistance 1.5 Ω f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2/8 Min. STY60NM50 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Parameter Turn-on Delay Time Rise Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge Test Conditions Min. VDD = 250V, ID = 30A RG = 4.7Ω VGS = 10V (see test circuit, Figure 3) VDD = 400V, ID = 60A, VGS = 10V Typ. Max. Unit 51 ns 58 ns 190 266 nC 53 nC 97 nC SWITCHING OFF Symbol tr(Voff) Parameter Off-voltage Rise Time tf Fall Time tc Cross-over Time Test Conditions Min. VDD = 400V, ID = 60A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 5) Typ. Max. Unit 51 ns 46 ns 108 ns SOURCE DRAIN DIODE Symbol ISD Parameter Test Conditions Min. Typ. Source-drain Current Max. Unit 60 A 240 A 1.5 V ISDM (2) Source-drain Current (pulsed) VSD (1) Forward On Voltage ISD = 60A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 60A, di/dt = 100A/µs, VDD = 100 V, Tj = 25°C (see test circuit, Figure 5) 532 9.9 37 ns µC A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 60A, di/dt = 100A/µs, VDD = 100 V, Tj = 150°C (see test circuit, Figure 5) 636 13.4 42 ns µC A trr Qrr IRRM trr Qrr IRRM Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/8 STY60NM50 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STY60NM50 Normalized Gate Threshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/8 STY60NM50 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STY60NM50 Max247 MECHANICAL DATA mm DIM. MIN. A 4.70 TYP. inch MAX. MIN. TYP. MAX. 5.30 A1 2.20 2.60 b 1.00 1.40 b1 2.00 2.40 b2 3.00 3.40 c 0.40 0.80 D 19.70 20.30 e 5.35 5.55 E 15.30 15.90 L 14.20 15.20 L1 3.70 4.30 P025Q 7/8 STY60NM50 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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