TDA7312 DIGITAL CONTROLLED STEREO AUDIO PROCESSOR INPUT MULTIPLEXER: - 4 STEREO INPUTS FOUR SELECTABLE ADDRESSES TWO DIGITAL CONTROL OUTPUTS INPUT AND OUTPUT FOR EXTERNAL EQUALIZER OR NOISE REDUCTION SYSTEM VOLUME CONTROL IN 1.25dB STEPS TREBLE AND BASS CONTROL TWO SPEAKER ATTENUATORS: - INDEPENDENT SPEAKERS CONTROL IN 1.25dB STEPS - INDEPENDENT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SERIAL I2C BUS DESCRIPTION The TDA7312 is a volume, tone (bass and treble) balance (Left/Right) processor for quality audio applications. SDIP30 ORDERING NUMBER: TDA7312 Control is accomplished by serial I2C bus microprocessor interface. The AC signal setting is obtained by resistor networks andswitches combined with operationalamplifiers. Thanks to the used BIPOLAR/CMOS Tecnology, Low Distortion, Low Noise and Low DC stepping are obtained. PIN CONNECTION (Top view) November 1999 1/13 TDA7312 TEST CIRCUIT THERMAL DATA Symbol R th j-pins Description Thermal Resistance Junction-pins SDIP30 Unit 85 °C/W m ax ABSOLUTE MAXIMUM RATINGS Symbol VS Parameter Operating Supply Voltage T amb Operating Ambient Temperature Tstg Storage Temperature Range Value Unit 10.2 V 0 to 70 °C -40 to 150 °C QUICK REFERENCE DATA Symbol Min. Typ. Max. VS Supply Voltage Parameter 6 9 10 VCL Max. input signal handling 2 THD Total Harmonic Distortion V = 1Vrms f = 1KHz 0.01 S/N Signal to Noise Ratio 106 SC Channel Separation f = 1KHz 103 Volume Control 1.25dB step Bass and Treble Control 2db step Fader and Balance Control Mute Attenuation 2/13 1.25dB step Unit V Vrms 0.1 % dB dB -78.75 0 dB -14 +14 dB -38.75 0 100 dB dB TDA7312 BLOCK DIAGRAM 3/13 TDA7312 ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ, RG = 600Ω, all controls flat (G = 0), f = 1KHz unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY VS Supply Voltage IS Supply Current SVR 6 Ripple Rejection 60 9 10 V 8 11 mA 80 dB INPUT SELECTORS R II Input Resistance 35 50 V CL Clipping Level Input 1, 2, 3 2 2.5 70 Vrms KΩ SIN Input Separation (2) 80 100 dB RL Output Load resistance 2 eIN Input Noise KΩ µV 2 VOLUME CONTROL R IV Input Resistance 20 33 50 Control Range 70 75 80 dB AVMIN Min. Attenuation -1 0 1 dB AVMAX Max. Attenuation 70 75 80 dB ASTEP Step Resolution 0.5 1.25 1.75 dB -1.25 -3 0 1.25 2 dB dB C RANGE EA Attenuation Set Error ET Tracking Error VDC DC Steps Av = 0 to -20dB Av = -20 to -60dB adjacent attenuation steps From 0dB to Av max 0 0.5 kΩ 2 dB 3 7.5 mV mV SPEAKER ATTENUATORS Crange Control Range 35 37.5 40 dB SSTEP Step Resolution 0.5 1.25 1.75 dB 1.5 dB 80 100 0 1 3 10 mV mV +14 +16 dB EA AMUTE VDC Attenuation set error Output Mute Attenuation DC Steps adjacent att. steps from 0 to mute dB BASS CONTROL (1) Gb BSTEP RB Control Range Max. Boost/cut +12 Step Resolution 1 2 3 dB Internal Feedback Resistance 34 44 58 KΩ +13 +14 +15 dB 1 2 3 dB 0.2 0.3 V 10 µA TREBLE CONTROL (1) Gt TSTEP Control Range Max. Boost/cut Step Resolution DIGITAL OUTPUTS VCESAT Ileak 4/13 VOUT = Low IC =1mA I leakage VOUT = VS TDA7312 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. 2 2.5 Max. Unit AUDIO OUTPUTS VOCL Clipping Level RL Output Load Resistance CL Output Load Capacitance d = 0.3% Vrms 2 KΩ 10 nF ROUT Output resistance 30 75 120 Ω VOUT DC Voltage Level 4.2 4.5 4.8 V 2.5 5 15 µV µV GENERAL e NO Output Noise BW = 20-20KHz, flat output muted all gains = 0dB 3 µV Signal to Noise Ratio all gains = 0dB; VO = 1Vrms 106 dB Distortion AV = 0, VIN = 1Vrms AV = -20dB VIN = 1Vrms V IN = 0.3Vrms 0.01 0.09 0.04 A curve all gains = 0dB S/N d Sc Channel Separation left/right Total Tracking error 80 AV = 0 to -20dB -20 to -60 dB 0.1 0.3 % % % 1 2 dB dB 1 V 103 0 0 dB BUS INPUTS V IL Input Low Voltage VIH Input High Voltage 3 IIN Input Current -5 VO Output Voltage SDA Acknowledge IO = 1.6mA V +5 µA 0.4 V ADDRESS PIN (Internal 50KΩ pull down resistor). Notes: SDA, SCL, DIG OUT 1, DIG OUT 2 Pins are high impedance when V S = 0 (1) Bass and Treble response see attached diagram (fig.16). The center frequency and quality of the resonance behaviour can be choosen by the external circuitry. A standard first order bass response can be realized by a standard feedback network (2) The selected input is grounded thru the 2.2µF capacitor. Figure 1: Noise vs. Volume/Gain Settings Figure 2: Signal to Noise Ratio vs. Volume Setting 5/13 TDA7312 Figure 3: Distortion & Noise vs. Frequency Figure 4: Distortion & Noise vs. Frequency Figure 5: Distortion vs. Load Resistance Figure 6: Channel Separation (L → R) vs. Frequency Figure 7: Input Separation (L1 → L2, L3, L4) vs. Frequency Figure 8: Supply Voltage Rejection vs. Frequency 6/13 TDA7312 Figure 9: Output Clipping Level vs. Supply Voltage Figure 10: Quiescent Current vs. Supply Voltage Figure 11: Supply Current vs. Temperature Figure 12: Bass Resistance vs. Temperature Figure 13: Typical Tone Response (with the ext. components indicated in the test circuit) 7/13 TDA7312 I2C BUS INTERFACE Data transmission from microprocessor to the TDA7312 and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 14, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.15 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acFigure 14: Data Validity on the I2CBUS Figure 15: Timing Diagram of I2CBUS Figure 16: Acknowledge on the I2CBUS 8/13 knowledge bit. The MSB is transferred first. Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 16). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. TDA7312 address (the 8th bit of the byte must be 0). The TDA7312 must always acknowledge at the end of each transmitted byte. A sequence of data (N-bytes + acknowledge) A stop condition (P) SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte, containing the TDA7312 TDA7312 ADDRESS S MSB first byte 1 0 0 0 LSB MSB LSB DATA 1 ADDR ADDR 0 ACK 2 1 MSB LSB DATA ACK ACK P Data Transferred (N-bytes + Acknowledge) ACK = Acknowledge S = Start P = Stop SOFTWARE SPECIFICATION ADDR2 ADDR1 Chip address 1 MSB 0 0 0 1 ADDR ADDR 0 2 1 LSB CHIP ADDRESS 0 0 88 HEX 0 1 8A HEX 1 0 8C HEX 1 1 8E HEX DATA BYTES MSB 0 1 1 0 0 0 LSB 0 0 0 1 1 1 B2 0 1 0 1 1 B1 B1 B1 D2 0 1 B0 B0 B0 D1 C3 C3 A2 A2 A2 S2 C2 C2 A1 A1 A1 S1 C1 C1 A0 A0 A0 S0 C0 C0 FUNCTION Volume control Speaker ATT L Speaker ATT R Audio switch Bass control Treble control Ax = 1.25dB steps; Bx = 10dB steps; Cx = 2dB steps; Sx = Input Selector; D X = Dig Out Pins 9/13 TDA7312 SOFTWARE SPECIFICATION (continued) DATA BYTES (detailed description) Volume MSB 0 0 LSB 0 0 B2 B1 B0 B2 B1 B0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 A2 A1 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 A2 A1 A0 FUNCTION Volume 1.25dB steps 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 Volume 10dB steps 0 -10 -20 -30 -40 -50 -60 -70 For example a volume of -45dB is given by: 0 0 1 0 0 1 0 0 Speaker Attenuators MSB 1 1 LSB 0 0 0 1 B1 B1 B0 B0 0 0 1 1 0 1 0 1 1 1 A2 A2 A1 A1 A0 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 0 -10 -20 -30 1 For example attenuation of 25dB on speaker R is given by: 1 0 1 1 0 1 0 0 10/13 FUNCTION Speaker L Speaker R 1 1 Mute TDA7312 Audio Switch MSB 0 LSB 1 0 D2 D1 S2 S1 S0 1 1 1 1 0 0 1 1 0 1 0 1 0 1 FUNCTION Audio Switch Stereo 1 Stereo 2 Stereo 3 Stereo 4 DIG. OUT 1 = 0 DIG. OUT 1 = 1 DIG. OUT 2 = 0 DIG. OUT 2 = 1 0 1 Bass and Treble 0 0 1 1 1 1 0 1 C3 C3 C2 C2 0 0 0 0 1 1 1 1 C1 C1 0 0 1 1 0 0 1 1 C0 C0 0 1 0 1 0 1 0 1 Bass Treble -14 -12 -10 -8 -6 -4 -2 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 0 2 4 6 8 10 12 14 C3 = Sign For example Bass at -10dB is obtained by the following 8 bit string: 0 1 1 0 0 0 1 0 Status at Power on Reset Volume = 78.75dB Treble = Bass = +2dB Spkrs Attenuators = Mute Input = Stereo 1 Dig. OUT 1 = Dig. OUT 2 = 1 11/13 TDA7312 mm DIM. MIN. inch TYP. MAX. A MIN. TYP. 5.08 MAX. 0.20 A1 0.51 A2 3.05 3.81 4.57 0.12 0.15 0.18 B 0.36 0.46 0.56 0.014 0.018 0.022 B1 0.76 0.99 1.40 0.030 0.039 0.055 C 0.20 0.25 0.36 0.008 0.01 0.014 D 27.43 27.94 28.45 1.08 1.10 1.12 E 10.16 10.41 11.05 0.400 0.410 0.435 E1 8.38 8.64 9.40 0.330 0.340 0.370 0.020 e 1.778 0.070 e1 10.16 0.400 L 2.54 M S 12/13 3.30 3.81 0.10 0°(min.), 15°(max.) 0.31 OUTLINE AND MECHANICAL DATA 0.012 0.13 0.15 SDIP30 (0.400”) TDA7312 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics – Printed in Italy – All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philips I 2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 13/13