TDA7326 AM-FM RADIO FREQUENCY SYNTHESIZER FM INPUT AND PRECOUNTER FOR UP TO 140MHz AM INPUT FOR UP TO 40MHz 6-BIT SWALLOW COUNTER, 8-BIT PROGRAMMABLE COUNTER FOR FM AND SW 14-BIT PROGRAMMABLE COUNTER FOR LW AND MW THREE WIRES 8-BIT SERIAL INTERFACE ON-CHIP REFERENCE OSCILLATOR AND COUNTER PROGRAMMABLE SCANNING STEPS FOR AM AND FM DIGITAL PHASE DETECTOR AND LOOP FILTER TWO SEPARATE FREE PROGRAMMABLE FILTER APPLICATIONS AVAILABLE TUNING VOLTAGE OUTPUT 0.5 TO 9.5V PROGRAMMABLE CURRENT SOURCES TO SET THE LOOP GAIN ON-CHIP POWER ON RESET STANDBY MODE DIP16 SO16W ORDERING NUMBERS: TDA7326 (DIP16) TDA7326D (SO16W) DESCRIPTION The TDA7326 is a PLL frequency synthesizer in CMOS technology that performs all the function of a PLL radio tuning system for FM and AM (LW, MW, SW) BLOCK DIAGRAM July 1994 1/16 TDA7326 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VDD1 - VSS Supply Voltage - 0.3 to + 7 V VDD2 - VSS Supply Voltage - 0.3 to + 12 V Input Voltage VSS - 0.3 to VDD + 0.3 V Output Voltage VSS - 0.3 to VDD + 0.3 V VIN VOUT Input Current - 10 to + 10 mA IOUT Output Current - 10 to + 10 mA Tstg Storage Temperature - 55 to + 125 o TA Ambient Temperature -40 to + 85 o IIN C C PIN CONNECTION THERMAL DATA Symbol Parameter Rth j-amb Thermal Resistance Junction-ambient Figure 1:Input Sensitivity 2/16 DIP 16 SO 16L Unit 100 200 °C/W TDA7326 ELECTRICAL CHARACTERISTICS (Tamb = 25°C ; VDD1 = 5V; VDD2 = 9V fOSC = 4MHz; RISET = 68KΩ; unless otherwise specified.) Symbol Parameter Test Condition VDD1 Supply Voltage VDD2 Supply Voltage IDD1 FM Supply Current no output load, FM mode, fin = 100MHz IDD1 AM Supply Current no output load, AM mode, fin = 1MHz IDD1 STB Supply Current Standby mode IDD2 Supply Current VREF Voltage at pin 3 ViSET Voltage at pin 2 Min. Typ. Max. Unit 4.5 5.0 5.5 V 9.0 10.0 V 10 18 25 mA 3 5 10 mA 3 20 µA 0.5 2 3 mA 3.0 3.5 4.0 V RiSET = 68KΩ 7.0 8.0 9.0 V 20 MHz MHz RF INPUT (AMIN FMIN) fiAM Input Frequency AM Direct Mode, Vin = 50mV 0.5 Swallow Mode, Vin = 50mV 16 40 fiFM Input Frequency FM Sinus, Vin = 50mV 30 140 MHz ViAM Input Voltage AM Direct Mode 0.6 to 16MHz (Sinus) 40 600 mVrms Swallow Mode 16 to 40MHz (Sinus) 40 600 mVrms 30 600 mVrms ViFM Input Voltage FM 70 to 120MHz (Sinus) Zin Input Impedance FM fin = 120MHz 200 Ω Zin Input Impedance AM fin = 12MHz 1400 Ω OSCILLATOR fOSC Oscillator Frequency 4 tbu Built Up Time Euro-Quartz ITT C in Internal Capacitance 9 C OUT MHz 100 Internal Capacitance 9 Zin Input Impedance 4 Vin Input Voltage 0.5 ms pF pF 15 KΩ VDD1 Vpp PLL CHARACTERISTICS fstep Step Width AM 1/2.5 KHz fstep Step Width FM 12.5/25 KHz fref Ref Frequency AM 1/2.5 KHz fref Ref Frequency FM 12.5/25 KHz -0.1 µA LOOP FILTER INPUT (LPIN1, LPIN2 = PIN 15,16) -Iin Input Leakage Current VIN = VSS; Phase Detector Output = Tristate Iin Input Leakage Current VIN = VDD; Phase Detector Output = Tristate -1 0.1 +1 µA 3/16 TDA7326 ELECTRICAL CHARACTERISTICS (continued) LOOP FILTER OUTPUT (LPOUT = PIN 14) Symbol Parameter Test Condition vOL Output Voltage Low ILOAD = 0.2mA VDD2; = 10V VOH Output Voltage High -ILOAD = 0.2mA VDD2; = 10V Min. 9 Typ. Max. Unit 0.5 0.8 V 9.5 V CHARGE PUMP CURRENT GENERATION (LPIN1, LPIN2 = PIN 15, 16) Isi -Iso Sink Current LPIN1,2 Source Current LPIN1,2 CURR1 = 0, CURR2 = 0 2 5 7 µA CURR1 = 0, CURR2 = 1 120 200 280 µA CURR1 = 1, CURR2 = 1 180 300 420 µA µA CURR1 = 1, CURR2 = 0 370 500 630 CURR1 = 0, CURR2 = 0 2 5 7 µA CURR1 = 0, CURR2 = 1 120 200 280 µA CURR1 = 1, CURR2 = 1 180 300 420 µA CURR1 = 1, CURR2 = 0 370 500 630 µA 0.2 0.5 V DOUT1 OPENDRAIN OUTPUT(PIN 9) vOL Output Voltage Low ILOAD = 1mA BUS INTERFACE -IIL Input Leakage Current VIN = VSS -1 0.1 1 µA IIH Input Leakage Current VIN = VSS -1 0.1 1 µA vIH Input Voltage High Leading edge 3.4 VIL Input Voltage Low Leading edge 1.6 V 4.0 1.0 V BUS INTERFACE, WAITING TIME (see fig. 5) The Data is Acquired at the High → Low Clock Transition t1 CLK Low to DLEN L → H µs t3 DATA Transition to CLK H → L 0.1 µs t5 CLK H → L to DATA Transition 0.4 µs 5 µs FM mode 180 µs AM mode 2 ms 0.1 µs 0.2 BUS INTERFACE, DATA REPETITION TIME (see fig. 5) tr1 Release Time Between 2 bytes, except byte 4 tr2 Release Time after the transmission of byte 4 BUS INTERFACE, SETUP TIME (see fig. 5) t2 DLEN High to CLK L → H BUS INTERFACE, HOLD TIME (see fig. 5) t4 DATA Transition to CKL L → H t6 CLK H → L to DLEN H → L fCLK 0 µs 0.4 µs CLK Frequency 500 Duty Cycle 4/16 50 KHz % tpl Clock Pulse Low 1 µs tph Clock Pulse High 1 µs TDA7326 The loop gain can be set for different conditions. After a power on reset, all registers are reset to zero and the standby mode is activated. In standby mode, oscillator, reference counter, AM input and FM input are stopped. The power consumption is reduced to a minimum. 2.0 GENERAL DESCRIPTION This circuit contains a frequency synthesizer and a loop filter for an FM and AM radio tuning system. Only a VCO is required to build a complete PLL system. For FM and SW application, the counter works in a two stages configuration. The first stage is a swallow counter with a four modulus (:32/33/64/65) precounter. The second stage is an 8-bit programmable counter. For LW and MW application, a 14-bit programmable counter is available. The circuit receives the scaling factors for the programmable counters and the values of the reference frequencies via a three line serial bus interface. The reference frequency is generated by a 4MHz XTAL oscillator followed by the reference divider. An external oscillator (f = 4MHz) can be used instead of the internal one; it must be connected to OSCIN (pin 7). The reference step-frequency is 1 or 2.5kHz for AM. For FM mode a step frequency of 12.5 and 25kHz can be selected. The circuit checks the format of the received data words. Valid data in the interface shift register are stored automatically in buffer registers at the end of transmission. The output signals of the phase detector are switching the programmable current sources. Their currents are integrated in the loop filter to a DC voltage.The values of the current sources are programmable by two bits also received via the serial bus. The loop filter amplifier is supplied by a separate positive power supply, to minimize the noise induced by the digital part of the system. 3.0 DETAILED DESCRIPTION OF THE PLL FREQUENCY SYNTHESIZER 3.1 INPUT AMPLIFIERS The signals applied on AM and FM input are amplified to get a logic level in order to drive the frequency dividers. 3.1.1 Input Impedance The typical input impedance: for the FM input is 200Ω and for AM input is 1.4kΩ. 3.1.2 Input sensitivity (see Figures 1a and 1b). 3.2 DATA AND CONTROL REGISTER 3.2.1 Register Location The data registers (bit2...bit7) for the control register and the data registers PC7...PC0, SC5...SC0 for the counters are organized in four words, identified by two address bits (bit 7 and bit 6), bit 7 is the first bit to be sent by the controller, bit0 is the last one. The order and the number of the bytes to be transmitted is free of choice. The modification of the PC7...PC0 registers is valid for the internal counters only after transmission of byte 4 (SC5...SC0). 3.2.2 CONTROL AND STATUS REGISTERS Register Configuration ADDRESS BITS DATA BITS BYTE MSB-BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 Function adr 0 adr 1 data 0 data 1 data 2 data 3 data 4 data 5 byte 1 0 0 test 0 test 1 test 2 SOUT CURR2 fREF byte 2 0 1 PC7 PC6 LPF1/2 CURR 1 SWM/DIR AM/FM byte 3 1 0 PC5 PC4 PC3 PC2 PC1 PC0 byte 4 1 1 SC5 SC4 SC3 SC2 SC1 SC0 REGISTER NAME SWM/DIR AM/FM fREF CURR1 CURR2 LPF1/LPF2 SOUT FUNCTION Swallow direct-mode switch 1 = SWM, 0 = DIR AM - FM band switch 1=AM, 0 = FM Selection of reference frequency (see table 3.4) Current select of change pump Current select of change pump Loop filter input select 1= IPF1, 0 = IPF2 Switch output condition 1=output high, 0 = output low 5/16 TDA7326 3.3 DIVIDER FROM VCO FREQUENCY TO REFERENCE FREQUENCY This divider provides a low frequency fSYN which is phase compared with the reference frequency fREF. 3.4 OPERATING MODE Four operating modes are available: - FM mode, - AM swallow mode, - AM direct mode, - Standby mode They are user programmable with the SWR/DIR and AM/FM bits in the byte 2. Standby mode: all functions are stopped. This allows low current consumption without lost of information in all register, it is activated by forcing bit 0 (AM/FM) and bit 1 (SWM/DIR) both at zero value. MODE SECTION SWM/DIR AM/FM STAND-BY 0 0 FM 1 0 AM SWALLOW 0 1 AM DIRECT 1 1 3.4.1 FM and AM (SW) Operation (Swallow Mode) The FM or AM signal is applied to a four modulus: 32/33/64/65 high speed prescaler, which is controlled by a 6 bit divider ’A’.This divider is controlled by the 6 bit SC register. In parallel the output of the prescaler is connected to a 8 bit divider ’B’. This divider is controlled by the 8 bit PC register. For FM mode with 25kHz reference frequency operation, the divider A is a 5 bit divider. The high speed prescaler is working in : 32/33 dividing mode. Bit 6 of the SC register has to be kept to ”0”. Dividing range calculation : For FM mode with 12.5kHz reference frequency and SW swallow mode operation : fVCO = [ 65 ⋅ A1 + (B1 + 1 - A1) ⋅ 64 ] . fREF or fVCO = (64 ⋅ B1 + A1 + 64) ⋅ fREF Important : For correct operation B ≥ 64 and B ≥ A. At FM mode with 25kHz reference frequency : fVCO = [ 33 ⋅ A2 + (B2 + 1 - A2) ⋅ 32 ] ⋅ fREF fVCO = (32 ⋅ B2 + A2 + 32) ⋅ fREF Important: For correct operation B ≥ 32 and B ≥ A. A and B are variable values of the dividers. To keep the actual tuning frequency after a modification of the reference frequency, the values of the dividers have to be modified in the following way. Switching from 25kHz to 12.5kHz reference frequency : B1 = B2, A1 = A2 ⋅ 2 Switching from 12.5kHz to 25kHz reference frequency: A1 (A1 + 1) and A2 = B2 = B1, A2 = 2 2 for odd values A1. The AM signal is directly applied to the 14 bit static divider ’C’. This divider is controlled by both SC and PC registers. Dividing range: fVCO = (C + 1) ⋅ fREF Figure 2: FM and AM (SW) operation (swallow mode) OSC IN PREDIVIDER R fref fsyn PD REGISTER SC5 .. SC0 AM IN COUNTER A REGISTER PC7 .. PC0 PREDIVIDER M/M+1 COUNTER B FM IN D94AU101 6/16 TDA7326 Figure 3: AM direct mode operation for SW, MW and LW OSC IN fref PREDIVIDER R fsyn PD MSB AM IN REGISTER PC7 .. PC0 REGISTER SC5 .. SC0 COUNTER : C FM IN D94AU102 3.4 REFERENCE FREQUENCY GENERATOR The crystal oscillator clock is divided by the reference frequency divider to provide the reference frequency to the phase comparator. Reference frequency divider range is selectable by the programming bit ’fREF’. Available reference frequency are shown in following table. TABLE 3.4 AM/FM fREF fREF (kHz) 0 0 12.5 0 1 25 1 0 1 1 1 2.5 Figure 4: Phase comparator 7/16 8/16 DATA CLK DLEN t1 t3 t2 tph t5 t4 tpl byte 1 - 3 tR1 byte 1 - 3 byte 4 D94AU103 byte 1 - 4 TDA7326 Figure 5 TDA7326 3.5 THREE STATE PHASE COMPARATOR The phase comparator generates a phase error signal according to phase difference between fSYN and fREF. This phase error signal drives the charge pump current generator 3.6 CHARGE PUMP CURRENT GENERATOR This system generates signed pulses of current. Duration and polarity of those pulses are determined by the phase error signal. The absolute current values are programmable by ’CURR1’ and ’CURR2’ bits and controlled by an external resistor RISET connected to Pin 2 and GND. 3.7 LOW NOISE CMOS OP-AMP A low noise Op-Amp is available on chip. The positive input of this Op-Amp is connected to an internal voltage divider and to Pin 3 ’VREF’. The negative input is connected to the charge pump output. In cooperation with this internal amplifier and external components, an active filter can be provided. To increase the flexibility in application the negative input can be switched to two input pins (Pins 15 and 16). This switch is controlled by ’LPF’ register with ’LPF’ low Pin 15 is active and ’LPF’ high Pin 16 is active. This feature allows two separate active filters with different performance. 3.8 TEST FUNCTION The test pin (Test Out) is used only for testing: it has no use in real applications. The three bits test0, test1, test2, of the test REGISTER must be programmed as 0,0,0 in application. Some device internal signals can be checked at pin 9 (TST OUT) and pin 7 (OSC IN) by programming different codes of the test register according to the Table 1. For example by programming the code 110 the ”fsyn out” will be available at pin 9 and ”fREF input” at pin 7. TABLE 1: Test Register Status Test Function test 0 test 1 test 2 0 0 0 1 0 0 fref Output 0 1 0 Phi Output fref Input 1 1 0 fsyn Output fref Input 0 0 1 Phi input Oscin (appl. mode) PIN9 (TEST/OUT) PIN 7 (OSCIN) Sout (appl. mode) Oscin (appl. mode) Oscin (appl. mode) 3.9 C-BUS INTERFACE This interface allows communication between the PLL device and µp systems. A bus control system check the format of transmission, only eight bit word transmission is allowed. Four registers with 6 bit are user programmable. The selection of this four registers is controlled by two address bits. 9/16 TDA7326 4.0 BIT ORGANIZATION OF THE BUS TRANSFER OPERATION Loading registers for all bytes of the programmable counters and all control registers 0 1 PC7 PC6 LPF1/ SWM CURR1 LPF2 DIR 1 1 SC5 (0)* SC4 SC3 SC2 AM FM SC1 1 0 SC0 0 PC5 PC4 PC3 PC2 0 0 0 0 PC3 PC2 PCO ⇒ SOUT CURR2 fref PC1 Loading registers for all bytes of the programmable counters and all control registers 0 1 PC7 PC6 LPF2/ SWM CURR1 LPF1 DIR AM FM 1 1 1 SC5 (0)* SC4 SC1 SC0 SC3 SC2 0 PC5 PC4 PC1 PCO ⇒ Loading registers for 11 or 12 bits of the programmable counters 1 0 PC5 PC4 PC3 PC2 PC1 PC0 1 1 SC5 (0)* SC4 SC3 SC2 SC1 SC0 Loading registers for 5 or 6 bits of the programmable counters 1 1 SC5 (0)* SC4 SC3 SC2 SC1 SC0 Setting control register for loop filter selection charge pump current bit 1, mode AM/FM selection 0 1 X X LPF2/ CURR1 SWM/ LPF1 DIR AM FM Test mode inizialization (Test0 = Test1 = Test2 = 0) 0 0 TST0 TST1 TST2 SOUT CURR2 fREF Setting control register for switch output pin 9, charge pump current bit 2, reference frequency select 0 0 0 0 0 SOUT CURR2 fREF (*) This bit has to be ”0” for fREF = ”1” (fREF = 25kHz in FM mode or 2.5KHz AM swallow mode) 5.0 FREQUENCY PROGRAMMATION 5.1 AM/FM Computation Resume FM SWALLOW MODE fREF = 12.5KHz FVCO = (64 ⋅ PC + SC + 64) ⋅ fREF FVCO = (DIV_VAL+ 64) ⋅ fREF fREF = 25KHz FVCO = (32 ⋅ PC + SC + 32) ⋅ fREF FVCO = (DIV_VAL+ 32) ⋅ fREF where: PC = Program Counter Value (PC7 to PC0) 10/16 swallow 6bit swallow 5bit (bit SC5 = 0) SC = Swallow Counter Value (SC5 to SC0) DIV_VAL = Divider Factor TDA7326 AM SWALLOW MODE FVCO = (64 ⋅ PC + SC + 64) ⋅ fREF fREF = 1KHz FVCO = (DIV_VAL+ 64) ⋅ fREF swallow 6bit FVCO = (32 ⋅ PC + SC + 32) ⋅ fREF fREF = 2.5KHz FVCO = (DIV_VAL+ 32) ⋅ fREF swallow 5bit (bit SC5 = 0) AM DIRECT MODE FVCO = (DIV_VAL+ 1) ⋅ fREF 5.2: Examples a) CONDITIONS: FM MODE (fRF = 98.1MHz, fREF = 25KHz; IF = 10.7MHz it follows: that FVCO = 98.1 + 10.7 = 108.8MHz FVCO - 32 =4352 - 32 = 4320 = 10 E 0 Hex DIV_VAL = fref = 1 0 0 0 0 1 1 1 0 0 0 0 0 0 binary ⇒ PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 SC5 SC4 SC3 SC2 SC1 SC0 SC = 0 (*) PC = 135 b) CONDITIONS: FM MODE (fRF = 98.8MHz, fREF = 25KHz; IF = 10.7MHz it follows: FVCO = 98.8 + 10.7 = 109.5MHz DIV_VAL = 4380 - 32 = 4348 = 10 FC Hex = 1 0 0 0 0 1 1 1 0 1 1 1 0 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 SC5 SC4 SC3 SC2 SC1 SC0 binary ⇒ SC = 28 (*) PC = 135 NOTE: (*) The bit SC5 is FORCED = 0, and higher weigth bits are left shift ed one position. 11/16 TDA7326 c) CONDITIONS: FM MODE (fRF = 98.8MHz, fREF = 12.5KHz; IF = 10.7MHz it follows: FVCO = 98.8 + 10.7 = 109.5MHz DIV_VAL = 8760 - 64 = 8696 = 21 F8 Hex 1 = 0 0 0 0 1 1 1 1 1 1 0 0 0 binary ⇒ PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 SC5 SC4 SC3 SC2 SC1 SC0 PC = 135 d) CONDITIONS: AM DIRECT MODE, (fRF = 530KHz, fREF = 1KHz; IF = 450KHz it follows: FVCO = 530 + 450 = 980KHz FVCO 980 DIV_VAL = ± 1= ± 1 = 979 = 3D3 Hex fREF 1 0 = 0 0 0 1 1 1 1 0 1 0 0 1 1 binary PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 SC5 SC4 SC3 SC2 SC1 SC0 e) CONDITIONS: AM DIRECT MODE, (fRF = 1710KHz, fREF = 1KHz; IF = 450KHz it follows: FVCO = 1710 + 450 = 2160KHz FVCO 2160 ± 1 = 2159 = 86F Hex DIV_VAL = ± 1= 1 fREF = 0 0 1 0 0 0 0 1 1 0 1 1 1 1 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 SC5 SC4 SC3 SC2 SC1 SC0 12/16 SC = 56 binary TDA7326 Figure 5: Application with two loop-filters *) C7 must be connected as closed as possible between pin 10 and pin 13 Figure 6: PC Board and Component Layout of fig. 5 13/16 TDA7326 DIP16 PACKAGE MECHANICAL DATA mm DIM. MIN. a1 0.51 B 0.77 TYP. MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 14/16 inch 3.3 0.130 1.27 0.050 TDA7326 SO16 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 2.65 0.1 0.104 0.2 a2 MAX. 0.004 0.012 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 0.020 c1 45° (typ.) D 10.1 10.5 0.398 0.413 E 10.0 10.65 0.394 0.419 e 1.27 0.050 e3 8.89 0.350 F 7.4 7.6 0.291 0.299 L 0.5 1.27 0.020 0.050 M S 0.75 0.030 8° (max.) 15/16 TDA7326 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 16/16