TDA7345 DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX 1 STEREO INPUT VOLUME CONTROL IN 1.25dB STEP TREBLE AND BASS CONTROL THREE SURROUND MODES ARE AVAILABLE: – MOVIE, MUSIC AND SIMULATED FOUR SPEAKER ATTENUATORS: – 4 INDEPENDENT SPEAKERS CONTROL IN 1.25dB STEPS FOR BALANCE FACILITY – INDEPENDENT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS SO28 ORDERING NUMBER: TDA7345D DESCRIPTION The TDA7345 is a volume tone (bass and treble) balance (Left/Right) processor for quality audio applications in car radio and Hi-Fi systems. It reproduces surround sound by using phase shifters and a signal matrix. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor net- works and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained. PIN CONNECTION CREF 1 28 Vs PS2 2 27 PS3 PS1 3 26 PS4 LP1 4 25 LP HP1 5 24 REAR IN HP2 6 23 REAR OUT L-in 7 22 R-in BASS-LA 8 21 BASS-RA BASS-LB 9 20 BASS-RB TREBLE-L 10 19 TREBLE-R REC_OUT_L 11 18 DIG GND REC_OUT_R 12 17 SDA Lout 13 16 SCL Rout 14 15 AGND D94AU191A November 1999 1/18 R-in 0.47µF L-in 0.47µF 22 7 50K 50K + 28 VS - + - - + 15 L-R AGND SUPPLY R6 + 1 RPS2 RPS1 RLP1 RHP1 R5 2 C5 22µF CREF 25 MOVIE/ MUSIC SIM PS1 90Hz 1.2nF LP LPF 9KHz 23 REAR OUT EFFECT CONTROL OFF 24 MOVIE/SIM PS3 400Hz RPS3 27 PS3 22nF MUSIC PHASE SHIFTER PS2 4KHz PS2 3 PS1 6 HP2 HP1 5 4 100nF LP1 100nF 680nF REAR IN MIXING AMP MIXING AMP PS4 400Hz RPS4 26 PS4 22nF VOL VOL BASS RB 9 100nF 21 5.6K 100nF BASS-RA RB BASS 100nF 20 TREBLE(L) 5.6nF TREBLE 10 19 5.6nF TREBLE(R) TREBLE I2 C BUS DECODER + LATCHES 8 BASS-LA 5.6K 100nF BASS-LB BASS-RB 2/18 5.6nF MUTE 12 14 18 17 16 13 11 D94AU192A SPKR ATT MUTE SPKR ATT MUTE SPKR ATT MUTE SPKR ATT REC_ OUT_R ROUT DIG GND SDA SCL LOUT REC_OUT_L TDA7345 BLOCK DIAGRAM TDA7345 TEST CIRCUIT 5.6nF C15 100nF C14 100nF C13 22µF C3 LP1 HP1 680nF C16 0.47µF HP2 L-in PS1 4 PS2 3 2 10µF C1 100nF C2 CREF 22nF C4 VS 1 28 22nF C5 PS3 PS4 27 26 5 6 1.2nF C6 REAR IN 24 7 2.2µF REAR OUT 23 C17 C10 100nF 8 21 9 20 BASS-RA C21 100nF BASS-LB R2 5.6K TREBLE-L 5.6nF C22 D94AU193A 0.47µF C7 R-in 22 TDA7345 C20 100nF BASS-LA LP 25 C11 100nF 10 BASS-RB R1 5.6K TREBLE-R 19 11 12 13 REC OUT L REC OUT R LOUT 14 ROUT AGND 15 16 17 SCL SDA 5.6nF C12 18 DIG GND THERMAL DATA Symbol R th j-pins Description Thermal Resistance Junction-pins Value Unit 85 °C/W Ma x. ABSOLUTE MAXIMUM RATINGS Symbol VS Parameter Value Operating Supply Voltage T amb Operating Ambient Temperature Tstg Storage Temperature Range Unit 11 V -10 to 85 °C -55 to +150 °C QUICK REFERENCE DATA Symbol Parameter Min. Typ. Max. 9 10.5 VS Supply Voltage 7 VCL Max. input signal handling 2 THD Total Harmonic Distortion V = 1Vrms f = 1KHz 0.02 S/N Signal to Noise Ratio V out = 1Vrms (made = OFF) 106 SC Channel Separation f = 1KHz Volume Control Treble Control 1.25dB step (2db step) Bass Control (2db step) Unit V Vrms 0.1 % dB 70 dB -78.75 0 dB -14 +14 dB dB -14 +14 Balance Control 1.25dB step REC-OUT L & R -38.75 0 dB Balance Control 1.25dB step (LOUT, ROUT) -78.75 0 dB Mute Attenuation 90 dB 3/18 TDA7345 ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ, RG = 600Ω, all controls flat (G = 0),Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY VS Supply Voltage 7 9 10.5 V IS Supply Current 20 25 35 mA 60 80 SVR Ripple Rejection LCH / RCH out, Mode = OFF dB INPUT STAGE R II Input Resistance V CL Clipping Level THD = 0.3%; Lin or Rin 35 50 2 2.5 Vrms 3.0 Vrms THD = 0.3%; Rin + Lin (2) C RANGE Control Range 65 19.68 KΩ dB AVMIN Min. Attenuation -1 0 1 dB AVMAX Max. Attenuation 18.68 19.68 20.68 dB ASTEP Step Resolution 0.11 0.31 0.51 dB -3 0 3 mV 70 75 VDC DC Steps adjacent att. step VOLUME CONTROL C RANGE Control Range AVMIN Min. Attenuation -1 0 AVMAX Max. Attenuation 70 75 ASTEP Step Resolution Av = 0 to -40dB 0.5 EA Attenuation Set Error Av = 0 to -20dB Av = -20 to -60dB -1.5 -3 ET Tracking Error VDC DC Steps adjacent attenuation steps dB 1 dB 1.25 1.75 dB 0 1.5 2 dB dB 2 dB dB -3 0 3 mV BASS CONTROL (1) Gb BSTEP RB Control Range +11.5 +14.0 +16.0 dB Step Resolution Max. Boost/cut 1 2 3 dB Internal Feedback Resistance 32 44 56 KΩ +13 +14 +15 dB 1 2 3 dB -6 dB 1 1.5 dB TREBLE CONTROL (1) Gt TSTEP Control Range Step Resolution Max. Boost/cut EFFECT CONTROL C RANGE SSTEP 4/18 Control Range - 21 Step Resolution 0.5 TDA7345 ELECTRICAL CHARACTERISTICS (continued) SURROUND SOUND MATRIX Symbol Parameter Test Condition Min. Typ. Max. Unit GOFF In-phase Gain (OFF) Mode OFF, Input signal of 1kHz, 1.4 Vp-p, Rin → Rout Lin → Lout -1.5 0 1.5 dB D GOFF LR In-phase Gain Difference (OFF) Mode OFF, Input signal of 1kHz, 1.4 Vp-p (Rin → Rout), (Lin → Lout) -1.5 0 1.5 dB GMOV1 In-phase Gain (Movie 1) Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p R in → Rout, Lin → Lout 7 dB GMOV2 In-phase Gain (Movie 2) Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p R in → Rout, Lin → Lout 8 dB DGMOV LR In-phase Gain Diffrence (Movie) Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin → Rout) – (Lin → Lout) 0 dB GMUS1 In-phase Gain (Music 1) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin → Rout) – (Lin → Lout) 6 dB GMUS2 In-phase Gain (Music 2) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p R in → Rout, Lin → Lout 7.5 dB D GMUS LR In-phase Gain Difference (Music) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin → Rout) – (Lin → Lout) 0 dB L MON1 Simulated L Output 1 Simulated Mode, EffectCtrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin → Lou t 4.5 dB LMON2 Simulated L Output 2 Simulated Mode, EffectCtrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin → Lou t – 4.0 dB LMON3 Simulated L Output 3 Simulated Mode, EffectCtrl = -6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin → Lou t 7.0 dB R MON1 Simulated R Output 1 Simulated Mode, EffectCtrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin →R out – 4.5 dB R MON2 Simulated R Output 2 Simulated Mode, EffectCtrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin →R out 3.8 dB R MON3 Simulated R Output 3 Simulated Mode, EffectCtrl = -6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin → Rout – 20 dB RLP1 Low Pass Filter Resistance 7.5 10 12.5 RPS1 Phase Shifter 1 Resistance 13.5 17.95 22.5 KΩ kΩ RPS2 Phase Shifter 2 Resistance 0.30 0.40 0.50 KΩ RPS3 Phase Shifter 3 Resistance 13.6 18.08 22.6 KΩ RPS2 Phase Shifter 4 Resistance 13.6 18.08 22.6 KΩ R HPI High Pass Filter Resistance 45 60 75 KΩ RLPF LP Pin Impedance 7.5 10 12.5 KΩ 5/18 TDA7345 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit SPEAKER ATTENUATORS (REC_OUT_L, REC_OUT_R) Crange Control Range 35 37.5 40 dB SSTEP Step Resolution 0.5 1.25 1.75 dB Attenuation set error -1.5 Output Mute Attenuation 80 90 adjacent att. steps -3 0 EA AMUTE VDC DC Steps 1.5 dB dB 3 mV SPEAKER ATTENUATORS (LOUT, ROUT) Crange Control Range 70 75 SSTEP Step Resolution Av = 0 to -40dB 0.5 1.25 1.75 dB EA Attenuation set error Av = 0 to 20dB -1.5 0 1.5 dB Av = -20 to -60dB -3 0 2 dB VDC DC Steps adjacent att. steps -3 0 3 mV 80 90 AMUTE Output Mute Attenuation dB dB AUDIO OUTPUTS (LOUT, ROUT, REC_OUT_L, REC_OUT_R) VOCL Clipping Level 2 2.5 ROUT Output resistance d = 0.3% 100 200 300 Vrms Ω VOUT DC Voltage Level 4.2 4.5 4.8 V 8 8 15 15 µVrms µVrms GENERAL NO(OFF) Output Noise (OFF) BW = 20Hz to 20KHz Output LOUT, ROUT, Output: REC-OUT-L, REC-OUT-R NO(MOV) Output Noise (Movie) Mode =Movie , BW = 20Hz to 20KHz Rout and Lout measurement 30 µVrms NO(MUS) Output Noise (Music) Mode = Music , BW = 20Hz to 20KHz, Rout and Lout measurement 30 µVrms N O(MON) Output Noise (Simulated) Mode = Simulated, BW = 20Hz to 20KHz Rout and Lout measurement 30 µVrms d Distorsion Av = 0 ; Vin = 1Vrms SC Channel Separation 0.02 60 0.1 70 % dB BUS INPUTS V IL Input Low Voltage VIH Input High Voltage 3 IIN Input Current -5 VO Output Voltage SDA Acknowledge IO = 1.6mA Note: (1) Bass and Treble response: The center frequency and the resonance quality can be choosen by the external circuitry. A standard first order bass response can be realized by a standard feedback network. (2) The peack voltage of the two input signals must be less then (Lin + Rin) peak • AVin < 6/18 VS 2 VS : 2 1 V +5 µA 0.8 V V 0.4 TDA7345 I2C BUS INTERFACE Data transmission from microprocessor to the TDA7345 and viceversa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an ac- knowledge bit. The MSB is transferred first. Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. Figure 3: Data Validity on the I2CBUS Figure 4: Timing Diagram of I2CBUS Figure 5: Acknowledge on the I2CBUS 7/18 TDA7345 the end of each transmitted byte. A subaddress (function) bytes (identified by the MSB = 0) A sequence of dates and subaddresses (N bytes + achnowledge. The dates are identified by MSB = 1, subaddresses by MSB = 0) A stop condition (P) SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte, containing the TDA7345 address (the 8th bit of the byte must be 0). The TDA7345 must always acknowledge at TDA7345 ADDRESS MSB S 1 LSB 0 0 0 0 0 1 0 MSB ACK LSB DATA MSB ACK LSB DATA ACK S D94AU194 Data Transferred (N-bytes + Acknowledge) ACK = Achnowledge S = Start P = Stop INTERFACE FEATURES - Due to the fact that the MSB is used to select if the byte transmitted is a subaddress (function) or a data (value), between a start and stop condition, is possible to receive, how many subaddresses and datas as wanted. - The subaddress (function) is fixed until a new subaddress is transmitted, so the TDA7345 can receive how many data as wanted for the selected subaddress (without the need for a new start condition) - If TDA7345 receives a subaddress with the LSB = 1 the incremental bus is selected, so it enters in a loop condition that means that every acknowledge will increase automatically the subaddress (function) and it receives the data related to the new subaddress. chip address, a subaddress with the LSB = 0 (no incremental bus), N-datas (all these datas concern the subaddress selected), a new subaddress, N-data, a stop condition. So it can receive in a single transmission how many subaddress are necessary, and for each subaddress how many data are necessary. 2) INCREMENTAL BUS TDA7345 receives a start condition, the correct chip address a subaddress with the LSB = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress. The first data that it receives doesn’t concern the subaddress sended but the next one, the second one concerns the subaddress sended plus two in the loop etc, and at the end it receives the stop condition. In the pictures there are some examples: S = start ACK = acknowledge 1) NO INCREMENTAL BUS B = 1 incremental bus, B = 0 no incremental bus TDA7345 receives a start condition, the correct P = stop 1) one subaddress, with n data concerning that subaddress (no incremental bus) EXAMPLES CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 D94AU195 8/18 0 0 1 0 DATA 1 ... DATA n MSB ACK 0 A0 A1 A2 A3 X LSB X 0 MSB ACK 1 LSB DATA ACK P TDA7345 2) one subaddress, (with incremental bus) , with n data (data1 that concerns subaddress +1, data 2 that concerns subaddress + 2 etc.) CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 0 0 1 0 DATA 1 ... DATA n MSB ACK LSB 0 A0 A1 A2 A3 X X MSB 1 ACK LSB 1 DATA ACK P D94AU196 3) more subaddress with more data CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 0 0 1 0 DATA 1 ... DATA n MSB ACK LSB 0 A0 A1 A2 A3 X X 0 MSB ACK 1 SUBADDRESS LSB DATA DATA 1 ... DATA n MSB ACK LSB 0 A0 A1 A2 A3 X X 0 MSB ACK 1 LSB DATA ACK 1 D94AU197 DATA BYTES FUNCTION SELECTION FIRST BYTE (subaddress) The first byte select the function, it is identified by the MSB = 0 MSB LSB SUBADDRESS A0 A1 A2 A3 B 0 0 0 0 X X X B VOLUME ATTENUATION & LOUDNESS 0 1 0 0 X X X B SURROUND & OUT & EFFECT CONTROL 0 0 1 0 X X X B BASS 0 1 1 0 X X X B TREBLE 0 0 0 1 X X X B REC-OUT-R 0 1 0 1 X X X B REC-OUT-L 0 0 1 1 X X X B R OUT 0 1 1 1 0 X X B LOUT 0 1 1 1 1 X X B INPUT STAGE CONTROL B = 1 yes incremental bus; B = 0 no incremental bus; X = indifferent 0,1 9/18 TDA7345 VALUE SELECTION The second byte select the value, it is identified by the MSB = 1 VOLUME ATTENUATION MSB 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LSB 1.25 dB STEPS 0 1 0 1 0 1 0 1 0 -1.25 -2.50 -3.75 -5.00 -6.25 -7.50 -8.75 10 dB STEPS 0 -10 -20 -30 -40 -50 -60 -70 LSB 1.25 dB STEPS 0 1 0 1 0 1 0 1 0 -1.25 -2.50 -3.75 -5.00 -6.25 -7.50 -8.75 10 dB STEPS 0 -10 -20 -30 -40 -50 -60 -70 MUTE OFF ON 0 1 0 1 0 1 0 1 ATT SPEAKER L AND R MSB 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10/18 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 TDA7345 ATT REC-OUT L AND R MSB LSB 1.25 dB STEPS 1 X X 0 0 0 0 1 X X 0 0 1 -1.25 1 X X 0 1 0 -2.50 1 X X 0 1 1 -3.75 1 X X 1 0 0 -5.00 1 X X 1 0 1 -6.25 1 X X 1 1 0 -7.50 1 X X 1 1 1 -8.75 10 dB STEPS 1 X X 0 0 0 1 X X 0 1 -10 1 X X 1 0 -20 1 X X 1 1 1 X X 1 1 -30 1 1 1 MUTE LSB 2 dB STEPS TREBLE/ BASS MSB 1 X X X 0 1 1 1 14 1 X X X 0 1 1 0 12 1 X X X 0 1 0 1 10 1 X X X 0 1 0 0 8 1 X X X 0 0 1 1 6 1 X X X 0 0 1 0 4 1 X X X 0 0 0 1 2 1 X X X 0 0 0 0 0 1 X X X 1 0 0 0 0 1 X X X 1 0 0 1 -2 1 X X X 1 0 1 0 -4 1 X X X 1 0 1 1 -6 1 X X X 1 1 0 0 -8 1 X X X 1 1 0 1 -10 1 X X X 1 1 1 0 -12 1 X X X 1 1 1 1 -14 11/18 TDA7345 SURROUND & OUT & EFFECT CONTROL MSB LSB SELECTION SELECTION SURROUND 1 0 0 SIMULATED 1 0 1 MUSIC 1 1 0 MOVIE 1 1 1 OFF SELECTION EFFECT CONTROL 1 0 0 0 0 -6 1 0 0 0 1 -7 1 0 0 1 0 -8 1 0 0 1 1 -9 1 0 1 0 0 -10 1 0 1 0 1 -11 1 0 1 1 0 -12 1 0 1 1 1 -13 1 1 0 0 0 -14 1 1 0 0 1 -15 1 1 0 1 0 -16 1 1 0 1 1 -17 1 1 1 0 0 -18 1 1 1 0 1 -19 1 1 1 1 0 -20 1 1 1 1 1 -21 For example to select the music mode, out fix, effect control =-9dB: 1 00 1 1 1 0 1 12/18 TDA7345 INPUT CONTROL RANGE (0 TO -19.68dB) MSB LSB 0.3125 dB STEPS 1 X 0 0 0 0 1 Xx 0 0 1 -0.3125 1 X 0 1 0 -0.625 1 X 0 1 1 -0.9375 1 X 1 0 0 -1.25 1 X 1 0 1 -1.5625 1 X 1 1 0 -1.875 1 X 1 1 1 -2.1875 1 X 0 0 0 0 1 X 0 0 1 -2.5 1 X 0 1 0 -5.0 1 X 0 1 1 -7.5 1 X 1 0 0 -10 1 X 1 0 1 -12.5 1 X 1 1 0 -15 1 X 1 1 1 -17.5 2.5 dB STEPS POWER ON RESET VOLUME ATTENUATION MAX ATTENUATION, TREBLE -14dB BASS -14dB SURROUND + EFFECT CONTROL OFF + MAX ATTENUATION ATT SPEAKER R MUTE ATT SPEAKER L MUTE ATT REC-OUT L MUTE ATT REC-OUT R MUTE 13/18 TDA7345 PIN: HP1 PIN: HP2 LP1 VS VS 10K 20µA 5.5K 60K HP2 60K GND HP1 GND 5.5K D94AU199 D94AU198 PIN: BASS - LA, BASS - RA PIN: Lin, Rin VS VS 20µA 20µA 50K GND VREF BASS-LB D94AU200 GND 48K BASS-RB PIN: BASS - LB, BASS - RB D94AU201 PIN: TREBLE - L, TREBLE - R VS VS 20µA GND 48K 25K BASS-LA BASS-RA 14/18 20µA D94AU202 D94AU203 TDA7345 PIN: LOUT, ROUT, REC-OUT-1 REC-OUT-R PIN: SCL, SDA VS 20µA 20µA 100Ω D94AU205 D94AU204 PIN: LP PIN: PS3, PS2 VS VS 20µA 20µA 10K 18.08K PS3A GND PS4A D94AU206 D94AU207 PIN: CREF PIN: PS2 VS VS 20µA 50K 20µA 398Ω 50K PS2A D94AU208 D94AU209 15/18 TDA7345 PIN: PS1 PIN: LP1 VS VS 20µA 20µA 17.95K 10K PS1A HP1 D94AU211 D94AU210 PIN: REAR OUT PIN: REAR IN VS VS 20µA 20µA 20K 20K D94AU214 16/18 D94AU215 TDA7345 mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 2.65 MAX. 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 c1 0.020 45° (typ.) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 S OUTLINE AND MECHANICAL DATA SO28 8 ° (max.) 17/18 TDA7345 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 18/18