STMICROELECTRONICS TDA7421

TDA7421
®
AM/FM TUNER FOR CAR RADIO
AND Hi-Fi APPLICATIONS
FRONT-END FOR AM/FM RECEIVERS
UP-CONVERSION ARCHITECTURE FOR AM
HIGH SPEED PLL WITH INLOCK DETECTOR
FOR OPTIMIZED RDS APPLICATIONS
SINGLE FREQUENCY REFERENCE FOR AM/FM
AM/FM STATION DETECTOR
µP-CONTROLLED COMPENSATION OF EXTERNAL COMPONENTS SPREAD
ADJUSTABLE AUDIO MUTE
FULLY PROGRAMMABLE BY I2C BUS
ADVANCED BICMOS TECHNOLOGY
TQFP64
ORDERING NUMBER: TDA7421
GENERAL DESCRIPTION
The TDA7421 is a high performance tuner circuit
that integrates AM/FM sections, IF counter and
PLL synthesizer on a single chip.
Use of BICMOS technology allows the implementation of tuning functions with a minimum of external components.
Value spread of external components can be fully
compensated by means of on-chip electrical adjustment controlled by external µP.
The Automatic Gain Control (AGC) operates on
different sensitivities and bandwidths in order to
improve sensitivity and dynamic range. I2C bus
allows to control selected functions of the tuner
(AGC and amplifiers gain, PLL and counters operation modes).
FM IF AMP2 IN -
FM IF AMP2 IN +
FM IF AMP1 OUT
FM IF AMP1 IN -
FM IF AMP1 IN +
AM MIX2 OUT -
AM MIX2 OUT +
RF VCC
AM MIX2 IN-
AM MIX2 IN +
FM IF AGC IN
MIX OUT -
MIX OUT +
AM AGC1 TC
AM AGC1 RF AMP
AM AGC1 PIN
PINS CONNECTION
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AM MIX1 IN -
1
48
FM IF AMP2 OUT
AM MIX1 IN +
2
47
IF1 VCC
FM MIX IN -
3
46
FM LIM IN +
FM MIX IN +
4
45
FM LIM IN -
FM RF AGC IN
5
44
IF1 GND
FM AGC OUT
6
43
FM BW TC
RF GND
7
42
VCO B
8
41
VCO E
9
40
FM MUTE DRIVE
FM SMETER AM SMETER
FM DET ADJ
FM SD AM SD
OSC GND
10
39
AUDIO OUT
XTAL D
11
38
FM QUAD+
XTAL G
12
37
FM QUAD-
OSC VCC
13
36
IF2 VCC
FM ANT ADJ
14
35
AM IF2 IN
FM RF ADJ
15
34
AM REF
PLL VCC
16
33
AM BPF
June 1998
AM DET
AM AGC2 TC
IF2 GND
DIG GND
IFC SSTOP AM
STEREO OUT
CLN GND
DIG VDD
SCL
SDA
SLEEP
PLL GND
PLL VREF
LP IN3
LP IN2
LP IN1
LP OUT
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D96AU546A
1/38
SDA
SCL
SLEEP
AGC1 ANT
AM AGC1 RF AMP OUT
AM MIX
IN+
AM MIX IN-
XTALD
XTALG
VCOB
VCOE
FM MIX
IN-
FM MIX
IN+
FM RF AGC IN
MIX OUTI2C
BUS
÷
FILTER
ADJ.
MIX OUT+
VCO
FM AGC OUT
FM IF
AGC IN
FM
AGC
FM IF
AMP1 INAM RF AGC
10.25MHz
OSC
÷
AM
MIX2 IN+
FILTER
ADJ.
÷
PHASE
COMPARATOR
FM IF
AMP2 IN+
AM MIX2
OUT+
FM IF
AMP1 IN+
AM
AGCI TC
FM IF
AMP2 INAM MIX2
OUT-
LOCK
DET
FM IF
AMP2 OUT
AM IF2
IN
LIM IN+
CHARGE
PUMP
-
S METER
LIMITER
FM IF
COUNTER
AM IF
COUNT
AM IF
FILTER
ADJ.
QUAD-
ADJACENT
CH. DET.
QUADRATURE
DETECTOR
QUAD+
AM
IFREF
2/38
AM BPF
IFC SSTOP
AM STEREO OUT
AM
DETECTOR
AM IF
AGC
+
ADJACENT
CH. MUTE
SOFT
MUTE
DETUNING
MUTE
AM
SMETER
TRIPLE
OUT
4 BIT DAC
AM AGC2
TC
+
DETUNING
DETECTOR
SLIDER
AM DET
FM MUTE
FM
AM
÷
D96AU540A
+
AM SD
FM SD
AM IF
COUNTER
4 BIT DAC
STOP
STATION
PLL GND
PLL VREF
PLL VCC
LPOUT
FM RF ADJ
FM ANT ADJ
LPIN3
LPIN1
LPIN2
BW TC
AM SD/
FM SD
AM SMETER
FM SMETER
FM DET ADJ OUT
AUDIO OUT
TDA7421
BLOCK DIAGRAM
LIM IN-
AM MIX2
IN-
FM IF
AMP1 OUT
TDA7421
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
-40 to 85
-55 to 150
°C
°C
Tamb
Tstg
VCC
Operating Temperature Range
Storage Temperature Range
Analog Supply Voltages (PLL, RF, IF1, IF2, OSC)
10.2
V
VDD
Digital Supply Voltage
5.5
V
THERMAL DATA
Symbol
Parameter
Rth j-amb
Thermal resistance Junction-Ambient
Value
Unit
68
°C/W
typ.
PIN DESCRIPTION
N.
Name
Function
1
2
AM MIX1 IN AM MIX1 IN +
3
FM MIX IN -
Input "-" to the FM mixer (differential input)
4
5
6
FM MIX IN +
FM RF AGC IN
FM AGC OUT
Input "+" to the FM mixer (differential input)
Input to the RF AGC circuit
Voltage output to the FM AGC
7
8
RF GND
VCO B
Input "-" to the AM 1st mixer (differential input)
Input "+" to the AM 1st mixer (differential input)
RF circuits ground
Local oscillator input to the transistor base (two-pin oscillator)
9
VCO E
10
11
12
OSC GND
XTAL D
XTAL G
Local oscillator input to the transistor emitter (two-pin oscillator)
13
14
15
OSC VCC
FM ANT ADJ
FM RF ADJ
16
17
18
PLL VCC
LP OUT
LP IN1
PLL positive supply
Op Amp output to PLL loop filters
PLL "N. 1" loop filter connection to Op Amp inverting input
19
20
21
22
LP IN2
LP IN3
PLL VREF
PLL GND
PLL "N. 2" loop filter connection to Op Amp inverting input
PLL "N. 3" loop filter connection to Op Amp inverting input
Voltage reference to Op Amp noninverting input
PLL ground
23
24
SLEEP
SDA
25
SCL
Oscillator ground
Crystal oscillator input to MOS drain (two-pin oscillator)
Crystal oscillator input to MOS gate (two-pin oscillator)
Oscillator positive supply
Tuning varicap voltage for antenna FM filter
Tuning varicap voltage for RF FM filter
I2C bus disconnect signal
I2C bus data
I2C bus clock
3/38
TDA7421
PIN DESCRIPTION (continued)
N.
Name
27
DIG GND
Function
28(*)
IFC SSTOP
AM STEREO OUT
29
30
CLN GND
IF2 GND
31
AM AGC2 TC
32
AM DET
Connection to the capacitor of the AM diode-capacitor detector
33
34
AM BPF
AM REF
Connection to the AM IF filter
Reference voltage of AM IF amplifier
35
36
AM IF2 in
IF2 VCC
Input (single ended) of AM 2nd IF amplifier
IF 2nd positive supply
Digital circuits ground
Search stop signal or
Output (single ended) of AM IF amplifier
"Clean" ground
IF 2nd ground
AM 2nd AGC time constant
37
FM QUOD -
"-" Insertion pt. of FM quadrature network (differential)
38
FM QUAD +
"+" Insertion pt. of FM quadrature network (differential)
39
AUDIO OUT
Audio frequency output (single ended)
40 (*)
FM SD
AM SD
41(*)
42
FM SMETER
AM SMETER
FM DET ADJ
FM MUTE DRIVE
43
FM BW TC
FM detuning detector time constant
44
45
IF1 GND
FM LIM IN -
IF 1st ground
Input "-" of FM limiter (differential input)
46
47
48
FM LIM IN +
IF1 VCC
FM IF AMP2 OUT
Input "+" of FM limiter (differential input)
IF 1st positive supply
Output (single ended) of the FM IF 2nd amplifier buffer
49
50
51
FM IF AMP2 IN FM IF AMP2 IN +
FM IF AMP1 OUT
Input "-" of the FM IF 2nd amplifier (differential input)
Input "+" of the FM IF 2nd amplifier (differential input)
Output (single ended) of the FM IF 1st amplifier buffer
52
53
54
FM IF AMP1 IN FM IF AMP1 IN +
AM MIX2 OUT -
Input "-" of the FM IF 1st amplifier (differential input)
Input "+" of the FM IF 1st amplifier (differential input)
Output "-" of the AM 2nd mixer (differential output)
55
56
57
58
AM MIX2 OUT +
RF VCC
AM MIX2 IN AM MIX2 IN +
Output "+" of the AM 2nd mixer (differential output)
RF stage positive supply
Input "-" to the AM 2nd mixer (differential input)
Input "+" to the AM 2nd mixer (differential input)
59
60
FM IF AGC IN
MIX OUT -
61
62
63
64
MIX OUT +
AM AGC1 TC
AM AGC1 RF AMP
AM AGC1 PIN
FM Station detector output or
AM Station detector output
FM S-meter output or
AM S-meter output or
FM detuning adjustment
FM mute time constant
Input FM IF AGC circuit
Output "-" of the FM/AM 1st mixer (differential output)
Output "+" of the FM/AM 1st mixer (differential output)
AM 1st AGC time constant
Voltage output of the AM 1st AGC, to the transistor of the RF AF amplifier
Current output of the AM 1st AGC, to the PIN diodes antenna AM attenuator
(*) Pin function is user-defined by software.
4/38
TDA7421
ELECTRICAL CHARACTERISTICS
DC PARAMETERS (Tamb = 25°C; Vcc = 8.5V, Vdd = 5V unless otherwise specified)
Symbol
Parameter
DIG Vdd
Digital Supply Voltage
DIG Idd
Digital Supply Current
PLL VCC
PLL Supply Voltage
PLL ICC
PLL Supply Current
RF VCC
RFSupply Voltage
RF ICC
RF Supply Current
IF1 VCC
IF1 Supply Voltage
IF1 ICC
IF1 Supply Current
IF2 VCC
IF2 ICC
IF2 Supply Voltage
IF2 Supply Current
Test Condition
Min.
Typ.
4.75
Max.
Unit
5.25
V
AM MODE
4.0
4.6
5.2
mA
FM MODE
3.5
7.5
4.0
4.5
10
mA
V
AM MODE
1.2
1.6
2.0
mA
FM MODE
2.5
7.5
3.0
3.5
10
mA
V
AM MODE
15.0
17.5
20.0
mA
FM MODE
10.0
7.5
13.0
16.0
10
mA
V
AM MODE
2.2
2.7
3.2
mA
FM MODE
16.0
7.5
19.5
23.0
10
mA
V
AM MODE
8.5
10.5
12.5
mA
FM MODE
27.0
7.5
32.0
37.0
10
mA
V
OSC VCC
Oscillator Supply Voltage
OSC ICC
Oscillator Supply Current
AM MODE
FM MODE
14.5
11.0
17.0
14.0
19.5
17.0
mA
mA
Total Supply Current
AM MODE
FM MODE
45.0
73.0
50.0
81.0
55.0
89.0
mA
mA
Min.
Typ.
Max.
Uni
80.9
55
98.2
65.4
MHz
MHz
TOTAL ICC
AC PARAMETERS
Ref: FM Test Circuit measure Vosc with high impedance FET probe
Voltage Controlled Oscillator (VCO)
Symbol
Parameter
Test Condition
fVCOmin
Minimum VCO Frequency
Vturn = 0, Europe/USA
Japan
fVCOmax
Maximum VCO Frequency
Vturn = VCC, Europe/USA
Japan
Oscillator Amplitude
fosc = 108.8MHz, Europe/USA
fOSC = 72.3MHz, Japan
VOSC
123.2
79.2
128
90
MHz
MHz
106
dBu
Reference Oscillator
Ref: AM Test Circuit measure VXTAL with high impedance FET probe
Symbol
fXTAL
VXTAL
Parameter
Reference Frequency
Oscillator Amplitude
Test Condition
Min.
Typ.
10.25
108
Max.
Uni
MHz
dBu
5/38
TDA7421
ELECTRICAL CHARACTERISTICS (continued)
FM Section Global Performances
Refer to Evaluation Circuit and enclosed curves (S+N/N, THD)
- RF Input: fc = 98.1MHz, 75KHz dev., 1KHz mod.,60dBu
- Audio Output: BPF 20Hz - 20KHz
Symbol
S+N/N
THD
VO AF
US
AGCrange
Parameter
Test Condition
Min.
Signal to Noise Ratio
Typ.
Max.
68
Total Harmonic Distortion
Audio Output Level
deviation = 40KHz
Usable Sensitivity
antenna level at which
S+N/N=30dB
350
Range AGC FM
0.3
400
Uni
dB
450
4
%
mVRMS
dBu
65
dB
FM Front-end Electrical Adjustments
Ref: FM Test Circuit measure VANTADJ and VRFADJ referred to VPLLOUT
Symbol
ANTADJ
MAX OFF
ANTADJ
STEP OFF
RFADJ
MAX OFF
RFADJ
STEP OFF
Min.
Typ.
Max.
Uni
Maximum FM Antenna Filter
Adjustment Voltage Offset
Parameter
VPLLOUT = 2.5V, ANA3-0 set to
1111
Test Condition
21
25
27
%
FM Antenna Filter Adjustment
Voltage Offset Step
VPLLOUT = 2.5V, ANA3-0 set to
1001
2.8
3.6
4.4
%
Maximum FM RF Filter
Adjustment Voltage Offset
VPLLOUT = 2.5V, RFA3-0 set to
1111
21
25
27
%
FM RF Filter Adjustment Voltage
Offset Step
VPLLOUT = 2.5V, RFA3-0 set to
1001
2.8
3.6
4.4
%
Min.
Typ.
Max.
Unit
FM Mixer
Ref: FM Test Circuit, measure input at VMIXFMIN, output at VMIXOUT
Symbol
ZIN,MIX
GMIX
Parameter
Single-ended input impedance
(pin 3, pin4)
Test Condition
f = 100MHz
Ω
12
Conversion Gain
3rd order intermodulation
distortion intercept point
fIN = 98.1MHz
21.8
dB
IP3MIX
fd = 98.1MHz; fu1 = 98.2MHz;
fu2 = 98.3MHz;
104
dBu
CP1MIX
1dB compression point
fIN = 98.1MHz
90
dBu
FM AGC
Ref: FM Test Circuit, measure input at VFMRFAGCIN, and VFMIFAGCIN, output at VFMAGCOUT
Symbol
Parameter
VRFAGCSTART
Open Loop Rf Agc Starting Point
RINRFAGC
VIFAGCSTART
Input Resistance
Open Loop If Agc Starting Point
RINIFAGC
ROUTFMAGC
6/38
Input Resistance
Output Resistance
Test Condition
Min.
Typ.
Max.
Unit
fRFAGCIN = 98.1MHz Value of
VFMRFAGCIN, at which
VFMAGCOUT = 4V
74
80
86
dBu
fIFAGCIN = 10.7MHz Value of
VFMIFAGCIN, at which
VFMAGCOUT = 4V
FAGC2-0 set to 111
71
77
83
dBu
20
20
10
KΩ
KΩ
KΩ
TDA7421
ELECTRICAL CHARACTERISTICS (continued)
FM IF Amplifier 1
Ref: FM Test Circuit, measure input at VFMAMP1IN, output at VFMAMP1OUT
Symbol
RIN,AMP1
ROUT,AMP1
GTYP,AMP1
Parameter
Input Resistance
Output Resistance
Typical Gain
GMIN,AMP1
Minimum Gain
GMAX,AMP1
Maximum Gain
IP3AMP1
CP1AMP1
3rd Order Intermodulation
Distortion Intercept Point
1dB Compression Point
Test Condition
f = 10.7MHz
f = 10.7MHz
fIN = 10.7MHz, FBH3-0 set to
0100
fIN = 10.7MHz, FBH3-0 set to
0001
fIN = 10.7MHz, FBH3-0 set to
0000
fd = 10.7MHz; fu1= 10.8MHz; fu2=
10.9MHz, FBH3-0 set to 0100
fIN = 10.7MHz; FBH3-0 set to
0100
Min.
Max.
16.5
Typ.
330
330
17.5
18.5
Unit
Ω
Ω
dB
14.5
15.5
16.5
dB
18.5
19.5
20.5
dB
109
dBu
96
dBu
FM IF Amplifier 2
Ref: FM Test Circuit, measure input at VFMAMP2IN, output at VFMAMP2OUT
Symbol
RIN,AMP2
ROUT,AMP2
GTYP,AMP2
GMIN,AMP2
GMAX,AMP2
IP3AMP2
CP1AMP2
Parameter
Input Resistance
Output Resistance
Typical Gain
Minimum Gain
Maximum Gain
3rd Order Intermodulation
Distortion Intercept Point
1dB Compression Point
Test Condition
f = 10.7MHz
f = 10.7MHz
fIN = 10.7MHz, FBL3-0 set to 0100
fIN = 10.7MHz, FBL3-0 set to 0001
fIN = 10.7MHz, FBL3-0 set to 0000
fd = 10.7MHz; fu1= 10.8MHz; fu2=
10.9MHz, FBL3-0 set to 0100
fIN = 10.7MHz; FBL3-0 set to 0100
Min.
5
3
7
Typ.
330
330
6
4
8
122
Max.
7
5
9
110
Unit
Ω
Ω
dB
dB
dB
dBu
dBu
FM Limiter, Field Strengh Meter and Demodulator
Ref: FM Test circuit, measure:
- Input at VFMLIMIN, fIN = 10.7MHz
- filtered FS Meter output at VSM,FILT
- shifted FS Meter output at VSM,SHIFT (FMADJ set to 0)
- demodulator adjustment output at VSM,SHIFT (FMADJ set to 1)
Symbol
RIN,LIM
GLIM
LS
SM1
SM2
SM3
SMMINSHIFT
SMMAXSHIFT
GDEM
GDEMADJ
Parameter
Limiter Input Resistance
Limiter Gain
Limiting Sensitivity
Smeter 1 at VSM,FILT
Smeter 2 at VSM,FILT
Smeter 3 at VSM,FILT
Smeter Minimum Shift Voltage at
VSM,SHIFT referred to VSM,FILT
Smeter Maximum Shift Voltage
at VSM,SHIFT referred to VSM,FILT
Demodulator Conversion Gain
Test Condition
VFMLIMIN =
VFMLIMIN =
VFMLIMIN =
VFMLIMIN =
00000
VFMLIMIN =
11111
VFMLIMIN >
Demodulator Adjustment
Conversion Gain
VFMLIMIN > LS, measured at
VSMSHIFT, FMADJ set to 1
Min.
42dBu
77dBu
102dBu
70dBu, FSL4-0 set to
0.1(1)
2.4(1)
4.0(1)
0.25
Typ.
330
90
23
0.25
2.75
4.35
0.3
70dBu, FSL4-0 set to
1.55
1.8
LS
2
14
Max.
0.5(1)
3.1(1)
4.7(1)
0.35
Unit
Ω
dB
dBu
V
V
V
V
2.05
V
mVRMS/
KHz
mVRMS/
KHz
NOTE1: Refer to Global application circuit; input at first Ceramic Filter in, FBH3-0 set to 0001, FBL3-0 set to 0001
7/38
TDA7421
ELECTRICAL CHARACTERISTICS (continued)
FM Audio Amplifier
Ref: FM Test circuit, measure:
- Input at VFMLIMIN, = 95dBu, fIN = 10.7MHz
- audio output at VAUDIO, BPF 20Hz to 20KHz
- muting voltage at VMUTE, DRIVE
Symbol
VMUTE
VPLAY
Parameter
Mute Voltage
Play Voltage
VAF
Audio Amplifier Gain in Play
Conditions
Audio Amplifier Highest Gain in
Mute Condition
Audio Amplifier Lowest Gain in
Mute Condition
AF Output Level
THD
AFTotal Harmonic distortion
GAMP,PLAY
GAMP,MUTEMAX
GAMP,MUTEMIN
S+N/N
AMR
AUDIOcurr
MUTE Rout
AF Signal to Noise Ratio
Amplitude Modulation Rejection
Test Condition
VMUTE,DRIVE for which ∆VAF = 29dB, FMHIGH set to 0, AUM2-0
set to 111
VMUTE,DRIVE for which ∆VAF = 1dB, FMHIGH set to 0, AUM2-0
set to 111
VMUTE,DRIVE < VPLAY
VMUTE,DRIVE > VMUTE, FMHIGH
set to 1, AUM2-0 set to 001
VMUTE,DRIVE > VMUTE, FMHIGH
set to 0, AUM2-0 set to 111
fDEV = 75KHz, FMOD = 1KHz,
VMUTE,DRIVE < VMUTE
fDEV = 75KHz, FMOD = 1KHz,
VMUTE,DRIVE < VMUTE
fDEV = 75KHz, FMOD = 1KHz,
VMUTE,DRIVE < VMUTE
AM modulation deph 30%, f MOD =
1KHz, with respect to FM
modulated signal with fDEV =
40KHz, VMUTE,DRIVE < VMUTE
Audio Out Current Capability
Mute Drive Output Resistance
Min.
2
350(1)
Typ.
Max.
Unit
V
0.3
V
9
dB
6.5
dB
-21
dB
400
450(1) mVRMS
0.5
%
68(1)
75
%
60(1)
67
dB
1
mA
KΩ
5
NOTE1: Refer to Global application circuit; input at first Ceramic Filter in, FBH3-0 set to 0001, FBL3-0 set to 0001
FM QUALITY DETECTORS
Field Strength Detector
Ref: FM Test Circuit, measure:
- Input at VFMLIMIN, fIN = 10.7MHz, CW
- output at VMUTE,DRIVE
Symbol
FSDMIN
Parameter
Field Strenght Detector Minimum
Threshold
FSDMAX
Field Strenght Detector Maximum
8/38
Test Condition
VFMLIMIN level at which
VMUTE,DRIVE = VMUTE, FSM3-0 set
to 0000
VFMLIMIN level at which
VMUTE,DRIVE = VMUTE, FSM3-0 set
to 1111
Min.
Typ.
40
60
Max.
Unit
dBu
dBu
TDA7421
ELECTRICAL CHARACTERISTICS (continued)
Detuning Detector
Ref: FM Test Circuit, measure:
- Inputs at VFMLIMIN, CW
- output at VMUTE,DRIVE
Symbol
DDSTART
DDSLOPE,MIN
Parameter
Detuning Detector Starting Point
Detuning Detector Minimum
Muting Slope
DDSLOPE,MAX Detuning Detector Maximum
Muting Slope
DDTRC
Detuning Detector Time Constant
Ratio
Test Condition
frequency shift from 10.7MHz at
which VMUTE,DRIVE = VPLAY
frequency shift from 10.7MHz +
DDSTART, at which VMUTE,DRIVE =
VMUTE, BWM2-0 set to 100,
FMRECSEEK set to 0
frequency shift from 10.7MHz +
DDSTART, at which VMUTE,DRIVE =
VMUTE, BWM2-0 set to 001,
FMRECSEEK set to 0
ratio of "reception" mode
integration time constant inside the
Detuning Detector with respect to
"seek" mode
Min.
Typ.
±23
Max.
Unit
KHz
22.5
30
37.5
KHz
7.5
10
12.5
KHz
34/6
s/s
Adjacent Channel Detector
Ref: FM Test Circuit, measure:
- Inputs at VFMLIMIN: desired 10.7MHz, 95dBu CW; undesired 10.8MHz CW
- output at VMUTE,DRIVE
- BWM2-0 set to 001
Symbol
ACDMAX
Parameter
Adjacent Channel Quality Detector
Maximum Sensitivity Threshold
ACDMIN
Adjacent Channel Quality Detector
Minimum Sensitivity Threshold
Test Condition
amplitude of undesired signal at
which VMUTE,DRIVE = VMUTE,
HDM4-0 set to 11111
amplitude of undesired signal at
which VMUTE,DRIVE = VMUTE,
HDM4-0 set to 00000
Min.
Test Condition
VFMLIMIN level at which
VFMSD = 2.5, FSM4-0 set to 00000
VFMLIMIN level at which
VFMSD = 2.5, FSM4-0 set to 11111
Min.
Test Condition
frequency shift from 10.7MHz at
which VFMSD = 2.5V
Min.
Typ.
91
Max.
94.8
Unit
dBu
dBu
Field Strength Station Detector
Ref: FM Test Circuit, measure:
- Inputs at VFMLIMIN: desired 10.7MHz, CW
- output at VFMSD
- FMRECSEEK set to 1
Symbol
FSSDMIN
FSSDMAX
Parameter
Field Strength Station Detector
Minimum Threshold
Field Strength Station Detector
Maximum Threshold
Typ.
24
Max.
76
Unit
dBu
dBu
Detuning Station Detector
Ref: FM Test Circuit, measure:
- Input at VFMLIMIN, CW;
- output at VFMSD
- FMRECSEEK set to 1
Symbol
DSD
Parameter
Detuning Station Detector
Threshold
Typ.
23
Max.
Unit
KHz
9/38
TDA7421
ELECTRICAL CHARACTERISTICS (continued)
Adjacent Channel Station Detector
Ref: FM Test Circuit, measure:
- Input at VFMLIMIN: desired 10.7MHz, 95dBu CW; undesired 10.8MHz CW
- output at VFMSD
- FMRECSEEK set to 1
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
ACSDMAX
Adjacent Channel Detector
Maximum Sensitivity Threshold
amplitude of undesired signal at
which VFMSD = 2.5V, HDM4-0 set
to 11111
92.5
dBu
ACDMIN
Adjacent Channel Detector
Minimum Sensitivity Threshold
amplitude of undesired signal at
which VFMSD = 2.5V, HDM4-0 set
to 00000
94.9
dBu
AM Section Global Performances
Refer to Evaluation Circuit and enclosed curves (S+N/N, THD)
- RF Input: fc = 1MHz, f mod = 1KHz, m = 0.3;
- Audio Output: BPF 20Hz - 20KHz
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Maximum Sensitivity
VINRF = 74dBu; ∆VAF = - 20dB
20
dBu
Usable Sensitivity
S+N/N = 20dB
31
dBu
AGC Range
VINRF = 74dBu; ∆VAF = -10dB
50
dB
Signal to Noise Ratio
Image Rejection
VINRF = 74dBu
f1 = 1.9MHz
f2 = 22.4MHz
53.0
dB
αTw
Tweet
THD
Total Harmonic Distortion
VINRF = 74dBu; f1 = 900KHz;
f2 = 1350KHz
VINRF = 74dBu; m = 0.3
VIN MIN
VIN US
∆Vis
S+N/N
αIMAG
46.0
dB
1.2
0.45
VINRF = 74dBu; m = 0.8
VINRF = 120dBu; m = 0.3
VAF
VAMST
Audio Output Level
AM IF2 Output level
VINRF = 74dBu
VINRF = 74dBu
dB
1.0
1.73
%
%
137
0.33
167
106
197
%
mVRMS
dBu
Min.
Typ.
Max.
Unit
7.5
1.2
8.5
9.5
KΩ
dB
AM Mixer 1
Ref: AM Test Circuit, measure input at VMIX2AMIN, output at VMIXOUT
Symbol
Parameter
RINMIX1
GMIX1
IP3MIX1
Input Resistance
Conversion Gain
3rd Order Intermodulation
Distortion Intercept Point
CP1MIX1
1dB Compression Point
10/38
Test Condition
fIN = 1MHz
fd = 1MHz; fu1 = 1.1MHz;
fu2 = 1.2MHz;
fIN = 1MHz
115
dBu
98.7
dBu
TDA7421
ELECTRICAL CHARACTERISTICS (continued)
AM Wide & Narrow AGC
Ref: AM Test Circuit, input at VMIX1AMIN, and VMIX2AMIN, output at VAMAGC1AMP, andVAMAGC1PIN
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
VWAGCTYP
Open Loop WIDE AGC Typical
Starting Point
fWAGCIN = 1MHz, AAG3-0 set to
1000; VMIX1AMIN at which
VAMAGC1AMP = 2.5V
91.3
dBu
VWAGCMIN
Open Loop WIDE AGC Minimum
Starting Point
80.6
dBu
VWAGCMAX
Open Loop WIDE AGC Maximum
Starting Point
fWAGCIN = 1MHz, AAG3-0 set to
0000; VMIX1AMIN at which
VAMAGC1AMP = 2.5V
fWAGCIN = 1MHz, AAG3-0 set to
1111; VMIX1AMIN at which
VAMAGC1AMP = 2.5V
95.6
dBu
VNAGCTYP
Open Loop NARROW AGC
Typical Starting Point
fNAGCIN = 10.7MHz, AAG3-0 set
to 1000; VMIX2AMIN at which
VAMAGC1AMP = 2.5V
93.2
dBu
VNAGCMIN
Open Loop NARROW AGC
Minimum Starting Point
fNAGCIN = 10.7MHz, AAG3-0 set
to 0000; VMIX2AMIN at which
VAMAGC1AMP = 2.5V
82.8
dBu
VNAGCMAX
Open Loop NARROW AGC
Maximum Starting Point
fNAGCIN = 10.7MHz, AAG3-0 set
to 1111; VMIX2AMIN at which
VAMAGC1AMP = 2.5V
97.4
dBu
ROUTAMAGC1
IAMAGC1PIN
Output Resistance
Maximum Pin-diode Current
fWAGCIN = 1MHz;
VMIX1AMIN = 90dBu; AAG3-0 set to
0000
23.3
KΩ
1.4
mA
AM Mixer 2
Ref: AM Test Circuit, measure input at VMIX2AMIN, output at VMIX2OUT, (switches must be in position 2 for
AGC measurements).
Symbol
Parameter
RINMIX2
GMIX2
IP3MIX2
Input Resistance
Maximum conversion Gain
3rd Order Intermodulation
Distortion Intercept Point
CP1MIX2
1dB Compression Point
Test Condition
fIN = 10.7MHz
fd = 10.7MHz; fu1 = 10.8MHz;
fu2 = 10.9MHz;
fIN = 10.7MHz
AGCMIXCP
Central Point of AGC2 Intevention
on Mixer 2
fIN = 10.7MHz;
VMIX2AMIN = 52dBu;
Value of VMIX2OUT
AGCMIXSP
AGC2 Starting Point on Mixer 2
AGCMIXR
AGC2 Range on Mixer 2
fIN = 10.7MHz; Value of VMIX2AMIN
for which VMIX2OUT is AGCMIXCP 3dB
fIN = 10.7MHz; Range of
VMIX2AMIN for which VMIX2OUT is
AGCMIXCP ±3dB
Min.
Typ.
Max.
Unit
5
19.6
KΩ
dB
122
dBu
90.7
dBu
61.2
dBu
40
dBu
24
dB
11/38
TDA7421
ELECTRICAL CHARACTERISTICS (continued)
AM IF2 Amplifier
Ref: AM Test Circuit, measure input at VIP2AMPIN, output at VIP2AMPOUT, (switches must be in position 1),
fIN = 450KHz.
Symbol
RIN,IF2AMP
GIF2AMP
AGCAMPCP
AGCAMPSP
Parameter
Input Resistance
Maximum Gain
Central Point of AGC2 Intevention
on IF2 Amp
AGC2 Starting Point on IF2 Amp
AGCAMPR
AGC2 Range on IF2 Amp
AGCTCR
IFAMST
IFAMSTcurr
AGC2 Time Constant Ratio
AM IF2 Output Level at pin 28
Current Capability of pin 28
Test Condition
VIF2AMPIN = 10dBu
VIF2AMPIN = 72dBu; Value of
VIF2AMPOUT
Value of VIF2AMPIN for which
VIF2AMPOUT is AGCAMPCP - 3dB
fIN = 10.7MHz; Range of
VMIX2AMIN = for which VMIX2OUT is
AGCMIXCP ±3dB
Ratio of AGC2 "reception" Time
Constant and "seek" Time Constant
VIF2AMPIN = 72dBu;
AMSTEREO set to 1
AMSTEREO set to 1
Min.
Typ.
2
51
115
Max.
63
dBu
36
dB
150/5
104
Unit
KΩ
dB
dBu
106
s/s
108
dBu
µA
150
AM Field Strength Meter and Field Strength Station Detector
Ref: AM Test Circuit, measure at VMIX2AMIN, outputs at VAMSMETER and at VAMSD (switches in position 2),
- fIN = 10.7KHz.
- AMSEEK set to 1
Symbol
Min.
Typ.
Max
Unit
AMSM1
AMSM2
AM Smeter 1 at VAMSMETER
AM Smeter 2 at VAMSMETER
Parameter
VMIX2AMIN = 35dBu
Test Condition
2.2
2.89
3.6
V
VMIX2AMIN = 65dBu
2.5
3.26
4.0
V
AMSM3
AMSDMIN
AM Smeter 3 at VAMSMETER
Station Detector Minimum
Threshold
VMIX2AMIN = 95dBu
VMIX2AMIN at which VAMSD = 2.5V,
ASS3-0 set to 0000
3.0
3.73
44
4.5
V
dBu
AMSDMAX
Station Detector Maximum
Threshold
VMIX2AMIN at which VAMSD = 2.5V,
ASS3-0 set to 1111
64
dBu
IF Counter Output
Ref: AM & FM Test Circuit, measure at pin 28
Symbol
Parameter
Test Condition
Min.
Typ.
Max
Unit
IFCFM
FM IFC Sensitivity
VFMLIMIN at which Vpin 28 = 2.5V,
FMRECSEEK set to 1, EW2-0 set
to 101, IFS2-0 set to 010
34
dBu
IFCAM
AM IFC Sensitivity
VIF2AMPIN at which Vpin 28 = 2.5V,
AMSEEK set to 1, EW2-0 set to
011, IF2-0 set to 100, AMFM
STBY1-0 set to 10
29
dBu
150
µA
IFCcurrent
12/38
IFC Current Capability
TDA7421
ELECTRICAL CHARACTERISTICS (continued)
Loop Filter Input Output
(LP_IN1, LP_IN2, LP_IN3, LP_OUT)
Symbol
Test Condition
Min.
Typ.
Max.
Unit
-IIN
IIN
Input Leakage Current
Input Leakage Current
Parameter
VIN = GND; PDout = Tristate 1)
VIN = VDD; PDout = Tristate
-2
-2
0
0
2
2
µA
µA
VOL
VOH
Output Voltage Low
IIN = -0.2mA; VCC = 8.5V
0.5
V
Output Voltage High
IOUT = 0.2mA; VCC = 8.5V
8
V
IOUT
Output Current Sink
VPLL = 8.5V;
10
mA
IOUT
Output Current Source
Vout = 0.5 to 8V
10
mA
I2C Bus Interface
Symbol
Parameter
Test Condition
Min.
Typ.
Max
Unit
500
KHz
fSCL
SCL Clock Frequency
100
tAA
SCL Low to SDA Data Valid
300
ns
tbuf
Time the Bus Must Be Free for
the New Transmission
4.7
µs
START Condition hold Time
4.0
µs
tLOW
Clock Low Period
4.7
µs
tHIGH
Clock High Period
4.0
µs
tSU-SDA
Start Condition Setup Time
4.7
µs
tHD-DAT
Data Input Hold Time
0
µs
tSU-DAT
Date Input Setup Time
250
ns
tR
SDA & SCL Rise Time
µs
tF
SDA & SCL Full Time
µs
tHD-STA
Stop Condition Setup Time
4.7
µs
tDH
DATA OUT Time
300
ns
VIL
VIH
Input Low Voltage
Input High Voltage
tSU-STO
1
3
V
V
(1) depends upon filter circuitry
(2) depends upon application circuit
(3) depends only upon IF2 ceramic filter
13/38
TDA7421
AM TEST CIRCUIT
VMiXOUT
2
1
2K
IAMAGC1PIN
VAMAGC1RFAMP
330
64
VMiX2AMIN
T2
T3
VCC
VCC
63
61
60
58
57
55
54
AGC
W&N
1
VMIX1AMIN
2
+
15pF
2
35
2K
34
VIF2AMPIN
1
-
11
1M
VXTAL
AGC2
12
15pF
40
41
VAMSD
VAMSMETER
DET
31
VIF2AMPOUT
33
32
D97AU803A
FM TEST CIRCUIT
10nF
10nF
T1
1:3.5
VMiXFMIN
VFMAMP1OUT
VCC
VTun
3
61
10nF
59
60
53
330
10nF
51
50
330
49
48
330
330
-
-
+
+
46
V1
L2
22pF
15pF
1.8K
8
330
9
45
10nF
VFMLIMIN
10nF
+
68pF
5
VFMRFAGCIN
10nF
VFMAGCOUT
FM AGC
-
5K
10nF
10nF
52
330
VFMAMP2OUT
330
10nF
4
VTun
VFMAMP2IN
VFMIFAGCIN
T2
VFMAMP1IN
VMIXOUT
330
AUDIO
38
DEMOD
6
L6
10nF
37
14
15
16
40
41
VAMTADJ
VRFADJ
VPLLOUT
VFMSD
VSMSHIFT
31
42
39
VAUDIO
VMUTEDRIVE
100K
VSMFILT
10nF
D97AU804A
14/38
TDA7421
FM SECTION
Featuring a single conversion configuration, it
comprises a multi-stage IF limiter whose gain is
I2C controlled and a quadrature demodulator with
detuning and adjacent channel detectors. Signal
meter and stop station functions are also supported
AM SECTION
AM signal is converted by means of UP-DOWN
configuration (IF1 = 10.7MHz, IF2 = 450KHz) and
MW/LW bands are covered.
PLL SECTION
Three operating modes are available:
PM0
PM1
Operating Mode
0
1
0
0
0
1
Standby
AM
not used
1
1
FM
They are user programmable with the mode PM
registers.
Standby mode
It stops all functions. This allows low current consumption without loss of information in all registers. The pin LP-OUT is forced to 0V in power on.
All data registers are set to FE (11111110). The
oscillator runs even in stand-by mode.
FM and AM Operation
The FM or AM signal applies to a 32/33 prescaler, which is controlled by a 5 bit counter (A).
The 5 bit register (PC0 to PC4) controls this divider.
The output of the prescaler connects to a 11 bit
divider (B). The 11 bit register (PC5 to PC15)
controls the divider ’B’.
THREE STATE PHASE COMPARATOR
The phase comparator generates a phase error
signal according to phase difference between
fSYN and fREF. This phase error signal drives the
charge pump current generator.
CHARGE PUMP CURRENT GENERATOR
This stage generates signed pulses of current.
The phase error signal decides the duration and
polarity of those pulses.
The current absolute values are programmable
by A0, A1, A2 registers for high current and B0,
B1 registers for low current.
LOW NOISE CMOS OP-AMP
An internal voltage divider at pin VREF connects
the positive input of the low noise Op-Amp.
The charge pump output connects the negative
input. This internal amplifier in cooperation with
external components can provide an active filter.
The negative input is switchable to three input
pins (LPIN 1, LPIN 2 and LPIN 3), to increase the
flexibility in application.
This feature allows two separate active filters for
different applications.
A logical "1" in the LPIN 1/2 register activates pin
LPIN 1, otherwise pin LPIN 2 is active. While the
high current mode is activated LPIN 3 is switched
on.
INLOCK DETECTOR
The charge pump is switched in low current mode
as the truth table and the related figure shows.
CURRHIGH
LOCKENA
LOCK
(by inlock
detector)
Charge
Pump
Current
0
X
X
low current
1
1
1
1
1
0
low current
High current
1
0
1
High current
1
0
0
High current
The charge pump is forced in low current mode
when a phase difference of 10-40 usec is
reached.
A phase difference larger than the programmed
values will switch the charge pump immediately in
the high current mode.
Few programmable delays are available for inlock
detection.
IF COUNTER SYSTEM FOR AM/FM
The IF counter mode is controlled by IFCM register:
IFCM1
IFCM0
FUNCTION
0
0
NOT USED
0
1
FM MODE
1
0
AM MODE
1
1
NOT USED
A sample timer to generate the gate signal for the
main counter is built with a 14 bit programmable
counter to have the possibility to use any fre-
15/38
TDA7421
ADDRESS ORGANIZATION (PLL and IF Counter)
LSB
MSB
FUNCTION
SUBAD
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PLL CHARGE PUMP
00H
L P IN 1 / 2
CURRH
B1
B0
A3
A2
A1
A0
PLL COUNTER
01H
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PLL COUNTER
02H
PC15
PC14
PC13
PC12
PC11
PC10
PC9
PC8
PLL REF
COUNTER
03H
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
PLL REF
COUNTER
PLL LOCK
DETECT
IFC REF COUNTER
04H
RC15
RC14
RC13
RC12
RC11
RC10
RC9
RC8
05H
LDENA
-
D3
D2
D1
D0
PM1
PM0
06H
IRC7
IRC6
IRC5
IRC4
IRC3
IRC2
IRC1
IRC0
IFC REF COUNTER
07H
IFCM1
IFCM0
IRC13
IRC12
IRC11
IRC10
IRC9
IRC8
IFC CONTROL
08H
IFENA
-
-
-
-
EW2
EW1
EW0
IFC CONTROL
09H
IFS2
IFS1
IFS0
CF4
CF3
CF2
CF1
CF0
quency. In FM mode a 6.25 KHz, in AM mode a
1KHz signal is generated. This counter is followed by an asynchronous divider to generate
several sampling times.
Intermediate Frequency Main Counter (IFMC)
This counter is a 13-21 bit synchronous autoreload down-counter. Four bits are programmable
to have the possibility for an adjust to the frequency of the IF filter.
The counter length is automatically adjusted to
the chosen sampling time and the counter mode.
At the start the counter will be loaded with a defined value which is an equivalent to the divider
value (tsample fIF).
If a correct frequency is applied to the IF counter
frequency inputs IF-AM and IF-FM, at the end of
the sampling time the main counter is changing
its state from 0 to 1FFFFFH.
This is detected by a control logic. The frequency
range inside which a successful count results is
detected is adjustable setting bits EW 0, 1, 2.
Up-down counter filter
The information coming from the IF main counter
control logic is shifted into a 5 bit up down
counter circuit clocked by the sampling time signal. At the start (rising edge of the IFENA signal)
the counter is set to 10H and the SSTOP signal is
forced to "1".
Only when the counter reaches the value 10H step, SSTOP goes to "0".
SSTOP will be "1" again, if the counter reaches
the value 10h + step.
16/38
Charge Pump Logic
CURR HIGH
CHARGE PUMP
CURRENT
LOCKENA
LOCK
D96AU548
FM and AM operation (swallow mode)
I2C bus
REF OSC IN
fosc
REGISTER
R0 ...R15
DIVIDER
:R
fref
fsyn
2
I C bus
REGISTER
PC0 ...PC4
AM IN
COUNTER
A
(O/I)
PRESCALER
32/33
2
I C bus
REGISTER
PC5 ... P15
DIVIDER
:B
FM IN
D96AU545
PD
TDA7421
ttim = (IFRC + 1) / fosc
tcnt = (CF + 1697) / fIF
tcnt = (CF + 44) / fIF
by controlling the discrimination window. This is
adjustable by programming the control registers
EW0...EW2.
The measurement time per cycle is adjustable by
setting the register IFS0 - IFS2.
The center frequency of the discrimination window is adjustable by the control register "CF0" to
"CF4". The available values are reported in databyte specification
FM mode
AM mode
Counter result succeeded:
ttim > tcnt - terr and
ttim > tcnt + terr
Counter result failed:
ttim< tcnt + terr or
ttim > tcnt - terr
where:
ttim = IF time cycle time
tcnt = IF counter cycle time
terr = discrimination window (controlled by the EW
registers)
succeeded
failed
tcnt -tERR
tcnt +tERR
D96AU551
failed
ttim
The precision of the measurements is adjustable
I2C BUS INTERFACE
General Description
The TDA7421 supports the I2C bus protocol. This
protocol defines the devices sending data into the
bus as transmitter and the receiving device as the
receiver.
The device that controls the transfer is a master
and the device being controlled is the slave. The
master will always initiates data transfer and provide the clock to transmit or receive operations.
Data Transition
Data transition on the SDA line must only occur
when the clock SCL is low. SDA transitions while
SCL is high will be interpreted as START or
STOP condition.
Start Condition
Phase Comparator
17/38
TDA7421
A start condition is defined by a HIGH to LOW
transition of the SDA line while SCL is at a stable
HIGH level. This START condition must precede
any command and initiate a data transfer onto the
bus.
The TDA7421 continuously monitors the SDA
and SCL lines for a valid START and will not response to any command if this condition has not
been met.
Stop condition
A STOP condition is defined by a LOW to HIGH
transition of the SDA while the SCL line is at a
stable HIGH level. This condition terminate the
communication between the devices and force’s
the bus interface of the TDA7421 into the initial
condition.
Acknowledge
Indicates a successful data transfer. The transmitter will release the bus after sending 8 bit of
data. During the 9th clock cycle the receiver will
pull the SDA line to LOW level to indicate it has
received the eight bits of data correctly.
Data transfer
During data transfer the TDA7421 samples the
SDA line on the leading edge of the SCL clock,
Therefore, for proper device operation the SDA
line must be stable during the SCL LOW to HIGH
transition.
Device Addressing
To start the communication between two devices,
the bus master must initiate a start instruction sequence, followed by an eight bit word corresponding to the address of the device it is addressing. The most significant 6 bits of the slave
address identify the device type.
The TDA7421 device code is fixed as "110001".
The next significant bit is used either to address
the tuner section (1) or the PLL section (0) of the
chip.
Following a START condition the master sends
slave address word; the TDA7421 will "acknowledge" after this first transmission and wait for a
second word (the word address field).
This 8 bit address field provides an access to any
of the 8 internal addresses. Upon receipt of the
word address the TDA7421 slave device will respond with an "acknowledge".
At this time, all the following words transmits to
the TDA7421 will be considered as data.
The internal address will be automatically incremented. After each word receipt the TDA7421 will
answer with an "acknowledge".
The interface protocol comprises:
– a subaddress byte
– a sequence of data (N-bytes + acknowledge)
– a stop condition (P)
– a start condition (S)
– a chip address byte
CONTROL REGISTER FUNCTION
REGISTER NAME
PC
RC
IRC
IFCM
EW
IFENA
CF
IFS
PM
D
LPIN1/2
A
B
LDENA
CURRH
18/38
FUNCTION
Programmable Counter for VCO Frequency
Reference Counter PLL
Reference Counter IF
IF Counter Mode
Frequency Error Window
Enable IF Counter
Center Frequency IF Counter
Sampling Time IF Counter
Stby, FM, AM, AM swallow mode (PLL Mode)
Programmable Delay for Lock Detector
Loop Filter Input Select
Charge Pump High Current
Charge Pump Low Current
Lock Detector Enable
Set Current High
TDA7421
IF Counter Block Diagram
IFENA
EW-REGISTER
IF-AM
11-21 BIT COUNTER
CF-REGISTER
IF-FM
OSC
ZD
14 BIT COUNTER
3 BIT COUNTER
IFC-REGISTER
IFS-REGISTER
UP/DOWN COUNTER
D97AU809
I2C Bus Timing Diagram
tHIGH
tR
tLOW
tR
SCL
tSU-STA
tHD-DAT
tSUBTOP
tSD-DAT
tHD-STA
SDA IN
tAA
tDH
ttxt
SDA OUT
D95AU378
19/38
TDA7421
Frame Example
For addressing the PLL part:
CHIP ADDRESS
SUBADDRESS
MSB
S
1
LSB
1
0
0
0
1
0
0
MSB
ACK
DATA 1 to DATA n
LSB
T2 T1 T0
A3 A2 A1 A0
I
MSB
LSB
ACK
ACK
P
D96AU549
for the TUNER part:
SUBADDRESS
CHIP ADDRESS
MSB
S
1
LSB
1
0
0
0
1
1
0
MSB
ACK
0
DATA 1 to DATA n
LSB
0
0
I
A3 A2 A1 A0
MSB
LSB
ACK
ACK
P
D96AU550
ACK = Acknowledge
S = Start
P = Stop
I = Page mode
T2, T1, T0 = used in test mode (for PLL only, for
TUNER addressing they must be 0)
A3, A2, A1, A0 = Mode selection
TUNER SUBADDRESS
MSB
X
X
X
I
A3
0
0
0
0
0
0
0
0
1
1
A2
0
0
0
0
1
1
1
1
0
0
A1
0
0
1
1
0
0
1
1
0
0
LSB
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
FUNCTION
STATUS
FM STOP STATION / FM IF AGC
FM SMETER SLIDER
AM AGC1 / AM STOP STATION
IFT1 / IFT2
FRONT END ADJUSTMENT
FM DEMODULATOR ADJUSTMENT
FM IF BUFFERS
FM AUDIO MUTE GAIN / FM SOFT MUTE
FM HOLE DETECTOR / FM DETUNING
Page mode disabled
Page mode enabled
must be "0"
PLL SUBADDRESS
MSB
T3
T2
T1
I
0
1
A3
0
0
0
0
0
0
0
0
1
1
A2
0
0
0
0
1
1
1
1
0
0
A1
0
0
1
1
0
0
1
1
0
0
LSB
A0
0
1
0
1
0
1
0
1
0
1
FUNCTION
Charge pump control
PLL counter 1 (LSB)
PLL counter 2 (MSB)
PLL reference counter 1 (LSB)
PLL reference counter 2 (MSB)
PLL lockdetector control and PLL mode select
IFC reference counter 1 (LSB)
IFC reference counter 2 (MSB) and IFC mode select
IF counter control 1
IF counter control 2
page mode DISABLED
page mode enabled
T1, T2, T3 are used for testing the PLL, in application mode they have to be "0".
20/38
TDA7421
PLL DATA BYTE SPECIFICATION
CHARGEPUMP CONTROL
MSB
D7
D6
D5
D4
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
B1
B0
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
LSB
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
A2
A1
A0
0
1
0
1
LPIN1/2 CURRH
A3
FUNCTION
High current = 0mA
High current = 0.5mA
High current = 1.0mA
High current = 1.5mA
High current = 2.0mA
High current = 2.5mA
High current = 3.0mA
High current = 3.5mA
High current = 4.0mA
High current = 4.5mA
High current = 5.0mA
High current = 5.5mA
High current = 6.0mA
High current = 6.5mA
High current = 7.0mA
High current = 7.5mA
Low current = 0µA
Low current = 15µA
Low current = 100µA
Low current = 115µA
Select low Current
Select high Current
Select loop filter 1
Select loop filter 2
Subaddress = 00H
PLL COUNTER 1 (LSB)
MSB
LSB
D7
D6
D5
0
0
0
0
0
0
0
0
0
D4
D3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PC7
1
PC6
1
PC5
1
PC4
1
PC3
D2
FUNCTION
D1
D0
0
0
1
0
1
0
LSB = 0
LSB = 1
LSB = 2
•••
1
1
1
0
0
1
0
1
0
LSB = 252
LSB = 253
LSB = 254
1
PC2
1
PC1
1
PC0
LSB = 255
Bit name
0
0
0
0
0
0
0
0
0
all combinations allowed
Subaddress = 01H
21/38
TDA7421
PLL COUNTER 2 (MSB)
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
MSB = 0
0
0
0
0
0
0
0
1
MSB = 256
0
0
0
0
0
0
all combinations allowed
1
0
MSB = 512
•••
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
MSB = 64768
MSB = 65024
1
1
1
1
1
1
1
0
MSB = 65280
MSB = 65536
1
1
1
1
1
1
1
1
PC15
PC14
PC13
PC12
PC11
PC10
PC9
PC8
Bit name
Subddress = 02H
Swallow mode: fvco/fsyn = LSB + MSB + 32
PLL REFERENCE COUNTER 1 (LSB)
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
LSB = 0
LSB = 1
0
0
0
0
0
0
all combinations allowed
1
0
LSB = 2
•••
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
LSB = 252
LSB = 253
LSB = 254
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
LSB = 255
Bit name
Subaddress =03H
PLL REFERENCE COUNTER 2 (MSB)
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
MSB = 0
MSB = 256
MSB = 512
1
1
1
1
1
1
all combinations allowed
1
1
1
1
1
1
0
0
0
1
•••
MSB = 64768
MSB = 65024
1
1
RC15
1
1
RC14
1
1
RC13
1
1
RC9
0
1
RC8
MSB = 65280
MSB = 65536
Bit name
1
1
RC12
fOSC/fREF = LSB + MSB + 1
22/38
1
1
RC11
1
1
RC10
Subddress = 04H
TDA7421
LOCK DETECTOR & PLL MODE CONTROL
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
0
D0
0
0
1
FUNCTION
PLL standby mode
PLL AM
1
0
not used
1
1
PLL FM mode
0
0
PD phase difference threshold 10ns
0
1
1
0
PD phase difference threshold 20ns
PD phase difference threshold 30ns
1
1
PD phase difference threshold 40ns
0
0
Not used in application mode
0
1
Activation delay = 4 ⋅ fref
1
0
Activation delay = 6 ⋅ fref
1
1
Activation delay = 8 ⋅ fref
0
1
No lock detector controlled chargepump
Lock detector controlled chargepump
LDENA
D3
D2
D1
D0
PM1
PM0
Bit name
Subaddress = 05H
IF COUNTER REFERENCE CONTROL 1 (LSB)
MSB
LSB
D7
D6
D5
0
0
0
0
0
0
0
0
0
D4
D3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IRC7
1
IRC6
1
IRC5
1
IRC4
1
IRC3
D2
FUNCTION
D1
D0
0
0
1
0
1
0
LSB = 0
LSB = 1
LSB = 2
•••
1
1
1
0
0
1
0
1
0
LSB = 252
LSB = 253
LSB = 254
1
IRC2
1
IRC1
1
IRC0
LSB = 255
Bit name
0
0
0
0
0
0
0
0
0
all combinations allowed
Subaddress = 06H
23/38
TDA7421
IF COUNTER REFERENCE CONTROL 2 (MSB) AND IF COUNTER MODE SELECT
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
MSB = 0
0
0
0
0
0
0
0
1
MSB = 256
0
0
0
0
0
0
all combinations allowed
1
0
MSB = 512
•••
1
1
1
1
0
1
MSB = 15616
1
1
1
1
1
0
MSB = 15872
1
1
1
1
1
1
MSB = 16128
0
0
NOT USED IN APPLICATION MODE
0
1
IF counter FM mode
1
0
IF counter AM mode
1
1
not used
IFCM1 IFCM0 IRC13
IRC12 IRC11
IRC10
IRC9
IRC8
Bit name
Subaddress = 07H
fosc/ftim = LSB + MSB + 1
IF COUNTER CONTROL 1
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
don’t use
don’t use
0
0
1
1
0
1
don’t use
EW delta f = ±6.25KHz (FM); ±1KHz (AM)
1
0
0
EW delta f = ±12.5KHz (FM); ±2KHz (AM)
1
0
1
EW delta f = ±25KHz (FM); ±4KHz (AM)
1
1
1
1
0
1
EW delta f = ±50KHz (FM); ±8KHz (AM)
EW delta f = ±100KHz (FM); ±16KHz (AM)
IF counter disabled / stand by
IF counter enabled
EW2
EW1
EW0
0
1
IFENA
24/38
FUNCTION
Bit name
Subaddress = 08H
TDA7421
IF COUNTER CONTROL 2
MSB
D7
LSB
D6
D5
FUNCTION
D4
D3
D2
D1
D0
0
0
0
0
0
fcenter = 10.60000MHz (FM) 448KHz (AM)
0
0
0
0
1
fcenter = 10.60625MHz (FM) 449KHz (AM)
0
0
0
0
0
0
1
1
0
1
fcenter = 10.61250MHz (FM) 450KHz (AM)
fcenter = 10.61875MHz (FM) 451KHz (AM)
0
0
0
0
1
1
0
0
0
1
fcenter = 10.62500MHz (FM) 452KHz (AM)
fcenter = 10.63125MHz (FM) 453KHz (AM)
0
0
0
0
1
1
1
1
0
1
fcenter = 10.63750MHz (FM) 454KHz (AM)
fcenter = 10.64375MHz (FM) 455KHz (AM)
0
1
0
0
0
fcenter = 10.65000MHz (FM) 456KHz (AM)
0
1
0
0
1
fcenter = 10.65625MHz (FM) 457KHz (AM)
0
0
1
1
0
0
1
1
0
1
fcenter = 10.66250MHz (FM) 458KHz (AM)
fcenter = 10.66875MHz (FM) 459KHz (AM)
0
1
1
0
0
fcenter = 10.67500MHz (FM) 460KHz (AM)
0
1
1
0
1
fcenter = 10.68125MHz (FM) 461KHz (AM)
0
0
1
1
1
1
1
1
0
1
fcenter = 10.68750MHz (FM) 462KHz (AM)
fcenter = 10.69375MHz (FM) 463KHz (AM)
1
1
0
0
0
0
0
0
0
1
fcenter = 10.70000MHz (FM) 464KHz (AM)
fcenter = 10.70625MHz (FM) 465KHz (AM)
1
0
0
1
0
fcenter = 10.71250MHz (FM) 466KHz (AM)
1
1
0
0
0
1
1
0
1
0
fcenter = 10.71875MHz (FM) 467KHz (AM)
fcenter = 10.72500MHz (FM) 468KHz (AM)
1
0
1
0
1
fcenter = 10.73125MHz (FM) 469KHz (AM)
1
1
1
0
0
1
1
1
0
1
1
0
0
1
0
fcenter = 10.73750MHz (FM) 470KHz (AM)
fcenter = 10.74375MHz (FM) 471KHz (AM)
fcenter = 10.75000MHz (FM) 472KHz (AM)
1
1
0
0
1
fcenter = 10.75625MHz (FM) 473KHz (AM)
1
1
1
1
0
0
1
1
0
1
fcenter = 10.76250MHz (FM) 474KHz (AM)
fcenter = 10.76875MHz (FM) 475KHz (AM)
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
fcenter = 10.77500MHz (FM) 476KHz (AM)
fcenter = 10.78125MHz (FM) 477KHz (AM)
fcenter = 10.78750MHz (FM) 478KHz (AM)
fcenter = 10.79375MHz (FM) 479KHz (AM)
0
0
0
0
0
1
tsample = 20.48ms (FM mode); 128ms (AM; MODE)
tsample = 10.24ms (FM mode); 64ms (AM; MODE)
0
0
1
1
1
1
0
0
0
1
0
1
tsample = 5.12ms (FM mode); 32ms (AM; MODE)
tsample = 2.56ms (FM mode); 16ms (AM; MODE)
tsample = 1.28ms (FM mode); 8ms (AM;MODE)
tsample = 640µs (FM mode); 4ms (AM;MODE)
1
1
0
1
1
1
IFS2 IFS1 IFS0 CF4 CF3 CF2
tsample = 320µs (FM mode); 2ms (AM; MODE)
tsample = 160µs (FM mode); 1ms (AM; MODE)
CF1 CF0 bit name
Subaddress = 09H
25/38
TDA7421
TUNER DATA BYTE SPECIFICATION
ADDRESS ORGANIZATION (Tuner AM/FM)
LSB
MSB
FUNCTION
SUBAD
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
T ES T O N FMMUTE FMADJ FMHIGH AMSTER AMSEEK AM/FM/
EO
/ FM
STBY
RECSEEK
BIT 0
STATUS
00H
AM/FM/
STBY
FM STOP STATION/
FM IF AGC
01H
FAG2
FAG1
FAG0
FSS4
FSS3
FSS2
FSS1
FSS0
FM SMETER SLIDER
02H
FSL4
FSL3
FSL2
FSL1
FSL0
-
-
-
AM AGC1/AM STOP
STATION
03H
ASS3
ASS2
ASS1
ASS0
AAG3
AAG2
AAG1
AAG0
IFT1/IFT2
04H
T2A3
T2A2
T2A1
T2A0
T1A3
T1A2
T1A1
T1A0
FRONT END
ADJUSTMENT
05H
ANA3
ANA2
ANA1
ANA0
RFA3
RFA2
RFA1
RFA0
FM DEMODULATOR
ADJUSTMENT
FM IF BUFFERS
06H
SDD
DEM6
DEM5
DEM4
DEM3
DEM2
DEM1
DEM0
07H
FBL3
FBL2
FBL1
FBL0
FBH3
FBH2
FBH1
FBH0
FM SOFT MUTE/
FM AUDIO MUTE GAIN
08H
FSM3
FSM2
FSM2
FSM0
-
AUM2
AUM1
AUM0
FM HOLE DETECTOR
/FM DETUNING
DETECTOR
09H
BWM2
BWM1
BWM0
HDM4
HDM3
HDM2
HDM1
HDM0
26/38
TDA7421
STATUS (subaddress 00H)
MSB
S7
LSB
S6
TESTON FMMUTE
S5
S4
FMADJ FMHIGH
S3
S2
S1
AM
AM
AM/FM/
STEREO SEEK/FM STBY
RECSEEK
X
X
0
X
X
X
X
0
0
0
0
X
0
0
AM/FM/
STBY
0
STAND-BY
1
FM ON, RECEPTION, DEEP
MUTE
FM ON, SEEK, DEEP MUTE
0
0
0
0
X
1
0
1
0
0
0
1
X
0
0
1
0
0
0
1
X
1
0
1
0
0
1
X
X
X
0
1
0
1
1
X
X
X
0
1
0
X
X
X
0
0
1
0
0
X
X
X
0
1
1
0
0
X
X
X
1
0
1
0
0
X
X
X
1
1
1
0
0
X
X
X
0
0
1
1
0
X
X
X
0
1
1
1
0
X
X
X
1
0
1
1
0
X
X
X
1
1
1
1
X
X
1
FUNCTION
S0
FM ON, RECEPTION,
SHALLOW MUTE
FM ON,SEEK SHALLOW
MUTE
FM ON FOR DEMOD
ADJUSTM, DEMOD ON
FM ON FOR DEMOD
ADJUSTMENT DEMOD
MUTED
AM ON (Japan), RECEPTION,
IFC OUT SELECTED
AM ON (Japan), SEEK, IFC
OUT SELECTED
AM ON (Japan),
RECEPTION AM STEREO
OUT SELECTED
AM ON (Japan), SEEK, AM
STEREO OUT SELECTED
AM ON (EU, US), RECEPTION,
IFC OUT SELECTED
AM ON (EU, US), SEEK, IFC
OUT SELECTED
AM ON (EU, US),
RECEPTION AM STEREO
OUT SELECTED
AM ON (EU, US), SEEK, AM
STEREO OUT SELECTED
PLL TEST OUTPUT ENABLED
AM TURN ON SEQUENCE AT POWER ON: it is necessary to cycle through ST-BY for a correct operation.
27/38
TDA7421
FM STOP STATION / FM IF AGC (subaddress 01H)
MSB
LSB
FUNCTION
FAG2
FAG1
FAG0
FAG4
FSS3
FSS2
FSS1
FSS0
fmifagc
MSB
fmifagc
fmifagc
LSB
fmstop
station
MSB
fmstop
station
fmstop
station
fmstop
station
fmstop
station
LSB
FM STOP STATION
THRESHOLD
0
X
0
X
0
X
0
X
0
X
Maximum sensitivity
•••
1
1
1
1
1
Minimum sensitivity
all combinations allowed
FM IF AGC
THRESHOLD
0
0
0
Maximum sensitivity
X
X
X
•••
1
1
0
Minimum sensitivity
1
1
1
Keying AGC disabled
all combinations allowed
FM SMETER SLIDER (subaddress 02H)
MSB
FSL4
fmsmeters
lider MSB
0
0
0
0
0
1
1
28/38
LSB
FSL3
FSL2
FSL1
fmsmeterslider
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
1
1
1
all combinations allowed
FUNCTION
FSL0
fmsmeter
slider LSB
0
1
0
1
0
0
1
FM SMETER SLIDER
THRESHOLD (mV)
300 (baseline)
348.4 (+48.4)
396.8 (+96.8)
493.6 (+193.6)
687.2 (+387.2)
1074.4 (+774.4)
1800 (top)
TDA7421
AM STOP STATION / AM AGC1 (subaddress 03H)
MSB
LSB
ASS3
ASS2
amstopsta
tion MSB
ASS1
amstopstation
AAG3
AAG2
AAG1
AAG0
amstopsta
tion LSB
amagc1
MSB
amagc1
amagc1
amagc1
LSB
0
X
0
X
0
X
0
X
Maximum sensitivity
•••
1
Minimum sensitivity
AM STOP STATION
THRESHOLD
1
0
X
1
FUNCTION
ASS0
1
1
all combinations allowed
AM AGC1
THRESHOLD
0
X
0
X
0
X
Maximum sensitivity
•••
1
1
1
Minimum sensitivity
all combinations allowed
IFT1/ IFT2 (subaddress 04H)
MSB
LSB
FUNCTION
T2A3
T2A2
T2A1
T2A0
T1A3
T1A2
T1A1
T1A0
IFT2
adjust
MSB
IFT2
adjust
IFT2
adjust
IFT2
adjust
LSB
IFT1
adjust
MSB
IFT1
adjust
IFT1
adjust
0
0
0
IFT1
adjust
LSB
0
0
0
0
0
0
1
0
1
0
1
0
0
Cift1
2Cift1
4Cift1
1
0
0
0
8Cift1
1
1
1
1
15Cift1
ADJUSTMENT
CAPACITOR
0
all combinations allowed
0
0
0
0
0
0
0
0
0
0
1
1
0
Cift2
2Cift2
0
0
1
4Cift2
8Cift2
15Cift2
0
1
1
1
0
0
0
1
1
all combinations allowed
29/38
TDA7421
FRONT END ADJUSTMENT (subaddress 05H)
MSB
LSB
FUNCTION
ANA3
ANA2
ANA1
ANA0
RFA3
RFA2
RFA1
RFA0
ant
adjustm
MSB
ant
adjustm
ant
adjustm
ant
adjustm
LSB
RF
adjustm
MSB
RF
adjustm
RF
adjustm
RF
adjustm
LSB
X
0
0
0
0
0
0
1
0
-3.6%
0
0
1
0
-7.2%
0
1
0
0
-14.3%
0
1
1
1
-25%
1
1
0
0
0
1
1
0
3.6%
7.2%
1
1
1
1
0
1
0
1
14.3%
25%
Voffset RF varicap /
VPLL
all combinations allowed
V offset antenna varicap
/ VPLL
X
0
0
0
0
0
0
1
0
-3.6%
0
0
0
0
1
1
1
0
1
0
0
1
-7.2%
-14.3%
-25%
1
0
0
1
3.6%
1
1
1
0
1
1
1
0
1
0
0
1
7.2%
14.3%
25%
all combinations allowed
30/38
TDA7421
FM DEMODULATOR ADJUSTMENT (subaddress 06H)
MSB
LSB
FUNCTION
SDD
DEM6
DEM5
DEM4
DEM3
DEM2
DEM1
DEM0
SD
disable
demadj
MSB
0
demadj
demadj
demadj
demadj
demadj
0
0
0
0
0
demadj
LSB
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
Cdemod
2Cdemod
0
0
0
0
0
0
0
1
1
0
0
0
0
0
4Cdemod
8Cdemod
0
0
1
0
0
0
0
16Cdemod
0
1
1
0
0
0
0
0
0
0
0
0
0
0
32Cdemod
64Cdemod
1
1
1
1
1
1
1
127Cdemod
ADJUSTMENT
CAPACITOR
0
all combinations allowed
SD DISABLE
0
1
SD ENABLED
SD DISABLED (High
impedance output)
FM IF BUFFERS (subaddress 07H)
MSB
FBL3
LSB
FBL2
FBL1
FBL0
FBH3
FBH2
FBH1
buff2
buff2 gain buff2 gain buff2 gain
buff1
buff1
buff1 gain
buff1
gain MSB
LSB
gain MSB gain MSB
gain LSB
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
all else not allowed
FUNCTION
FBH0
BUFFER 1 GAIN (dB)
0
1
0
19.5
15.5
16.5
0
0
17.5
18.5
BUFFER 2 GAIN (dB)
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
all else not allowed
0
1
8
4
0
0
0
5
6
7
31/38
TDA7421
FM SOFT MUTE / FM AUDIO MUTE GAIN (subaddress 08H)
MSB
FSM3
FSM2
FSM1
FSM0
AUM2
fmsoftmute fmsoftmute fmsoftmute fmsoftmute
MSB
LSB
0
0
0
0
X
X
X
X
1
1
1
1
all combinations allowed
LSB
AUM0
AUM1
buff1 gain buff1 gain buff1 gain
MSB
LSB
0
0
1
0
1
1
0
1
0
1
1
1
0
0
1
0
1
1
0
1
0
1
1
1
FUNCTION
FM SOFT MUTE
THRESHOLD
Maximum sensitivity
•••
Minimum sensitivity
Audio max mute atten.
(dB) with bit FMHIGH
byte 0 = 1
1
-2.5
0
-5
0
-7.5
1
-10
0
-12.5
1
-15
Audio max mute atten.
(dB) with bit FMHIGH
byte 0 = 0
1
-17.5
0
-20
0
-22.5
1
-25
0
-27.5
1
-30
all else not allowed
FM HOLE DETECTOR / FM DETUNING DETECTOR (subaddress 09H)
MSB
LSB
BWM2
BWM1
BWM0
HDM4
HDM3
HDM2
HDM1
HDM0
BW MSB
BW
BW LSB
Hole det
MSB
0
X
1
Hole det
Hole det
Hole det
Hole det
LSB
0
X
1
0
0
0
X
X
X
1
1
1
all combinations allowed
FUNCTION
MUTING SENSITIVITY
Minimum (deep hole)
•••
Maximum (shallow hole)
RECEPTION
0
0
1
0
1
0
1
0
0
all else not allowed
DETUNING MUTE RANGE
SEEK
0
0
0
X
X
X
1
1
1
all combinations allowed
CLAMPING WINDOW
32/38
10 (KHz)
15 (KHz)
30 (KHz)
Minimal Window
Intermediate values
Maximal Window
TDA7421
Evaluation Board Schematic Circuit (part A)
30 dB differential gain
FM IN
SP
RFVcc
From Cx - see schematic (part D)
0
100K
10n
10n
1
5p
T1
MIX_IN
6p
6p
50
100K
470
1K
3p
0
1K8
FM MIX IN-
4
FM MIX IN+
5
FM RF AGC IN
15p
OSC GND
11
XTAL D
12
1M
10.25MHz
1K5
VCO E
10
15p
0
VCO B
9
68p
L2
RF GND
8
22u +
3.3p
FM AGC OUT
7
22p
0
AM MIX1 IN+
3
6
100K
100n
AM MIX1 IN-
2
XTAL
13
OSC VCC
14
15p
FM ANT ADJ
15
4.7n
TP20
FM RF ADJ
16
1K5
PLL VCC
OSCVcc
4.7n
5K6
10n
10n
+
10u
0
TP21
1K5
From LPOUT - pin 17
47n
AM AGC2 TC
IF2 GND
AM DET
32
31
30
IFC SSTOP/AM ST
DIG GND
CLN GND
29
28
27
SCL
DIG VDD
26
SDA
25
24
PLL GND
PLL VREF
LP IN3
SLEEP
23
22
21
20
LP IN1
LP IN2
19
18
17
LP OUT
Evaluation Board Schematic Circuit (part B)
From Rx
TP18
33n
33K
+
3.3n
22n
2.7n
4K3
TP22
1n
+
2.2u
18K
I2CBUS
1
2
3
4
5
TP19
AM ST
22n
+5V
+
4.7n
10u
33/38
TDA7421
Evaluation Board Schematic Circuit (part C)
see schematic (part D)
TP11
TP12
48
FMIF AMP2OUT
47
IF1 VCC
IF1Vcc
0
46
FM LIM IN+
45
FM LIM IN-
50
+
+
2.2u
40
TP13
1u
TP14
TP15
FMIF2
CF4
10.7MHz
22n
IF1 GND 44
43
FM BW TC
42
FM MUTE DRIVE
FM/AM S-METER 41
FM SD/AM SD
0
22n
TP16
100K
39
AUDIO OUT
AUDIO OUT
38
FM QUAD+
FM QUAD-
37
IF2 VCC
36
AM IF2 IN
35
AM REF
34
AM BPF
33
5K6
L6
IF2Vcc
+
1mH
10n
22u
120p
TP17
Evaluation Board Schematic Circuit (part D)
FMIF1
RFVcc
TP6
1
TP5
1
50
27
0
1K
1mH
AMIF
0
0
100n
TP7
1
RFVcc
100n
50
CF1
10.7MHz
82p
AM IN
0
TP3
1
0
TP4
1
0
0
0
AMAMP
1 TP8
10n
27
15p
1u
T2
4K7
+
50
F2
450KHz
+
T3
470
0
0
TP2
1
TP1
1
4K7
0
0
RFVcc
22n
18p
1.5n
F3
10.7MHz
+
1u
2K7
68p
0
10n
0
+
1u
3p
From pin 1 - AM MIX IN-
1
TP10
1
TP9
22n
50
51
52
49
FMIF AMP2IN-
FMIF AMP2IN+
FMIF AMP1OUT
54
55
53
FMIF AMP1 IN+
AM MIX2 OUT-
56
RF VCC
AM MIX2 OUT+
58
57
AM MIX2 IN-
AM MIX2 IN+
60
61
62
59
FM IF AGC IN
MIX OUT-
MIX OUT+
10n
63
RFVcc
AM AGC1 PIN
10n
120p
AM AGC1 TC
82p
64
0
0
22n
68uH
AM AGC1 RF AMP
68uH
FMIF AMP1 IN-
1M
22n
From pin 35 - AM IF2 IN
From pin 48 - FMIF AMP2 OUT
34/38
TDA7421
Evaluation Board Schematic Circuit (part E)
Supply Voltage (12V)
10
Gnd
MR1
+Vs
JP1
220n
1
F.C.
OSCVcc
10
IF1Vcc & IF2 Vcc
+ 100u
N.C.
5
NC
NC
6
GND GND
VO
1
L78L05A
4
220n
VIN
47u
56 78
3
8
+
GND GND
100n
L4916
7
OUT 8.5V 4
2
3
GND
GND
GND
GND
10u + 100n
PLLVcc
10
+VS
2
RFVcc
10
+5V
220n
Ground path
Notes:
- The components shown on the evaluation board schematic without the part value, are required only
for measurements between intermediate input/outputs:
- Parts description:
CF1
Ceramic filter 10.7MHz, 180KHz BW
CF3-CF4
Ceramic filter 10.7MHz, 150KHz BW
CF2
Ceramic filter 450KHz, 6KHz BW
T1
FM RF transformer
Unloaded Q= 103
3-1= 3 1/2T - 6-4= 1T 0.12φ2UEW
CTUNING(3-1)= 24pF @ 100MHz
T2
AM/FM IF1 transformer
Unloaded Q= 70
1-3= 13T - 1-5= 6 1/2T - 5-3= 6 1/2T - 4-6= 2T 0.08φ2UEW
CINT(1-2) = CINT(2-3) = 82pF; CEXT(1-3) = 10pF
T3
AM IF2 transformer
Unloaded Q= 40
1-3= 178T - 1-2= 89T - 2-3= 89T - 4-6= 33T 0.05φ2UEW
CINT(1-3) = 180pF; CEXT(1-3) = 20pF
L2
Oscillator coil
Unloaded Q= 80
6-4= 2 1/2T 0.12φ2UEW
CTUNING(6-4)= 36.8pF @ 100MHz
L6
Demodulator Coil
Unloaded Q= 35
6-4= 27T 0.1φ2UEW
CINT(4-6)= 47pF; CEXT(4-6) = 13.5pF
35/38
TDA7421
FM THD
FM S+N/N
Vs= 8V
fin= 98.1MHz +/-75KHz
fm= 1KHz
Vs= 8V
fin= 98.1MHz +/- 75KHz
T.H.D. (%)
RESPONSE (dB)
20Hz - 20KHz filter
FIELD STRENGTH
(dBu)
AM THD
fm= 1KHz
20Hz - 20KHz filter
without de-emphasis
FIELD STRENGTH (dBu)
AM S+N/N
Vs= 8V
fin= 1MHz m= 30%
Vs= 8V
fm= 1KHz
fin= 1MHz m= 30%
T.H.D. (%)
RESPONSE (dB)
20Hz - 20KHz filter
FIELD STRENGTH
36/38
(dBu)
fm= 1KHz
20Hz - 20KHz filter
FIELD STRENGTH (dBu)
TDA7421
TQFP64 PACKAGE MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
A
MIN.
TYP.
MAX.
1.60
A1
0.05
A2
1.35
B
C
0.063
0.15
0.002
0.006
1.40
1.45
0.053
0.055
0.057
0.18
0.23
0.28
0.007
0.009
0.011
0.12
0.16
0.20
0.0047
0.0063
0.0079
D
12.00
0.472
D1
10.00
0.394
D3
7.50
0.295
e
0.50
0.0197
E
12.00
0.472
E1
10.00
0.394
E3
7.50
0.295
L
0.40
0.60
L1
0.75
0.0157
0.0236
1.00
0.0295
0.0393
0°(min.), 7°(max.)
K
D
D1
A
D3
A2
A1
48
33
49
32
0.10mm
E
E1
E3
B
B
Seating Plane
17
64
1
16
C
L
L1
e
K
TQFP64
37/38
TDA7421
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics
© 1998 STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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38/38