STMICROELECTRONICS TDA7580

TDA7580
FM/AM DIGITAL IF SAMPLING PROCESSOR
PRODUCT PREVIEW
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FM/AM IF SAMPLING DSP
ON-CHIP ANALOGUE TO DIGITAL
CONVERTER FOR 10.7MHz IF SIGNAL
CONVERSION
SOFTWARE BASED CHANNEL EQUALIZATION
FM ADJACENT CHANNEL SUPPRESSION
RECEPTION ENHANCEMENT IN MULTIPATH
CONDITION
STEREO DECODER AND WEAK SIGNAL
PROCESSING
2 CHANNELS SERIAL AUDIO INTERFACE
(SAI) WITH SAMPLE RATE CONVERTER
I2C AND BUFFER-SPI CONTROL INTERFACES
RDS FILTER, DEMODULATOR & DECODER
INTER PROCESSOR TRANSPORT
INTERFACE FOR ANTENNA AND TUNER
DIVERSITY
FRONT-END AGC FEEDBACK
TQFP64
ORDERING NUMBER: TDA7580
DESCRIPTION
The TDA7580 is an integrated circuit implementing
an advanced mixed analogue and digital solution to
perform the signal processing of a AM/FM channel.
The HW&SW architecture has been devised so to
have a digital equalization of the FM/AM channel;
hence a real rejection of adjacent channels and any
other signals interfering with the listening of the desired station. In severe Multiple Paths conditions, the
reception is improved to get the audio with high quality.
BLOCK DIAGRAM
A/D
RDS
I2C/SPI
I2C/SPI
HS3I
IF Digital
Signal Processor
DAC
CGU
SAI1
SAI0
SRC
Oscillator
July 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/31
TDA7580
DESCRIPTION (continued)
The algorithm is self-adaptive, thus it requires no “on-the-field” adjustments after the parameters optimization.
The chip embeds a Band Pass Sigma Delta Analogue to Digital Converter for 10.7MHz IF conversion from a
“tuner device” (it is highly recommended the TDA7515).
The internal 24bit-DSP allows some flexibility in the algorithm implementation, thus giving some freedom for
customer required features. The total processing power offers a significant headroom for customer’s software
requirement, even when the channel equalization and the decoding software is running. The Program and Data
Memory space can be loaded from an external non volatile memory via I 2C or SPI.
The oscillator module works with an external 74.1MHz quartz crystal. It has very low Electro Magnetic Interference, as it introduces very low distortion, and in any case any harmonics fall outside the Radio bandwidth.
The companion tuner device receives the reference clock through a differential ended interface, which works
off the Oscillator module by properly dividing down the master clock frequency. That allows the overall system
saving an additional crystal for the tuner.
After the IF conversion, the digitized baseband signal passes through the Base Band processing section, either
FM or AM, depending on the listener selection. The FM Base Band processing comprises of Stereo Decoder,
Spike Detection and Noise Blanking. The AM Noise Blanking is fully software implemented.
The internal RDS filter, demodulator and decoder features complete functions to have the output data available
through either I2C or SPI interface. No DSP support is needed but at start-up, so that RDS can work in background and in parallel with other DSP processing. This mode (RDS-only) allows current consumption saving for
low power application modes.
An I2C/SPI interface is available for any control and communication with the main micro, as well as RDS data
interface. The DSP SPI block embeds a 10 words FIFO for both transmit and receive channels, to lighten the
DSP task and frequently respond to the interrupt from the control interface.
Serial Audio Interface (SAI) is the ideal solution for the audio data transfer, both transmit and receive: either
master or slave. The flexibility of this module gives a wide choice of different protocols, including I2S. Two fully
independent bidirectional data channels, with separate clocks allows the use of TDA7580 as general purpose
digital audio processor.
A fully Asynchronous Sample Rate Converter (ASRC) is available as a peripheral prior to sending audio data
out via the SAI, so that internal audio sampling rate (~36kHz and FM/AM mode) can be adapted by upconversion to any external rate.
An Inter Processor Transport Interface (HS 3I, High Speed Synchronous Serial Interface) is also available for a
modular system which implements Dual Tuner Diversity, thus enhancing the overall system performance. It is
about a Synchronous Serial Interface which exchanges data up to the MPX rate. It has been designed to reduce
the Electro Magnetic Interference toward the sensitive analogue signal from the Tuner.
General Purpose I/O registers are connected to and controlled by the DSP, by means of memory map.
A Debug and Test Interface is available for on-chip software debug as well as for internal registers read/write
operation.
2/31
TDA7580
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
VDD3
Parameter
Value
Unit
Nom. 1.8V
Nom. 3.3V
-0.5 to 2.5
-0.5 to 4.0
V
V
Analog Input or Output Voltage belonging to 3.3V IO ring (VDDSD,
VDDOSC)
-0.5 to 4.0
V
Digital Input or Output Voltage, 5V tolerant
Normal(2)
Fail-safe(3)
-0.5 to 6.50
-0.5 to 3.80
V
V
Nom. 1.8V
Nom. 3.3V
-0.5 to (VDD+0.5)
-0.5 to (VDD3+0.5)
V
Operating Junction Temperature Range
-40 to 125
°C
Storage Temperature
-55 to 150
°C
Power supplies (1)
All remaining Digital Input or Output Voltage
Tj
Tstg
Warning: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these
extremes.
Note: 1. VDD3 refers to all of the nominal 3.3V power supplies (VDDH, VOSC, VDDSD). VDD refers to all of the nominal 1.8V power supplies
(VDD, VMTR).
2. During Normal Mode operation VDD3 is always available as specified
3. During Fail-safe Mode operation VDD3 may be not available.
THERMAL DATA
Symbol
Rth j-amb
Parameter
Thermal resistance junction to ambient
Value
Unit
68
°C/W
3/31
TDA7580
VDD
DBOUT1
DBRQ1
DBIN1
DBCK1
VDDH
GNDH
DBOUT0
DBRQ0
DBIN0
DBCK0
58
57
56
55
54
53
52
51
50
49
VCMOP
59
5
GND
INN
60
4
VDDISO
INP
61
3
GNDH
VLO
62
2
VDDH
VCM
63
1
VDDSD
VHI
64
PIN CONNECTION (Top view)
DEBUG1
48
GND
DEBUG0 47
VDD
TST3_LRCKR
45
TST2_SCKR
44
LRCK_LRCKT
6
43
SCLK_SCKT
GNDSD
7
42
SDO0
GNDOSC
8
41
VDDH
XTI
9
40
GNDH
39
TST1_SDI1
OSC.
SAI
IFADC
46
10
VDDOSC
11
38
TST4_SDI0
VDDMTR
12
37
GPIO_SDO1
CKREFP
13
36
TESTN
35
GND
34
VDD
33
RESETN
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SCL_SCK
GND
VDD
IQSYNC
IQCH1
IQCH2
IQCH3
VDDH
GNDH
RDS_INT
RDS_CS
INT
ADDR_SD
16
RDS
MISO
GNDMTR
HS3I
SDA_MOSI
15
18
AGCKEY
17
14
S
D I
R
/ P
S2P C/S
D I
PROTSEL_SS
CKREFN
Tuner
XTO
IFADC Modulator Power Supply pins pair
Oscillator Power Supply pins pair
Tuner Clock Out and AGC Keying DAC Power Supply pins pair
Core Logic 1.8V Power Supply pins pair
I/O Ring 3.3V Power Supply pins pair
4/31
TDA7580
PIN DESCRIPTION
N°
Name
Type
Description
Notes
After
Reset
1
VHI
A
Internally generated IFADC Opamps
2.65V (@VDD=3.3V) Reference Voltage
Pin for external filtering
It needs external 22µF
and 220nF ceramic
capacitors
2
VCM
A
Internally generated Common Mode
1.65V (@VDD=3.3V) Reference Voltage
Pin for external filtering
It needs external 22µF
and 220nF ceramic
capacitors
3
VLO
A
Internally generated IFADC Opamps
0.65V (@VDD=3.3V) Reference Voltage
Pin for external filtering
It needs external 22µF
and 220nF ceramic
capacitors
4
INP
A
Positive IF signal input from Tuner
2.0Vpp @VDD=3.3V
5
INN
A
Negative IF signal input from Tuner
2.0Vpp @VDD=3.3V
6
VCMOP
A
Internally generated Modulator Opamps
Common Mode 2.65V (@VDD=3.3V)
Reference Voltage Pin for external
filtering
It needs external 22µF
and 220nF ceramic
capacitors
7
GNDSD
G
IFADC Modulator Analogue Ground
Clean Ground, to be
star-connected to
voltage regulator ground
8
GNDOSC
G
Oscillator Ground
Clean Ground, to be
star-connected to
voltage regulator ground
9
XTI
I
High impedance oscillator input (quartz
connection) or clock input when in
Antenna Diversity slave mode
Maximum voltage swing
is VDD
10
XTO
O
Low impedance oscillator output (quartz
connection)
11
VDDOSC
P
Oscillator Power Supply
3.3V
12
VDDMTR
P
Tuner reference clock and AGCKeying
DAC Power Supply
1.8V
13
CKREFP
B
Tuner reference clock positive output.
FM 100kHz
AMEU 18kHz
With internal pull_up, on
at reset
Output
14
CKREFN
B
Tuner reference clock negative output.
FM 100kHz
AMEU 18kHz
With internal pull_up, on
at reset
Output
15
AGCKEY
A
DAC output for Tuner AGCKeying
1.5kohm ±30% output
impedance. 1Vpp ±1%
output dynamic range
16
GNDMTR
G
Tuner reference clock and AGC keying
DAC Ground
5/31
TDA7580
PIN DESCRIPTION (continued)
Name
17
PROTSEL_SS
B
DSP0 GPIO for Control Serial Interface
(Low: SPI or High: I2C) selection at
device Bootstrap.
In SPI protocol mode, after Boot
procedure, SPI Slave Select, otherwise
DSP0 GPIO0
DSP0 GPIO0
5V tolerant
With internal pull_up, on
at reset
Input
18
SDA_MOSI
B
5V tolerant
Control Serial Interface and RDS IO:
- SPI mode: slave data in or master data With internal pull_up, on
at reset
out for main SPI and RDS SPI data in
- I2C mode: data for main I2C or RDS I2C
Input
19
MISO
B
SPI slave data out or master data in for
main SPI and RDS SPI data out
DSP0 GPIO1
5V tolerant
With internal pull_up, on
at reset
Input
20
SCL_SCK
B
Bit clock for Control Serial Interface and
RDS
5V tolerant
With internal pull_up, on
at reset
Input
21
GND
G
Digital Core Power Ground
22
VDD
P
Digital Core Power Supply
1.8V
23
IQSYNC
B
High Speed Synchronous Serial
Interface (HS3I) clock if HS3I master
mode, else DSP1 GPIO or DSP1 Debug
Port Clock (DBOUT1)
DSP1 GPIO0
5V tolerant
With internal pull_up, on
at reset
Input
24
IQCH1
B
High Speed Synchronous Serial
Interface (HS3I) Channel 1 Data if HS3I
master mode, else DSP1 GPIO or DSP1
Debug Port Request (DBRQ1)
DSP1 GPIO1
5V tolerant
With internal pull_up, on
at reset
Input
25
IQCH2
B
High Speed Synchronous Serial
Interface (HS3I) Channel 2 Data if HS3I
master mode, else DSP1 GPIO or DSP1
Debug Port Data In (DBIN1)
DSP1 GPIO2
5V tolerant
With internal pull_down,
on at reset
Input
26
IQCH3
B
High Speed Synchronous Serial
Interface (HS3I) Channel 3 Data if HS3I
master mode, else DSP1 GPIO or DSP1
Debug Port Data Out (DBCK1)
DSP1 GPIO3
5V tolerant
With internal pull_down,
on at reset
Input
27
VDDH
P
3.3V IO Ring Power Supply (HS3I, I2C/
SPI, RDS, INT)
28
GNDH
G
3.3V IO Ring Power Ground (HS3I, I2C/
SPI, RDS, INT)
29
RDS_INT
B
RDS interrupt to external main
microprocessor in case of traffic
information
DSP1 GPIO4
5V tolerant
With internal pull_up, on
at reset
Input
6/31
Type
Description
Notes
After
Reset
N°
TDA7580
PIN DESCRIPTION (continued)
N°
Name
Type
Description
Notes
After
Reset
30
RDS_CS
B
RDS chip select. When RESETN rising,
If RDS_CS 0, the RDS’s SPI is selected;
else RDS’s I2C
DSP1 GPIO5
5V tolerant
With internal pull_up, on
at reset
31
INT
I
DSP0 External Interrupt
5V tolerantWith internal
pull_up, on at reset
32
ADDR_SD
B
IFS chip master (Low) or slave (High)
mode selection, latched in upon
RESETN release. It selects the LSB of
the I2C addresses.
Station Detector output
DSP0 GPIO2
5V tolerantWith internal
pull_down, on at reset
33
RESETN
I
Chip Hardware reset, active Low
5V tolerant
With internal pull_up
34
VDD
P
Digital Power Supply
1.8V
35
GND
G
Digital Power Ground
36
TESTN
I
Test Enable pin, active Low
With internal pull_up
37
GPIO_SDO1
B
DSP0 GPIO for Boot selection or Audio
SAI0 output.
5V tolerant
DSP0 GPIO3
With internal pull_up, on
at reset
Input
38
TST4_SDI0
B
Audio SAI0 Data input or test selection
pin in Test Mode
5V tolerant
DSP0 GPIO5With
internal pull_up, on at
reset
Input
39
TST1_SDI1
B
DSP0 GPIO for Boot selection or Audio
SAI1 input. Test selection pin in Test
Mode.
5V tolerant
DSP0 GPIO4With
internal pull_up, on at
reset
Input
40
GNDH
G
3.3V IO Ring Power Ground (Audio SAI,
ResetN, Test Pins)
41
VDDH
P
3.3V IO Ring Power Supply (Audio SAI,
ResetN, Test Pins)
42
SDO0
B
Radio or Audio SAI0 data output
5V tolerant
With internal pull_up, on
at reset
Output
43
SCLK_SCKT
B
SAI0 Receive and Transmit bit clock
(master or slave with ASRC); SAI1
Transmit bit clock
5V tolerant
With internal pull_up, on
at reset
Input
44
LRCK_LRCKT
B
SAI0 Receive and Transmit LeftRight
clock (master or slave with ASRC); SAI1
Transmit LeftRight clock
5V tolerant
With internal pull_up, on
at reset
Input
Input
Input
7/31
TDA7580
PIN DESCRIPTION (continued)
N°
Name
Type
Description
Notes
After
Reset
45
TST2_SCKR
B
SAI0 Transmit bit clock; SAI1 Receive
and Transmit bit clock. Or Test selection
pin in Test Mode
5V tolerant
DSP0 GPIO6
With internal pull_up, on
at reset
Input
46
TST3_LRCKR
B
SAI0 Transmit LeftRight clock; SAI1
Receive and Transmit bit clock. Or Test
selection pin in Test Mode
DSP0 GPIO7
5V tolerant
With internal pull_up, on
at reset
Input
47
VDD
P
Digital Core Power Supply
1.8V
48
GND
G
Digital Core Power Ground
49
DBCK0
B
Debug Port Clock of DSP0 (DBCK0)
DSP0 GPIO9
5V tolerant
With internal pull_down,
on at reset
Input
50
DBIN0
B
Debug Port Data Input of DSP0 (DBIN0)
DSP0 GPIO11
5V tolerant
With internal pull_down,
on at reset
Input
51
DBRQ0
B
Debug Port Request of DSP0 (DBRQ0)
DSP0 GPIO
5V tolerant
With internal pull_up, on
at reset
Input
52
DBOUT0
B
Debug Port Data Output of DSP0
(DBOUT0)
DSP0 GPIO10
5V tolerant
With internal pull_up, on
at reset
Input
53
GNDH
G
3.3V IO Ring Power Ground (Debug
Interface, GPIO)
54
VDDH
P
3.3V IO Ring Power Supply (Debug
Interface, GPIO)
55
DBCK1
B
DSP1 Debug Port Clock (DBCK1) if HS3I
master mode, else High Speed
Synchronous Serial Interface (HS3I)
Channel3 Data
DSP1 GPIO9
5V tolerant
With internal pull_down,
on at reset
Input
56
DBIN1
B
DSP1 GPIO or DSP1 Debug Port Data
In (DBIN1) if HS3I master mode, else
High Speed Synchronous Serial
Interface (HS3I) Channel2 Data i
DSP1 GPIO11
5V tolerant
With internal pull_down,
on at reset
Input
57
DBRQ1
B
DSP1 GPIO or DSP1 Debug Port
Request (DBRQ1) if HS3I master mode,
else High Speed Synchronous Serial
Interface (HS3I) Channel1 Data
5V tolerant
With internal pull_up, on
at reset
Input
8/31
TDA7580
PIN DESCRIPTION (continued)
N°
Name
Type
Description
Notes
58
DBOUT1
B
DSP1 GPIO or DSP1 Debug Port Data
Out (DBOUT1) if HS3I master mode,
else High Speed Synchronous Serial
Interface (HS3I) clock
DSP1 GPIO10
5V tolerant
With internal pull_up, on
at reset
59
VDD
P
Digital Core Power Supply
1.8V
60
GND
G
Digital Core Power Ground
61
VDDISO
P
3.3V N-isolation biasing supply
62
GNDH
G
3.3V IO Ring Power Ground (Modulator
digital section)
63
VDDH
P
3.3V IO Ring Power Supply (Modulator
digital section)
64
VDDSD
P
3.3V IFADC Modulator Analogue Power
Supply
I/O TYPE
P: Power Supply from Voltage regulator
G: Power Ground from Voltage regulator
A: Analogue I/O
I: Digital Input
O: Digital Output
B: Bidirectional I/O
After
Reset
Input
Clean 3.3V supply to be
star-connected to
voltage regulator
Clean Power Supply, to
be star-connected to
3.3V voltage regulator
I/O DEFINITION AND STATUS
Z: high impedance (input)
O: logic low output
X: undefined output
1: logic high output
Output PP: Push-Pull/ OD: Open-Drain
9/31
TDA7580
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Parameter
Comment
Min.
Typ.
Max.
Unit
VDD
1.8V Power Supply Voltage
Core Power Supply
1.7
1.80
1.9
V
VDDH
3.3V Power Supply Voltage (1)
IO Rings Power Supply (with GNDH)
3.15
3.30
3.45
V
VOSC
3.3V Power Supply Voltage (1)
Oscillator Power Supply (GNDOSC)
3.15
3.30
3.45
V
VDDSD
3.3V Power Supply Voltage (1)
IF ADC Power Supply (with GNDSD)
3.15
3.30
3.45
V
VMTR
1.8V Power Supply Voltage
DAC-Keying and Tuner clock
Power Supply (with GNDMTR)
1.7
1.80
1.9
V
Max.
Unit
Note: 1. VDDH, VOSC, VDDSD are also indicated in this document as VDD3. All others as VDD.
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Typ.
lilh
Low Level Input Current
I/[email protected] (absolute value)
Vi = 0V (notes 1, 2)
without pull-up-down device
1
µA
lihh
High Level Input Current
I/[email protected] (absolute value)
Vi = VDD3 (notes 1, 2)
without pull-up-down device
1
µA
lil
Low Level Input Current
I/[email protected] (absolute value)
Vi = 0V (notes 1, 3, 4)
without pull-up-down device
1
µA
lih
High Level Input Current
I/[email protected] (absolute value)
Vi = VDD (notes 1, 3, 4)
without pull-up device
1
µA
Iipdh
Pull-down current I/Os @ VDD3
Vi = VDD3 (note 5)
with pull-down device
Iopuh
Pull-up current I/Os @ VDD3
Iopul
Iaihop
Iacm
Iail
Iain
Iaik
Ioz
10/31
3.2
6.6
10.0
µA
Vi = 0V(note 6)
with pull-up device
-10.0
-6.6
-3.2
µA
Pull-up current I/Os @ VDD
Vi = 0V (note 3)
with pull-up device
-5.4
-3.6
-1.8
µA
Analogue pin sunk/drawn current
on pin1 and pin 6
Vi = VDD3
0.95
1.25
1.55
mA
Vi = 0V
-6.25
-5.0
-3.75
mA
Vi = VDD3
1.5
2.0
2.5
mA
Vi = 0V
-2.5
-2.0
-1.5
mA
Vi = VDD3
3.75
5.0
6.25
mA
Vi = 0V
-1.55
-1.25
-0.95
mA
Vi = VDD3
24
32
40
µA
Vi = 0V
-40
-32
-24
µA
Vi = VDD
0.8
1.2
1.6
mA
Vi = 0V (spec absolute value)
1
µA
Vo = 0V or VDD3 (note 1)
without pull up/down device
1
µA
Analogue pin sunk/drawn current
on pin 2
Analogue pin sunk/drawn current
on pin 3
Analogue pin sunk/drawn current
on pin 4 and pin 5
Analogue pin sunk/drawn current
on pin 15
Tri-state Output leakage
TDA7580
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS (continued)
Symbol
IozFT
Ilatchup
Vesd
Parameter
Test Condition
Min.
Typ.
Max.
Unit
1
µA
3
µA
5V Tolerant Tri-state Output
leakage (without pull up/down
device)
Vo = 0V or Vdd (note 1)
I/O latch-up current
V < 0V, V > Vdd
200
mA
Electrostatic Protection
Leakage, 1µA
2000
V
Vo = 5.5V
1
Note: 1. The leakage currents are generally very small, <1nA. The value given here, 1µA, is the maximum that can occur after an Electrostatic Stress on the pin.
2. On pins:17 to 20,23 to 26,29 to 33,36 to 39,42 to 46,49 to 52,55 to 58.
3. On pins: 13 and 14.
4. Same check on the analogue pin 15 (phisically without pull-up-down)
5. On pins:25, 26,32,49,50,55,56
6. On pins:17 to 20,23 to 24,29 to 31,33,36 to 39,42 to 46,51, 52,57, 58
LOW VOLTAGE CMOS INTERFACE DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Condition
Vil
Low Level Input Voltage
1.70V<=VDD<=1.90V
Vih
High Level Input Voltage
1.70V<=VDD<=1.90V
Vol
Low level output Voltage
Iol = 4mA (notes 1)
Voh
High level output Voltage
I ol = -4mA (notes 1)
Min.
Typ.
Max.
Unit
0.3*VDD3
V
0.8*VDD3
V
0.15
VDD-0,15
V
V
Note: 1. It is the source/sink current under worst case conditions and reflects the name of the I/O cell according to the drive capability.
HIGH VOLTAGE CMOS INTERFACE DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Condition
Vil
Low Level Input Voltage
3.15V<=VDD3<=3.45V
Vih
High Level Input Voltage
3.15V<=VDD3<=3.45V
Vol
Low level output Voltage
Iol = XmA (notes 1 and 2)
Voh
High level output Voltage
I ol = -XmA (notes 1 and 2)
Min.
Typ.
Max.
Unit
0.8
V
2.0
V
0.15
VDD3-0.15
V
V
Note: 1. It is the source/sink current under worst case conditions and reflects the name of the I/O cell according to the drive capability
2. X=4mA for pins 17 to 20,29,30,32,36 to 39,42 to 46; X=8mA for pins 23 to 26,49 to 52,55 to 58.
CURRENT CONSUMPTION
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
120
200
mA
3
5
mA
IDD
Current through VDD Power
Supply
VDD=1.8V,VDD3=3.3V
All digital blocks working
IDDH
Current through VDDH Power
Supply
VDD=1.8V,VDD3=3.3V
All I/Os working with 5pF load
Current through VSD Power
Supply
VDD=1.8V,VDD3=3.3V
36
45
54
mA
Current through VOSC Power
Supply
VDD=1.8V,VDD3=3.3V
without quartz
5.5
8
10.5
mA
ISD
IOSCdc
11/31
TDA7580
CURRENT CONSUMPTION (continued)
Symbol
Parameter
Test Condition
IOSCac
Current through VOSC Power
Supply
VDD=1.8V,VDD3=3.3V
with quartz in FM mode
IMTR
Current through VMTR Power
Supply
VDD=1.8V,VDD3=3.3V
Min.
Typ.
Max.
Unit
11
14
17
mA
5
mA
Note: 74.1MHz internal DSP clock, at Tamb = 25°C. Current due to external loads not included.
OSCILLATOR CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
FOSCFM
Oscillator Frequency (XTI/XTO)
VOSC @ 3.3V
74.1
MHz
FOSCAM
Oscillator Frequency (XTI/XTO)
VOSC @ 3.3V
74.106
MHz
Notes: 1. The accuracy of this figure only depends on the quartz frequency precision: high stability oscillator
QUARTZ CHARACTERISTICS
Parameter Name
Parameter Value
Temperature range
-55°C ÷ +125°C
Adjustment tolerance (@ 25°C ± 3°C)
+/-20ppm
Frequency stability (-20°C ÷ +70°C)
+/-50ppm
Aging @ 25°C
5ppm/year
Shunt (static) capacitance (Co)
<6pF
Packages (holders)
UM-1; HC-52U; HC-35; HC-48U; HC-49U; HC-50U; HC-51U
Mode of oscillation
AT-3rd
Resonance resistance (ESR)
<35ohm
Oscillation Frequency (without external load)
≥74108000 Hz
Oscillation Frequency (12pF parallel load)
target 74.1MHz
DSP CORE
Symbol
FdspMax
Parameter
Maximum DSP clock frequency
Test Condition
At 1.7V Core Power Supply and
125°C junction temperature
Min.
Typ.
Max.
81.5
Unit
MHz
FM STEREO DECODER CHARACTERISTICS
Symbol
Parameter
a_ch
Channel Separation
THD
Total Harmonic Distortion
(S+N)/N
12/31
Signal plus Noise to Noise ratio
Test Condition
Min.
Typ.
50
Max.
Unit
dB
0.02
%
80
dB
TDA7580
SAMPLE RATE CONVERTER
MCK = 18.525MHz, Fsin/Fsout = 0.820445366
Symbol
THD+N
Parameter
Total Harmonic Distortion +
Noise
DR
Dynamic Range
IPD
Interchannel Phase Deviation
Test Condition
Typ.
Max.
Unit
20Hz to 20kHz, Full Scale, 16 bit inp.
-95
dB
20Hz to 20kHz, Full Scale, 20 bit inp.
-98
dB
1 kHz
Full Scale, 16 bit inp.
-95
dB
10 kHz
Full Scale, 16 bit inp.
-95
dB
dB
1 kHz
Full Scale, 20 bit inp.
-105
10 kHz
Full Scale, 20 bit inp
-98
dB
1 kHz -60 dB - 16 bit inp.,A-Weighted
98
dB
1 kHz -60 dB - 20 bit inp.,A-Weighted
120
fc
Cutoff Frequency
@ -3 dB
Rp
Pass Band Ripple
from 0 to 20kHz
Rs
Stopband Attenuation
@24.1kHz
Tg
Group Delay
Fsout = 44.1 kHz
Sampling Frequency In/Out Ratio
Fsout = 44.1 kHz
Fratio
Min.
dB
0
Degree
0.01
dB
Hz
-0.01
-120
dB
µs
540
0.7
1.05
13/31
TDA7580
POWER ON TIMING
Figure 1. Power on and boot sequence using I2C
VDD3
VDD
INT
RESETN
IFS SLAVE=1
IFS MASTER=0
ADDR_SD
PROTSEL_SS
RDS_CS
GPIO_SDO1
I2C/SPI SLAVE=1
I2C/SPI MASTER=0
TST1_SDI1
Boot
SDA_MOSI
tint
RDS init
trhd
SW download
Data
Tuner data
tdat
tsw
trsu
treson
ttun
tseq
Figure 2. Power on and boot sequence using SPI
VDD3
VDD
INT
RESETN
IFS SLAVE=1
IFS MASTER=0
ADDR_SD
PROTSEL_SS
RDS_CS
GPIO_SDO1
I2C/SPI SLAVE=1
I2C/SPI MASTER=0
TST1_SDI1
Boot
SDA_MOSI
tint
RDS init
trhd
SW download
tdat
tsw
trsu
treson
14/31
tseq
Data
Tuner data
ttun
TDA7580
Timing
tint
treson
Description
Value
Unit
Maximux delay for INT signal
1
ms
Minimum RESETN hold time at 0 after the start-up
22
ms
trsu
Minimum data set-up time
1
µs
trhd
Minimum data hold time
1
µs
tseq
Minimum wait time after boot
4
ms
tsw
Minimum wait time before downloading the Program Software
1
µs
ttun
Minimum wait time before downloading the software to the FE
1
µs
tdat
Minimum wait time before using interface protocols
1
µs
15/31
TDA7580
SAI INTERFACE
Figure 3. SAI Timings
Valid
SDI0-1
LRCKR
Valid
SCKR
(RCKP=0)
tlrs
tdt
tsdis
tlrh
tsdih
tsckpl
tsckph
tsckr
Timing
Description
TDSP
Internal DSP Clock Period (Typical 1/74.1MHz)
tsckr
Minimum Clock Cycle
Value
Unit
13.495
ns
32*TDSP
ns
tdt
SCKR active edge to data out valid
40
ns
tlrs
LRCK setup time
16
ns
tlrh
LRCK hold time
9
ns
tsdid
SDI setup time
16
ns
tsdih
SDI hold time
9
ns
tsckph
Minimum SCK high time
0.5*tsckr
ns
tsckpl
Minimum SCK low time
0.5*tsckr
ns
Note T DSP = DSP master clock cycle time = 1/FDSP
Figure 4. SAI protocol when RLRS=0; RREL=0; RCKP=1; RDIR=0
LRCKR
LEFT
RIGHT
SCKR
SDI0-1
16/31
LSB(n-1)
MSB(n)
MSB-1(n)
MSB-2(n)
TDA7580
Figure 5. SAI protocol when RLRS=1; RREL=0; RCKP=1; RDIR=1.
LEFT
LRCKR
RIGHT
SCKR
SDI0-1
MSB(n-1)
LSB(n)
LSB+1(n)
LSB+2(n)
Figure 6. SAI protocol when RLRS=0; RREL=0; RCKP=0; RDIR=0.
LEFT
LRCKR
RIGHT
SCKR
SDI0-1
LSB(n-1)
MSB(n)
MSB-1(n)
MSB-2(n)
Figure 7. SAI protocol when RLRS=0; RREL=1; RCKP=1; RDIR=0.
LRCKR
LEFT
RIGHT
SCKR
SDI0-1
LSB(n-1)
MSB(n)
MSB-1(n)
MSB-2(n)
17/31
TDA7580
SPI INTERFACE
Figure 8. SPI Timings
Valid
SS
MISO
MOSI
Valid
SCL
(CPOL=0,CPHA=0)
tsetup
tdtr
tsssetup
thold
tsshold
tsclkl
tsclkh
tsclk
Symbol
TDSP
Description
Internal DSP Clock Period (Typical 1/74.1MHz)
Value
Unit
13.495
ns
12*TDSP
ns
MASTER
tsclk
Minimum Clock Cycle
tdtr
Minimum Sclk edge to MOSI valid
40
ns
tsetup
Minimum MISO setup time
16
ns
thold
Minimum MISO hold time
9
ns
tsclkh
Minimum SCK high time
0.5*tsclk
ns
tsclkl
Minimum SCK low time
0.5*tsclk
ns
tsssetup
Minimum SS setup time
40
ns
tsshold
Minimum SS hold time
25
ns
12*TDSP
ns
SLAVE
tsclk
Minimum Clock Cycle
tdtr
Minimum Sclk edge to MOSI valid
40
ns
tsetup
Minimum MOSI setup time
16
ns
thold
Minimum MOSI hold time
9
ns
tsclkh
Minimum SCK high time
0.5*tsclk
ns
18/31
TDA7580
Symbol
Description
Value
Unit
tsclkl
Minimum SCK high low
0.5*tsclk
ns
tsssetup
Minimum SS setup time
40
ns
tsshold
Minimum SS hold time
20
ns
Figure 9. SPI Clocking Scheme
SS(#17)
SCK(#20)
(CPOL=0,CPHA=0)
SCK(#20)
(CPOL=0,CPHA=1)
SCK(#20)
(CPOL=1,CPHA=0)
SCK(#20)
(CPOL=1,CPHA=1)
MISO(#19)
MOSI(#18)
MSB
6
5
4
3
2
1
0
19/31
TDA7580
INTER PROCESSOR TRANSPORT INTERFACE FOR ANTENNA DIVERSITY
Figure 10. High Speed Synchronous Serial Interface - HS3I
Master Bit Clock
Master Data Out
M2
M3
256 cycles of 74.1MHz
Master Synch
Slave Data Out
S0
S1
S2
S3
tmbcc
tmbco
tmbcs
tsdos
Master Bit Clock
Master Data Out
Master Synch
Slave Data Out
Timing
Description
Value
Unit
32*TDSP
ns
TDSP
Internal DSP Clock Period (Typical 1/74.1MHz)
tmbcc
MBC minimum Clock Cycle
tmbco
MBC active edge to master data out valid
4
ns
tmbcs
MBC active edge to master synch valid
4
ns
tsdos
Slave Data Out setup time
6
ns
Note T DSP = DSP master clock cycle time = 1/FDSP
20/31
TDA7580
I2C TIMING
Figure 11. DSP and RDS I2C BUS Timings.
Symbol
Parameter
Test Condition
Standard Mode
I2C BUS
Fast Mode
I2C BUS
Unit
Min.
Max.
Min.
Max.
0
100
0
400
kHz
FSCL
SCLl clock frequency
tBUF
Bus free between a STOP and
Start Condition
4.7
–
1.3
–
µs
tHD:STA
Hold time (repeated) START
condition. After this period, the
first clock pulse is generated
4.0
–
0.6
–
µs
tLOW
LOW period of the SCL clock
4.7
–
1.3
–
µs
tHIGH
HIGH period of the SCL clock
4.0
–
0.6
–
µs
tSU:STA
Set-up time for a repeated start
condition
4.7
–
0.6
–
µs
tHD:DAT
DATA hold time
0
–
0
0.9
µs
tR
Rise time of both SDA and SCL
signals
Cb in pF
–
1000
20+
0.1Cb
300
ns
tF
Fall time of both SDA and SCL
signals
Cb in pF
–
300
20+
0.1Cb
300
ns
tSU;STO
Set-up time for STOP condition
4
–
0.6
–
µs
tSU:DAT
Data set-up time
250
--
--
100
ns
–
400
–
400
pF
Cb
Capacitive load for each bus line
21/31
TDA7580
FUNCTIONAL DESCRIPTION
The TDA7580 IC is a complete solution for high performance FM/AM Car Radio receivers, and has high processing power to allow Audio processing of both internal and external Audio source.
The processing engine is made of programmable DSP, with separate banks of Program and Data RAMs. In addition a number of hardware modules (peripherals) which help in the algorithm implementation of channel equalization, and FM/AM Baseband post-processing.
The HW architecture allows to perform Dual Tuner Diversity. In this case two TDA7580 are needed: one device
must be configurated as Master, generates the clock and controls the main data interfaces. The second device
becomes Slave and converts the second IF path, as well as helps the first chip as co-processor.
24-BIT DSP CORE
Some capabilities of the DSP are listed below:
■ Single cycle multiply and accumulate with convergent rounding and condition code generation
■ 24 x 24 to 56-bit MAC Unit
■ Double precision multiply
■ Scaling and saturation arithmetic
■ 48-bit or 2 x 24-bit parallel moves
■ 64 interrupt vector locations
■ Fast or long interrupts possible
■ Programmable interrupt priorities and masking
■ Repeat instruction and zero overhead DO loops
■ Hardware stack capable of nesting combinations of 7 DO loops or 15 interrupts/subroutines
■ Bit manipulation instructions possible on all registers and memory locations, also Jump on bit test
■ 4 pin serial debug interface
■ Debug access to all internal registers, buses and memory locations
■ 5 word deep program address history FIFO
■ Hardware and software breakpoints for both program and data memory accesses
■ Debug Single stepping, Instruction injection and Disassembly of program memory
DSP PERIPHERALS
■ Clock Generation Unit (CGU)
■ Stereo Decoder (HWSTER)
■ Serial Audio Interface (SAI)
■ Tuner AGC Keying DAC (KEYDAC)
■ Programmable I/O Interface (I2C/BSPI)
■ Asynchronous Sample Rate Converter (ASRC)
■ IF Band Pass Sigma Delta Modulator (IFADC)
■ Digital Down Converter (DDC)
■ Discriminator (CORDIC)
■ RDS
3
■ Tuner Diversity HS I
22/31
TDA7580
DSP PERIPHERALS
The peripherals are mapped in the X-memory space.
Most of them can be handled by interrupt, with software programmable priority.
Peripherals running at very high rate have direct access to X and Y Data Bus for very fast movement from or to
the core, by mean of single cycle instruction.
CLOCK GENERATION UNIT (CGU) and OSCILLATOR
This unit is responsible for supplying all necessary clocks and synchronization signals to the whole chip.
The control status register of this unit contains information about the current working mode (FM,AM,oscillator
[master mode] or clock buffer [slave mode]), the tuner clock frequency setting, the general setup of the oscillator.
This last function is performed inside the CGU, that establishes -using a self-trimming algorithm- which is the
current that can bias the oscillator: this feature let the oscillator be independent from process parameters variation. The values of bias current are stored in the control status register of the CGU: 4 bit for the coarse current
steps and 6 bit for the fine current steps. The bits relative to the fine current steps can be anyway corrected
(written) by the DSP to perform the SW frequency trimming (+/-80Hz per step in FM; +/-250Hz in AM).
It sets up the oscillator which works off a quartz crystal of nominally 74.1MHz, generating very low distortion,
thus improving the Electro Magnetic Interference. In FM mode the oscillator generates 74.1MHz, meanwhile in
AM mode this frequency is shifted to 74.106MHz. The quartz characteristics are defined earlier in this document.
In Slave mode the oscillator behaves as a buffer: the chip can be then driven using an external clock. The clock
divider, placed in this unit, gives the tuner the reference clock (100KHz in FM and AMUS, 18KHz in AMEU).
STEREO DECODER (HWSTER)
The fully digital hardware stereo decoder does all the signal processing necessary to demodulate an FM MPX
signal which is prepared by the channel equalization algorithm in the digital IF sampling device.
It makes up of pilot tone dependent Mono/Stereo switching as well as stereoblend and highcut.
Selectable deemphasis time constant allow the use of this module for different FM radio receiver standards.
There are built-in filters for field strength processing. In order to obtain the maximum flexibility the field strength
processing and noise cancellation, however, are implemented as software inside the programming DSP, which
has to provide control signals for the stages softmute, stereoblend, and highcut.
SERIAL AUDIO INTERFACE (SAI)
The two SAI modules have been embedded in such a way great flexibility is available in their use.
The two modules are fully separate and they each have a Receive and a Transmit channel, as well as they can
be selected as either master or slave.
The bit clocks and Left&Right clocks are routed through the pins, so the audio interface can be chosen to be
adapted to a large variety of application.
One SAI transmit channel can have the Asynchronous Sample Rate Converter in front, thus separate different
audio rate domains.
Additional feature are:
■ support of 16/24/32 bit word length
■
programmable left/right clock polarity
■
programmable rising/falling edge of the bit clock for data valid
■
programmable data shift direction, MSB or LSB received/transmitted first
23/31
TDA7580
I2C INTERFACES
The inter Integrated Circuit bus is a single bidirectional two-wire bus used for efficient inter IC control. All I2C
bus compatible devices incorporate an on-chip interface which allows them communicate directly with each other via the I2C bus.
Every component hooked up to the I 2C bus has its own unique address whether it is a CPU, memory or some
other complex function chip. Each of these chips can act as a receiver and /or transmitter on its functionality.
Two pins are used to interface both I2C of the DSP and RDS, which have different internal I2C address, thus
reducing the on-board pin interconnections.
SERIAL PERIPHERAL INTERFACES
The DSP and RDS can have this serial interface, alternative to the I2C one. DSP and RDS SPI modules have
separate pin for chip select.
The DSP SPI has a ten 24bit-words deep FIFO for both receive and transmit sections, which reduces DSP processing overhead even at high data rate.
The serial interface is needed to exchange commands and data over the LAN. During an SPI transfer, data is
transmitted and received simultaneously. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slave SPI device.
When an SPI transfer occurs an 8-bit word is shifted out one data pin while another 8-bit character is simultaneously shifted in a second data pin.The central element in the SPI system is the shift register and the read data
buffer. The system is single buffered in the transfer direction and double buffered in the receive direction.
HIGH SPEED SERIAL SYNCHRONOUS INTERFACE (HS3I)
The High Speed Serial Synchronous Interface is a module to send and receive data at high rate (up to 9.25Mbit/
s per channel) in order to exchange data between 2 separate TDA7580 chip.
The exchanged data are related to signals that are used to increase reception quality in Car Radio systems,
which make use of Antenna Diversity based upon two separate antenna and tuner sections.
The channel synchronization clock has a programmable duty cycle, so to reduce in-band harmonics noise.
TUNER AGC KEYING DAC (KEYDAC)
This DAC provides the front-end tuner with an analogue signal to be used to control the Automatic Gain Controlled stage, thus giving all time the best voltage dynamic range at the IFADC input.
ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC)
This hardware module provides a very flexible way to adapt the internal audio rate, to the one of an external
source. It does not require further work off the DSP.
There is no need to explicitly configure the input and the output sample rates, as the ASRC solves this problem
with an automatic Digital Ratio Locked Loop.
Main features are:
■ Automatic Tracking of Sample Frequency
■
Fully Digital Ratio Locked Loop
■
Sampling Clock Jitter Rejection
■
Up-conversion up to 1:2 Ratio
■
Linear Phase
24/31
TDA7580
IF BAND PASS SIGMA DELTA ANALOGUE TO DIGITAL CONVERTER (IFADC)
The IFADC is a Band Pass Sigma Delta A to D converter with sampling rate of 37.05MHz (nominal) and notch
frequency of 10.7MHz. The structure is a second order switched capacitor multi bit modulator with self calibration algorithm to adjust the notch frequency.
The differential ended input allows 4.0Vpp voltage dynamic range, and reduces the inferred noise back to the
previous stage (tuner), and in turn gives high rejection to common mode noises.
The high linearity (very high IMD) is needed to fulfill good response of the channel equalization algorithm.
Low thermal and 1/f noise assures high dynamic range.
DIGITAL DOWN CONVERTER (DDC)
The DDC module allows to evaluate the in-phase and quadrature components of the incoming digital IF signal.
The I and Q computation is performed by the DDC block, which at the same time shifts down to 0-IF frequency
the incoming digital signal.
After the down conversion the rate is still very high (at the 37.05MHz rate); a SincK filter samples data down by
a factor of 32, decreasing it to 1.1578MHz. An additional decimation is performed by the subsequent FIR filters,
thus lowering the data rate at the final 289.45kHz, being the MPX data rate.
RDS
The RDS block is an hardware cell able to process RDS/RBDS signal, intended for recovering the inaudible
RDS/RBDS information which are transmitted by most of FM radio broadcasting stations.
It comprises of the following:
■ Demodulation of the European Radio Data System (RDS)
■
Demodulation of the US Radio Broadcast Data System (RDBS)
■
Automatic Group and Block synchronisation with flywheel mechanism
■
Error Detection and Correction
■
RAM buffer with a storage capacity of 24 RDS blocks and related status information
■
I2C and SPI interface, with pins shared with the DSP I2C/SPI
After filtering the oversampled MPX signal, the RDS/RDBS demodulator extracts the RDS Data Clock, RDS
Data signal and the Quality information.
The following RDS/RBDS decoder synchronizes the bitwise RDS stream to a group and block wise information.
This processing also includes error detection and error correction algorithms.
In addition, an automatic flywheel control avoids exhausting data exchange between RDS/RDBS processor and
the host.
25/31
TDA7580
APPLICATION DIAGRAM
Hereafter are some examples of Applications in which the TDA7580 can be used. They are just basic references
as the device can operate.
49
50
51
52
53
54
55
56
57
58
59
60
61
62
1
63
64
Figure 12. Radio Mode with external Slave Audio DAC
48
2
47
3
TST3_LRCKR 46
TST2_SCKR 45
LRCK_LRCKT 44
4
5
6
7
SCLK_SCKT 43
SDO0 42
1
8
8
41
2
7
3
6
4
5
TDA7580
9
40
10
TDA7535
Dual DAC
32
31
30
29
28
27
26
25
24
33
23
34
16
22
35
15
21
14
20
36
19
GPIO_SDO1 37
13
18
12
17
11
TST1_SDI1 39
TST4_SDI0 38
Fs=36kHz
In this mode an external Slave Stereo DAC, like the ST TDA7535, can be easily connected and the
TDA7580 outputs the Audio from Radio station at 36kHz rate.
49
50
51
52
53
54
55
56
57
58
59
60
61
62
1
63
64
Figure 13. Radio Mode with external Master Audio Device
48
47
2
TST3_LRCKR
TST2_SCKR
LRCK_LRCKT
SCLK_SCKT
SDO0
3
4
5
6
7
8
44
1
43
2
42
41
TDA7580
9
46
45
34
16
33
27
26
25
24
23
22
21
20
19
External Audio Receiver
with its owned audio rate Fs
32
35
15
31
14
30
36
29
13
28
12
TST1_SDI1 39
TST4_SDI0 38
GPIO_SDO1 37
11
18
4
40
10
17
3
Fs
An external digital Audio device is connected externally as a digital audio master, and the internal
TDA7580 Sample Rate Converter is responsible for the conversion from internal 36kHz to the external
Audio Rate.
26/31
TDA7580
49
50
51
52
53
54
55
56
57
58
59
60
61
62
1
63
64
Figure 14. Audio Mode with external Slave Audio Device
48
2
47
3
TST3_LRCKR 46
4
TST2_SCKR
LRCK_LRCKT
SCLK_SCKT
SDO0
5
6
7
8
TDA7580
9
CD Player
Fs=44.1kHz
45
44
43
42
1
8
41
2
7
40
3
6
4
5
Fs=44.1kHz
1
8
13
36
2
7
14
35
3
6
15
34
4
5
16
33
TDA7535
Analog In
32
28
27
26
25
24
23
22
21
20
19
18
17
31
GPIO_SDO1 37
30
12
29
11
TST1_SDI1 39
TST4_SDI0 38
10
ADC
The 2 stereo channel Serial Audio Interface of the TDA7580 chip allows a very flexible application in which
external Audio Source/Sinks can be connected.
The example shows an external CD player digital output giving the main Fs audio rate of the whole system.
This rate is also the one of the external DACs and an ADC, being configured as slave.
27/31
TDA7580
ELECTRICAL APPLICATION SCHEME
The following application diagram must be considered an example. For the real application set-up refers the
application notes are necessary
.
28/31
TDA7580
PACKAGE MARKING
29/31
TDA7580
mm
DIM.
MIN.
inch
TYP.
MAX.
A
MIN.
TYP.
1.60
A1
0.05
A2
1.35
B
C
0.063
0.15
0.002
0.006
1.40
1.45
0.053
0.055
0.057
0.18
0.23
0.28
0.007
0.009
0.011
0.12
0.16
0.20
0.0047 0.0063 0.0079
D
12.00
0.472
D1
10.00
0.394
D3
7.50
0.295
e
0.50
0.0197
E
12.00
0.472
E1
10.00
0.394
E3
7.50
0.295
L
0.40
0.60
L1
0.75
OUTLINE AND
MECHANICAL DATA
MAX.
0.0157 0.0236 0.0295
1.00
0.0393
TQFP64
0°(min.), 7°(max.)
K
D
D1
A
D3
A2
A1
48
33
49
32
0.10mm
E
E1
E3
B
B
Seating Plane
17
64
1
16
C
L
L1
e
K
TQFP64
30/31
TDA7580
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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