TDA8205 NICAM QPSK DEMODULATOR HIGHLY INTEGRATED TWO CHIP SOLUTION FOR NICAM DEMODULATION (using TDA8204 decoder) AUTOMATIC DUAL STANDARD DEMODULATION 6.552MHz FOR I SYSTEM 5.85MHz FOR B/G SYSTEM 40dB RANGE AGC SINGLE CRYSTAL OPERATION NICAM 728 DATA AND CLOCK RECOVERY LOW PASS FILTER FOR PWM CODED AUDIO SIGNALS AND J-17 DE-EMPHASIS AUTOMATIC FM MONO SELECTION BY RESERVE SOUND SWITCH FUNCTION VERSATILE AUDIO SWITCHING MATRIX AUTOMATIC MUTE FUNCTION DESCRIPTION The TDA8205 is essentially divided into two signal processing sections. The first section handles all the NICAM signal acquisition, the QPSK demodulator and clock and data recovery circuits. The key point to note about this section is the dual frequency synthesiser. By use of only one quartz crystal, the IC is able to demodulate QPSK signals from either system I or system B/G in an automatic way. The second section of the TDA8205 manages the analog parts of the twin digital-to-analog converters (DACs) and all filtering and audio switching downstream of the DACs. A simple serial bus from the TDA8204 allows control of the switch functions by the CTV system microcontroller. October 1993 SHRINK 42 (Plastic Package) ORDER CODE : TDA8205 PIN CONNECTIONS GND 1 42 LF1 XC1 2 41 LF2 XC2 3 40 XK1 DF2 4 39 VCC DF1 5 38 EAIR BG IN 6 37 EAIL I IN 7 36 SAIR AGC 8 35 SAIL V CC 9 34 MAI V DD 10 33 CAP LFIL1 11 32 AMOR RG 12 31 AMOL GND 13 30 DC2 RFIL1 14 29 DC1 RESET 15 28 AOR VDD 16 27 AOL SERI 17 26 GND DACDL 18 25 MMO DACDR 19 24 TEST GND 20 23 NDO CK11648 21 22 CK728 8205-01.EPS . . .. .. . .. 1/8 TDA8205 Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Pin Name GND XC1 XC2 DF2 DF1 BGIN IIN AGC VCC VDD LFIL1 RG GND RFIL1 RESET VDD SERI DACDL DACDR GND CK11648 Function Ground Optional Crystal Optional Crystal Data Filter 2 (eye monitor) Data Filter 1 (eye monitor) System B/G Input System I Input AGC Filter Capacitor +12V Supply +5V Supply Left Filter 1 (J-17 De-emphasis) Gain Setting Resistor for DAC Ground Right Filter 1 (J-17 De-emphasis) Reset Chip +5V Supply Interchip Serial Bus Input DAC Data Left Input DAC Data Right Input Ground 11.648MHz Clock Output Pin No 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin Name CK728 NDO TEST MMO GND AOL AOR DC1 DC2 AMOL AMOR CAP MAI SAIL SAIR EAIL EAIR VCC XK1 LF2 LF1 Function 728kHz Clock Intput NICAM Data Output To be connected to GND Matrix Mute Out Ground Audio Output Left Audio Output Right Decoupling 1 Decoupling 2 Audio Mutable Output Left Audio Mutable Output Right Decoupling Capacitor Mono Audio Input Stereo Audio Input Left Stereo Audio Input Right External Audio Input Left External Audio Input Right +12V Supply 11.648MHz Crystal Loop Filter 2 Loop Filter 1 8205-01.TBL PIN ASSIGMENT DF2 LF1 LF2 NDO CK728 DACDL LFIL1 MAI SAIR AMOL AMOR EAIL EAIR 4 42 41 23 22 21 19 18 11 34 35 36 31 32 37 38 SAIL DF1 DACDR AGC 5 VDD 8 VDD 9 10 16 39 VCC VCC CK11648 BLOCK DIAGRAM MUTE IIN 7 SWITCH AGC CLOCK QSPSK DAC & DATA DEMOD 27 AOL LPF RECOVERY BG IN 6 SWITCH DAC MATRIX 28 AOR SWITCH 29 DC1 30 DC2 LPF DUAL FREQ TEST 24 SYNTHESISER 25 MMO RESET 15 SERIAL TDA8205 1 13 20 GND GND GND 26 GND 2 3 40 XC1 XC2 XK1 12 14 33 17 RG RFIL1 CAP SERI BLOCK DIAGRAM DESCRIPTION The QPSK signal enters the IC via two inputs after passing through two external bandpass filters at the relevant frequencies of 6.552MHz and 5.85MHz for system I and B/G respectively. The two inputs enter a source selection switch and pass immediately to an AGC block which has a total range of 40dB. The resulting levelled signal passes 2/8 to the QPSK demodulator which recovers the NICAM 728Kb/s data stream by means of carrier and clock recovery circuits. Carrier recovery is achieved with a baseband remodulator which consists of a phase locked loop with a switchable phase detector. This allows it to lock to one of four possible phases of the QPSK 8205-02.EPS INTERFACE TDA8205 carrier without disruption due to the modulation. Dual frequency operation is made possible by synthesising the carrier reference frequency thus saving the need for two extra crystals. Dual VCXO can also be software selected (SYN bit of CR3 in TDA8204) with external crystal (Pin XC1/XC2) for new standards. Selection between XC1 and XC2 is done with bit "IBG" in CR3 register of TDA8204 (IBG = 0 XC1 selected, IBG = 1 XC2 selected). The standards switch controls operation of the QSPK demodulator at either 6.552MHz or 5.85MHz. This can be controlled via the I2C bus or the decoder set into automatic mode in which it determines the standard by alternately trying to lock to the two systems. On chip low pass filters recover the in-phase and quadrature data channels which are then sliced by comparators. The symbol clock is recovered from this data and used to sample and re-time it. The two data channels are then decoded and serialized to obtain the NICAM-728 data which is then passed on to the NICAM decoder in the TDA8204. After processing the NICAM into a digital bit-stream in the TDA8204, the data is passed back to the TDA8205 for the analog functions of the DACs to be performed. Conversion of the pulse width modulated bit streams to analog takes place and is followed by low pass filtering which removes high frequency quantising noise and performs J-17 de-emphasis. The DACs signal level can be adjusted to match the reserve sound signal level. 1VRMS maximum on Pins LFIL1/RFIL1 can be obtained by selection of appropriate resistor on Pin RG. Once the analog audio has been recovered, certain source switch functions are performed. If the NICAM signal fails and if the reserve sound flag (C4), of SRO register, is set the reserve sound switch automatically selects Mono Audio Input. If the reserve sound flag (C4) is reset, the reserve sound switch will not change and the audio outputs will be muted (DAC outputs muted). If the NICAM signal only carries data, Mono Audio Input is selected. The reserve sound switch can be forced to select Mono Audio Input via I2C bus, using Bit FS0 = 1 and FS1 =0 of CR3 Register. This can be used in the case of NICAM marginal reception. To select Stereo Left and Right Audio Input Bit FS0 = 0 and FS1 = 1 of CR3 Register must be selected. The outputs from this reserve sound switch are available on Audio mutable output left and right, and are internaly connected to the audio matrix. A simple audio switching matrix is provided internally for flexible control over the audio source and destination selection. Audio signal left and right coming from the reserve sound switch and the external audio input left and right can be switched to the audio outputs left and right . DAC and auxiliary audio outputs can be muted. An additional +6dB gain can be applied to raise the output levels to 2VRMS maximum. For more informat ion see Sof t wa re Specification chapter (III.5.3/TDA8204). The DAC outputs are automatically muted under the following conditions - loss of frame alignement - the bit error rate (Ber) is > error rate limit - NICAM signal is conveying M1 only. The right DAC is muted unless M1 has been selected to be on both DAC outputs. - NICAM signal is conveying data only. For test purposes, the DAC outputs can be unmuted by forcing the bi-directional mute Pin 25 of TDA8204 or via I2C bus. Parameter Supply Voltage Supply Voltage Total Power Dissipation Operating Temperature Range Storage Temperature Range Value 15 7 1.2 0, + 70 -20, + 150 Unit V V W o C o C THERMAL DATA Symbol Rth (j-a) Parameter Thermal Resistance Junction-Ambient Max. Value 67 Unit C/W o 3/8 8205-03.TBL Symbol VCC VDD Ptot Toper Tstg 8205-02.TBL ABSOLUTE MAXIMUM RATINGS TDA8205 ELECTRICAL CHARACTERISTICS (Tamb = 25oC, VCC = 12V, VDD = 5V, unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit SUPPLY VCC Supply Voltage Range 11.4 12 12.6 V VDD Supply Voltage Range 4.75 5 5.25 V ICC Supply Current 18 36 50 mA IDD Supply Current 10 18 42 mA 0.4 V DIGITAL PINS OUTPUTS CK11, NDO VOL VOH Low Level Output Voltage (I = -4mA) HIgh Level Output Voltage (I = 4mA) 0.7 VDD V MMO (open collector) VOL Low Level Output Voltage (I = -1mA) 0.4 V ILK High Level Output Current (leakage) ±2 µA INPUTS SERI, DACDL, DACDR, CK728 VIL Low Level Input Voltage VIH High Level Input Voltage ILK Input Leakage Current 0.8 0.6 VDD V V ±2 µA ANALOG PINS I-B/G SELECTOR VDC DC Bias Voltage 2.8 V RIN Input Resistance 10 kΩ CIN Input Capacitance 10 pF AGC VIN Input Voltage Range 10 200 1000 mVPP AGClv AGC Low Voltage (VIN = 1VPP) 2 VPP AGChv AGC High Voltage (VIN = 10mVPP) 11 V AGCta AGC Attack Time (VIN = 10mV to 1V, CAGC = 100nF) 15 ms AGCtd AGC Decay Time (VIN = 1V to 10mV, CAGC = 100nF) 220 ms QPSK DEMODULATOR (LF1) VDC DC Bias Voltage (SYN = 1) 1 5 10 V Kd Phase Detector Constant (no mod.) 33 µA/rad kv VCO Constant 3.5 MHz/V EYE DIAGRAM MONITORS (DF1, DF2) VDC DC Bias Voltage 2.5 V ROUT Output Resistance 1.2 kΩ VOUT Output Voltage (System I) 0.6 VPP 4/8 VDC DC Bias Voltage Kd Phase Detector Constant (all 1’s) kv VCXO Constant 2.5 V 7 µA/rad 4.4 kHz/V 8205-04.TBL CLOCK AND DATA RECOVERY (LF2) TDA8205 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Min. Typ. Max. Unit DAC AND FILTER (LFIL1, RFIL1) VDC DC Bias Voltage 2.5 V IOUT Output Current (RG = 5.6kΩ, DAC full scale) 340 µAPP VRG RG Pin DC Voltage 1.25 V AUDIO MATRIX (AOL, AOR, AMOL, AMOR) DAC SELECTED VOUT Output Voltage (1kHz at -11.75dB, J17 de-emphasis, RG = 5.6kΩ) S/N Relative to 0.5VRMS, noise measured with IEC-179 A-filter THD 1kHz at 0.5VRMS, RG = 5.6kΩ Crosstalk at 1kHz, 0.5VRMS Chm 0.39 0.5 60 70 0.05 0.63 dB 0.2 65 Maximum Channel Matching Error VRMS % dB 2 dB MONO OR STEREO AUDIO INPUT SELECTED (MAI, SAIL, SAIR) S/N Relative to 0.5VRMS, noise measured with IEC-179 A-filter THD 1kHz at 0.5VRMS 88 dB 0.02 % Crosstalk at 1kHz, 0.5VRMS Chm Maximum Channel Matching Error 75 8205-05.TBL STEREO AUDIO INPUT SELECTED dB 2 dB 5/8 10nF C1 R3 1.2k Ω R2 470Ω R4 470Ω T1 6.0MHz Q1 C2 10nF C3 10nF R6 33Ω BFP 1 3 40 C5 220pF R7 470Ω C4 1nF 4 39 R18 10k Ω 2 42 41 C22 10µF F1 6.552MHz C7 680pF R8 150Ω 220nF C8 C10 6.8nF R5 100Ω R9 8.2M Ω TRAP 8205-03.EPS NICAM SYS. I IN R1 8.2k Ω 100nF C7 R10 39kΩ C11 150pF X1 11.648MHz C9 120pF C12 18pF* 6 7 MON1 MON2 C6 220pF VCC 5 8 38 37 36 35 34 10 11 L1 10µH V DD Q2 30 R13 43k Ω 14 29 L2 10µH 13 C23 10µF 6.8nF C14 R12 5.6k Ω 12 TDA8205 31 C24 1µF C25 1µF 33 32 C13 100nF 9 IC1 C19 100nF R11 5.6k Ω * C12 value depends on X1 17 26 18 19 25 24 C21 10µF C16 10µF R20 22k Ω C15 6.8nF R17 330Ω C17 100nF 20 21 23 22 C18 100nF R15 5.6k Ω C26 220µF R14 43k Ω 15 16 28 27 C20 10µF R19 270 Ω R16 1MΩ 1 42 2 3 41 40 4 39 5 38 FM mono (forced) mute LED1 6 37 7 8 36 35 LK1 9 10 33 31 30 29 12 13 14 C28 100nF 11 TDA8204 32 15 16 17 28 27 26 18 25 Q1, Q2 : BC109 or BC550C F1 : TOKO TH316BQM2110QDAF (5VFP) T1 : Matsushita EFCS6R0MWS X1 : 11.648MHz Crystal NDK IC2 34 LK2 Language Selection AUDIO OUTPUT 19 24 21 22 Unmute DAC (forced) stereo dual mono single mono 20 23 ERROR MONITOR L R LED2 LED3 6/8 LED4 FM MONO IN TDA8205 APPLICATION DIAGRAMS Figure 1 : Stand Alone Application (I standard) R11 470Ω 5.5MHz T1 R14 1.2kΩ R13 470Ω R12 8.2kΩ R8 1.2kΩ R7 470Ω 6.0MHz T2 TRAP 8205-04.EPS 10nF C34 10nF C31 Q2 Q1 C25 220nF R5 470Ω TRAP NICAM SYS. I IN NICAM SYS. BG IN R6 8.2kΩ R27 8.2MΩ VCC R1 39kΩ R15 100Ω C36 10nF C35 10nF R9 100Ω C33 10nF C32 10nF R16 33Ω BFP F2 6.552MHz R10 33Ω BFP F1 5.85MHz C45 680pF R2 150Ω C26 120pF C11 100nF C12 100nF C13 100nF C14 10µF C15 10µF C16 1µF C17 1µF C18 10µF 1 3 C30 220pF R18 470Ω C38 1nF R17 470Ω C37 1nF R31 10kΩ 2 4 5 MON1 MON2 7 C29 220pF 6 8 TDA8205 Q3 VDD C44 220µF C40 6.8nF R19 5.6kΩ +5V +12V R20 43kΩ C5 10µF C1 10µF R21 43kΩ C20 10µF C42 100nF C6 100nF C2 100nF C7 100nF C3 100nF R33 22kΩ C41 6.8nF R22 5.6kΩ C43 100nF 10 11 12 13 14 15 16 17 18 19 20 21 C39 100nF 9 IC1 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 11.648MHz X1 C10 100nF C21 6.8nF C22 150pF C23 18pF * C9 100nF Left AUDIO OUTPUT C19 10µF VCC C8 100nF VDD VDD SEL1 SEL0 ERROR MONITOR 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19 20 21 TDA8204 USER BITS I 2 S BUS Q1, Q2, Q3 : BC109 or BC550C F1 : TOKO TH316 BQM 2080 QDAF (5VFP) F2 : TOKO TH316 BQM 2110 QDAF (5VFP) T1 : Matsushita EFCS5R5MWS T2 : Matsushita EFCS6R0MWS X1 / 11.648MHz Crystal NDK 8 IC2 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 R25 330Ω LED1 mute R24 1MΩ VDD C4 100nF R32 270Ω Right RSW Left CK728 US1 Right TEST US0 AUDIO MUTABLE OUT DV GND FM MONO IN ADV SD Left PDV SCK STEREO AUDIO IN MUTE C4 Right R23 5.6kΩ FID WS Left CONTROL BITS C3 EXTERNAL AUDIO IN C2 Right C1 * C23 value depends on X1 LED3 dual mono LED2 single mono SCL SDA LED4 stereo VDD I 2 C BUS TDA8205 Figure 2 : I2C Bus Controlled Application (I and B/G standard) 7/8 TDA8205 PACKAGE MECHANICAL DATA 42 PINS - PLASTIC SHRINK e4 A I b1 L a1 F b2 e b E Stand-off e A a1 b b1 b2 b3 D E e e3 e4 F i L 22 1 21 Min. 3.30 Millimeters Typ. 0.51 0.35 0.20 0.75 0.75 15.57 Max. Min. 0.130 0.020 0.014 0.008 0.030 0.030 0.59 0.36 1.42 39.12 17.35 1.778 35.56 15.24 Inches Typ. 0.613 Max. 0.023 0.014 0.056 1.540 0.683 0.070 1.400 0.600 14.48 5.08 2.54 0.570 0.200 0.100 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. © 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 8/8 SDIP42.TBL Dimensions 42 PMSDIP42.EPS D