TDA9110 LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS PRODUCT PREVIEW Combined with ST7275 Microcontroller family, TDA9206 (Video preamplifier) and STV942x (On-Screen Display controller) the TDA9110 allows to built fully I2C bus controlled computer display monitors, with a reduce nu mber of external compon ents. VERTICAL VERTICAL RAMP GENERATOR 50 TO 165Hz AGC LOOP GEOMETRY TRACKING WITH V-POS & AMP I2C CONTROLS : V-AMP, V-POS, S-CORR, C-CORR DC BREATHING COMPENSATION SHRINK32 (Plastic Package) 2 I C GEOMETRY CORRECTIONS VERTICAL PARABOLA GENERATOR (Pincushion, Keystone) HORIZONTAL SIZE CONTROL (Amplitude) HORIZONTAL DYNAMIC PHASE (Side Pin Balance & Parallelogram) HORIZONTAL AND VERTICAL DYNAMIC FOCUS (Horizontal Focus Amplitude, Horizontal Focus Symmetry, Vertical Focus Amplitude) GENERAL SYNCHRO PROCESSOR 12V SUPPLY VOLTAGE 8V REFERENCE VOLTAGE HOR. & VERT. LOCK UNLOCK OUTPUTS READ/WRITE I 2C INTERFACE HORIZONTAL AND VERTICAL MOIRE DESCRIPTION The TDA9110 is a monolithic integrated circuit assembled in 32-pin shrunk dual in line plastic package. This IC controls all the functions related to the horizontal and vertical deflection in multimode or multi-frequency computer display monitors. The internal synchro processor, combined with the very powerful geometry correction block make the TDA9110 suitable for very high performance monitors with very few external components. The horizontal jitter level is extremely low. (Typical standard deviation : 300ps @ 31kHz). It is particularly well suited for high-end 15” and 17” monitors. ORDER CODE : TDA9110 PIN CONNECTIONS H/HVIN 1 32 5V VSYNC-IN 2 31 SDA HMOIRE 3 30 SCL HLOCKOUT 4 29 VCC PLL2C 5 28 HSIZE FC1 6 27 GND C0 7 26 HOUT R0 8 25 XRAY PLL1F 9 24 EWOUT HPOS 10 23 VOUT HGND 11 22 VCAP HFLY 12 21 VREF HREF 13 20 VAGCCAP HLOCKCAP 14 19 VGND HVFOCUS 15 18 DCBREATH HFOCUSCAP 16 17 GND December 1997 This is advance information on a new product now in development or undergoing evaluatio n. Details are subject to change without notice. 9110-01.EPS .. .. .. .. .. . . .. . .. .. .. HORIZONTAL EXTREMELY LOW JITTER LEVEL SELF-ADAPTATIVE DUAL PLL CONCEPT 150kHz MAXIMUM FREQUENCY X-RAY PROTECTION INPUT I2C CONTROLS : HORIZONTAL DUTY-CYCLE, H-POSITION 1/29 TDA9110 PIN CONNECTIONS Pin Name 1 H/HVIN Function 2 VSYNCIN TTL compatible Vertical Synchro Input (for separated H&V) 3 HMOIRE Horizontal Moire Output (to be connected to PLL2C through a resistor divider) 4 HLOCKOUT 5 PLL2C 6 FC1 High Threshold VCO Decoupling Filter 7 C0 Horizontal Oscillator Capacitor TTL compatible Horizontal Synchro Input First PLL Lock/Unlock Output (0V unlocked - 5V locked) Second PLL Loop Filter 8 R0 9 PLL1F First PLL Loop Filter Horizontal Oscillator Resistor 10 HPOS Horizontal Position Decoupling Filter 11 HGND Horizontal Section Ground 12 HFLY Horizontal Flyback Input (positive polarity) 13 HREF Horizontal Section Reference Voltage (to be filtered) 14 HLOCKCAP First PLL Lock/Unlock Time Constant Capacitor 15 FOCUSOUT Mixed Horizontal and Vertical Dynamic Focus Output 16 HFOCUSCAP 17 GND 18 BREATH Horizontal Dynamic Focus Oscillator Capacitor Ground (related internal reference) DC Breathing Input Control 19 VGND 20 VAGCCAP Vertical Section Ground 21 VREF Vertical Section Reference Voltage (to be filtered) 22 VCAP Vertical Sawtooth Generator Capacitor 23 VOUT Vertical Ramp Output (with frequency independant amplitude and S or C Corrections if any). It is mixed with vertical position reference voltage output and vertical moire. 24 EWOUT East/West Pincushion Correction Parabola Output 25 XRAY X-RAY protection input (with internal latch function) 26 HOUT Horizontal Drive Output (int. trans. open collector) Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator GND HSIZE DC HSize Control Output 29 VCC Supply Voltage (12V Typ) 30 SCL I2C Clock Input 31 SDA I2C Data Input 32 5V 2/29 Supply Voltage (5V Typ.) 9110-01.TBL General Ground (referenced to VCC) 27 28 TDA9110 QUICK REFERENCE DATA Value Unit Horizontal Frequency Parameter 15 to 150 kHz Autosynch Frequency (for given R0 and C0) 1 to 4.5 F0 ± Horizontal Synchro Polarity Input YES Polarity Detection (on both Horizontal and Vertical Sections) YES TTL Composite Synchro YES Lock/Unlock Identification (on both Horizontal 1st PLL and Vertical Section) YES 2 I C Control for H-Position XRay Protection I2C Horizontal Duty Adjust 2 ± 10 % YES 30 to 60 I C Free Running Adjustment NO Stand-by Function YES Two Polarities H-Drive Outputs NO Supply Voltage Monitoring YES PLL1 Inhibition Possibility NO Horizontal Blanking Output YES % Vertical Frequency 35 to 200 Hz Vertical Autosync (for 150nF) 50 to 150 Hz Vertical S-Correction YES Vertical C-Correction YES Vertical Amplitude Adjustment YES DC Breathing Control on Vertical Amplitude YES Vertical Position Adjustment YES East/West Parabola Output YES Pin Cushion Correction Amplitude Adjustment YES Keystone Adjustment YES Internal Dynamic Horizontal Phase Control YES Side Pin Balance Amplitude Adjustment YES Parallelogram Adjustment YES Tracking of Geometric Corrections YES Reference Voltage (both on Horizontal and Vertical) YES 2 I C Horizontal Dynamic Focus Amplitude Adjustment I2C Horizontal Dynamic Focus Keystone Adjustment 2 YES YES YES I C Vertical Dynamic Focus Amplitude Adjustment YES Type of Input Synchro Detection (supplied by 5V Digital Supply) YES Vertical Moiré Output YES I2C Controlled V-Moiré Amplitude YES Frequency Generator for Burn-in NO 2 Fast I C Read/Write 400 Horizontal Moiré Output YES 2 I C controlled H-Moiré Amplitude YES DC HSize Output Amplitude Control YES kHz 9110-02.TBL Dynamic Focus (both Horizontal and Vertical) 3/29 HREF 13 2 3 VSYNCIN HMOIRE 9110-02.EPS GND 27 SCL 30 SDA 31 5V 32 HSIZE 28 1 H/HVIN VGND 19 VREF 21 HGND 11 PLL1F SYNC PROCESSOR HFLY VSYNC 7 bits HPOS I2C INTERFACE HLOCKCAP HLOCKOUT 6 bits S AND C CORRECTION 6 bits LOCK/UNLOCK IDENTIFICATION PHASE/FREQUENCY COMPARATOR H-PHASE (7 bits) RESET GENERATOR 5 bits SYNC INPUT SELECT (1 bit) VREF VREF VCO 7 6 22 12 VPOS 7 bits 5 PHASE SHIFTER 24 23 VFOCUS 6 bits 18 X Keyst. 6 bits X2 PCC 7 bits X2 26 HOUT 25 XRAY 17 GND 29 VCC 15 HVFOCUS 16 HFOCUSCAP TDA9110 X2 VCC XRAY HOUT BUFFER Amp (7bits) Kest (5 bits) SAFETY PROCESSOR H-DUTY (5 bits) 20 VAMP 7 bits GEOMETRY TRACKING Key Bal 6 bits X 2 Spin Bal 6 bits X2 PHASE COMPARATOR VERTICAL OSCILLATOR RAMP GENERATOR VMOIRE 5 bits R0 8 VAGCCAP 14 FC1 DCBREATH 4 HFLY VOUT 10 C0 VCAP PLL2C EWOUT 4/29 9 TDA9110 BLOCK DIAGRAM TDA9110 Symbol VCC VDD VIN VESD HSize Cur Tstg Tj Toper Parameter Supply Voltage (Pin 29) Supply Voltage (Pin 32) Max Voltage on Pin 12 Pin 5 Pin 16 Pin 7 Pins 8, 9, 14, 20, 22 Pin 15, 18, 23, 24, 25, 26, 28 Pins 1, 2, 3, 4, 30, 31 ESD susceptibility Human Body Model,100pF Discharge through 1.5kΩ EIAJ Norm,200pF Discharge through 0Ω Max. Sourced Current (Pin 28) Max. Sunk Current (Pin 28) Storage Temperature Junction Temperature Operating Temperature Value 13.5 5.7 1.8 4.0 5.5 6.4 8.0 VCC VDD 2 300 2.5 100 -40, +150 +150 0, +70 Unit V V V V V V V V V kV V mA µA o C o C o C 9110-03.TBL ABSOLUTE MAXIMUM RATINGS Symbol Rth (j-a) Parameter Value Junction-ambient Thermal Resistance Max. Unit o 65 C/W 9110-04.TBL THERMAL DATA SYNCHRO PROCESSOR Operating Conditions (VDD = 5V, T amb = 25oC) Symbol HsVR MinD Mduty VsVR VSW VSmD VextM Parameter Horizontal Synchro Input Voltage Minimum Horizontal Input Pulses Duration Maximum Horizontal Input Signal Duty Cycle Vertical Synchro Input Voltage Minimum Vertical Synchro Pulse Width Maximum Vertical Synchro Input Duty Cycle Maximum Vertical Synchro Width on TTL H/Vcomposite Test Conditions Pin 1 Pin 1 Pin 1 Pin 2 Pin 2 Pin 2 Pin 1 Min. 0 0.7 Typ. Test Conditions Low Level High Level Pins 1, 2 Low level High Level Pin 4, Cout = 20pF Locked Unlocked C0 = 820pF Min. 26 0 5 35 Test Conditions Min. Typ. Max. 5 25 5 0 5 15 750 Unit V µs % V µs % µs Electrical Characteristics (VDD = 5V, Tamb = 25oC) Symbol VINTH RIN VOut Parameter Horizontal and Vertical Input Threshold Voltage (Pins 1, 2) Horizontal and Vertical Pull-Up Resistor Output Voltage (Pin 4) TfrOut VHlock Falling and Rising Output CMOS Buffer Horizontal 1st PLL Lock Output Status (Pin 4) VoutT Extracted Vsync Integration Time (% of TH) on H/V Composite Typ. Max. 0.8 2.2 200 0 5 200 Unit V V kΩ V V ns V V % I2C READ/WRITE Electrical Characteristics (VDD = 5V,Tamb = 25oC) Symbol Parameter Max. Unit 400 kHz µs µs V V 2 Fscl Tlow Thigh Vinth VACK Maximum Clock Frequency Low period of the SCL Clock High period of the SCL Clock SDA and SCL Input Threshold Acknowledge Output Voltage on SDA input with 3mA Pin 30 Pin 30 Pin 30 Pins 30,31 Pin 31 1.3 0.6 2.2 0.4 2 See also I C Table Control and I2C Sub Address Control 5/29 9110-05.TBL I C PROCESSOR TDA9110 HORIZONTAL SECTION Operating Conditions Symbol Parameter Test Conditions Min. Typ. Max. Unit VCO R0(Min.) Minimum Oscillator Resistor Pin 8 4 C0(Min.) Minimum Oscillator Capacitor Pin 7 390 F(Max.) Maximum Oscillator Frequency kΩ pF 150 kHz OUTPUT SECTION I12m Maximum Input Peak Current Pin 12 2 mA HOI Horizontal Drive Output Maximum Current Pin 26, Sunk current 30 mA Electrical Characteristics (VCC = 12V, Tamb = 25oC) Symbol Parameter Test Conditions Min. Typ. Max. Unit 12 13.2 V 5 5.5 SUPPLY AND REFERENCE VOLTAGES VCC Supply Voltage Pin 29 10.8 VDD Supply Voltage Pin 32 4.5 ICC Supply Current Pin 29 50 mA IDD Supply Current Pin 32 5 mA V VREF-H Horizontal Reference Voltage Pin 13, I = 5mA 7.4 8 8.6 V VREF-V Vertical Reference Voltage Pin 21, I = 5mA 7.4 8 8.6 V IREF-H Max. Sourced Current on VREF-H Pin 13 5 mA IREF-V Max. Sourced Current on VREF-V Pin 21 5 mA 1st PLL SECTION Polarity Integration Delay VVCO VCO Control Voltage (Pin9) 0.75 VREF-H = 8V f0 fH(Max.) ms VREF-H / 6 6.2 V V R0 = 5.9kΩ, C0 = 820pF, dF/dV = 1/11R0 C0 18.8 kHz Vcog VCO Gain (Pin 9) Hph Horizontal Phase Adjustment % of Horizontal Period ±10 % Horizontal Phase Setting Value Minimum Value Typical Value Maximum Value Sub-Address 01 Byte x1111111 Byte x1000000 Byte x0000000 2.6 3.2 3.8 V V V Free Running Frequency R0 = 5.9kΩ, C0 = 820pF, f0 = 0.97/8R0C 0 25 kHz Free Running Frequency Thermal Drift (No drift on external components) See Note -150 ppm/C PLL1 Capture Range R0 = 6.49kΩ, C0 = 820pF, from f0+0.5kHz to 4.5F0 fH(Min.) fH(Max.) Component accuracy : C0 = 2%, R0 = 1% Hphmin Hphtyp Hphmax f0 dF0/dT CR Note : This parameter is not tested on each unit. It is measured during our internal qualification. 6/29 28 100 kHz kHz 9110-05.TBL HpolT TDA9110 HORIZONTAL SECTION (continued) Electrical Characteristics (VCC = 12V, Tamb = 25oC) (continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit 0.65 0.75 V 60 ppm 30 60 % % 2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION FBth Hjit HDmin HDmax XRAYth Vphi2 VSCinh HDvd Flyback Input Threshold Voltage (Pin 12) Horizontal Jitter Horizontal Freq. = 31kHz Horizontal Drive Output Duty-Cycle (Pin 26) (see Notes 1 & 2) Low Level High Level Sub-Address 00 X-RAY Protection Input Threshold Voltage Pin 25 Byte xxx11111 Byte xxx00000 Internal Clamping Levels on 2nd PLL Loop Low Level Filter (Pin 5) High Level Threshold Voltage To Stop H-Out,V-Out when VCC < VSCinh Pin 29 Horizontal Drive Output (low level) Pin 26 IOUT = 30mA 8 V 1.6 3.7 V V 7.5 V 0.4 V HORIZONTAL DYNAMIC FOCUS FUNCTION HDFst Horizontal Dynamic Focus Sawtooth Minimum Level Maximum Level HfocusCap = C0 = 820pF, TH=TBD, Pin 16 Horizontal Dynamic Focus Sawtooth Discharge Width 2 4.7 V V Start by HDFstart 400 ns Internal fixed Phase Advance versus Hfly Middle Fixed for each frequency (Pin 16) 860 ns HDFDC Bottom DC Output Level RLOAD = 10kΩ, Pin 15 TDHDF DC Output Voltage Thermal Drift HDFamp Horizontal Dynamic Focus Amplitude Min Byte x1111111 Typ Byte x1000000 Max Byte x0000000 HDFdis HDFstart HDFKeyst Horizontal Dynamic Focus Keystone Min A/B Byte xxx11111 Typ Byte xxx10000 Max A/B Byte xxx00000 Sub-Address 03, Pin 15, FH = 50kHz, Keystone Typ Sub-Address 04, FH = 50kHz, Typ Amp B/A A/B A/B 2 V 200 ppm/C 1.1 1.7 3.5 VPP VPP VPP 2.5 1.0 2.5 VERTICAL DYNAMIC FOCUS FUNCTION (positive parabola) AMPVDF Vertical Dynamic Focus Parabola (added to horizontal one) Amplitude with VOUT and VPOS Typical Min. Byte 000000 Typ. Byte 100000 Max. Byte 111111 Sub-Address 0F VPP VPP VPP Parabola Amplitude Function of VAMP Sub-Address 05 (tracking between VAMP and VDF) with Byte 10000000 VPOS Typ. Byte 11000000 (see Figure 1 and Note 3) Byte 11111111 0.6 1 1.5 VPP VPP VPP VHDFKeyt Parabola Assymetry Function of VPOS Sub-Address 06 Control (tracking between VPOS and VDF) Byte x0000000 with VAMP Max. Byte x1111111 0.52 0.52 VDFAMP 9110-05.TBL 0 0.5 1 Notes : 1. Duty Cycle is the ratio of power transistor OFF time period. Power transistor is OFF when output transistor is OFF. 2. Initial Condition for Safe Operation Start Up 3. S and C correction are inhibited so the output sawtooth has a linear shape. 7/29 TDA9110 VERTICAL SECTION Operating Conditions Symbol Parameter Test Conditions Min. Pin 24 Pin 24 Pin 20 1.8 65 Typ. Max. Unit 6.5 V V MΩ OUTPUTS SECTION VEWM VEWm RLOAD Maximum EW Output Voltage Minimum EW Output Voltage Minimum Load for less than 1% Vertical Amplitude Drift Electrical Characteristics (VCC = 12V, Tamb = 25oC) Symbol Parameter Test Conditions Min. Typ. Max. Unit VERTICAL RAMP SECTION Voltage at Ramp Bottom Point VRT Voltage at Ramp Top Point (with Synchro) VREF-V Pin 22 VREF-V=8V, Pin 22 2 V 5 V VRT0.1 V VRTF Voltage at Ramp Top Point (without Synchro) Pin 22 VSTD Vertical Sawtooth Discharge Time Duration (Pin 22) With 150nF Cap 70 µs VFRF Vertical Free Running Frequency (see Notes 4 & 5) COSC (Pin 22) = 150nF Measured on Pin22 100 Hz ASFR AUTO-SYNC Frequency C22 = 150nF ±5% See Note 6 RAFD Ramp Amplitude Drift versus Frequency at Maximum Vertical Amplitude C22 = 150nF 50Hz < f and f < 165Hz 200 ppm/Hz % 50 165 Hz Rlin Ramp Linearity on Pin 22 (see Notes 4 & 5) 2.5 < V22 and V22 < 4.5V 0.5 Vpos Vertical Position Adjustment Voltage (Pin23 - VOUT centering) Sub Address 06 Byte x0000000 Byte x1000000 Byte x1111111 3.3 3.65 3.2 3.5 3.8 V V V Vertical Output Voltage (peak-to-peak on Pin 23) Sub Address 05 Byte x0000000 Byte x1000000 Byte x1111111 2.5 3.5 2.25 3 3.75 V V V VOR VOI Vertical Output Maximum Current (Pin23) dVS Max Vertical S-Correction Amplitude x0xxxxxx inhibits S-CORR x1111111 gives max S-CORR Vertical C-Corr Amplitude x0xxxxxx inhibits C-CORR Ccorr ±5 mA Subaddress 07 ∆V/VPP at T/4 ∆V/VPP at 3T/4 -4 +4 % % SubAddress 08 Byte x1000000 Byte x1100000 Byte x1111111 -3 0 3 % % % Notes : 4. With Register 07 at Byte x0xxxxxx (Vertical S-Correction Control) then the S correction is inhibited, consequently the sawtooth has a linear shape. 5. With Register 08 at Byte x0xxxxxx (Vertical C - Correction Control) then the C correction is inhibited, consequently the sawtooth has a linear shape. 6. It is the frequency range for which the VERTICAL OSCILLATOR will automatically synchronize, using a single capacitor value on Pin 22 and with a constant ramp amplitude. 8/29 9110-05.TBL VRB TDA9110 VERTICAL SECTION (continued) Electrical Characteristics (VCC = 12V, Tamb = 25oC) (continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit EAST/WEST FUNCTION EWDC TDEWDC EWpara EWtrack KeyAdj KeyTrack DC Output Voltage with Typ Vpos,Keystone, Corner and Corner Balance Inhibited DC Output Voltage Thermal Drift Parabola Amplitude with Vamp Max, V-Pos Typ, Keystone Inhibited Parabola Amplitude Function of V-AMP Control (tracking between V-AMP and E/W) with Typ Vpos, Keystone, EW Typ Amplitude (see Note 8) Keystone Adjustment Capability with Typ Vpos, EW Inhibited and Vertical Amplitude Max. (see Note 8 and Figure 4) Intrinsic Keystone Function of V-POS Control (tracking between V-POS and EW) with EW Max Amplitude and Vertical Amplitude Max. (see Note 8) A/B Ratio B/A Ratio Pin 24, see Figure 2 2.5 V See Note 7 Subaddress 0A Byte 11111111 Byte 10100000 Byte 10000000 Subaddress 05 Byte 10000000 Byte 11000000 Byte 11111111 Subaddress 09 Byte 1x000000 Byte 1x111111 Subaddress 06 100 ppm/C 2.5 1.25 0 V V V 0.45 0.8 1.25 V V V 0.9 0.9 VPP VPP Byte x0000000 Byte x1111111 0.52 0.52 DC HSIZE OUTPUT CONTROL HSize out DC HSize Output Level (Pin 28) Subaddress 0B Byte 00000000 Byte 01000000 Byte 01111111 0.5 2.5 4.5 V V V +1.4 -1.4 %TH %TH 0.5 0.9 1.4 %TH %TH %TH +1.4 -1.4 %TH %TH INTERNAL HORIZONTAL DYNAMIC PHASE CONTROL FUNCTION SPBpara SPBtrack ParAdj Partrack Side Pin Balance Parabola Amplitude (Figure 3) with Vamp Max, V-POS Typ and Parallelogram Inhibited (see Notes 8 & 9) Side Pin Balance Parabola Amplitude function of Vamp Control (tracking between Vamp and SP B) w it h SP B Ma x, V- PO S T yp and Parallelogram Inhibited (see Notes 8 & 9) Parallelogram Adjustment Capability with Vamp Max, V-POS Typ and SPB Max (see Notes 8 & 9) Intrinsic Parallelogram Function of Vpos Control (tracking between V-Pos and DHPC) with Vamp Max, SPB Max and Parallelogram Inhibited (see Notes 8 & 9) A/B Ratio B/A Ratio Subaddress 0D Byte x1111111 Byte x1000000 Subaddress 05 Byte 10000000 Byte 11000000 Byte 11111111 Subaddress 0E Byte x1111111 Byte x1000000 Subaddress 06 Byte x0000000 Byte x1111111 0.52 0.52 VERTICAL MOIRE VMOIRE Vertical Moire (measured on VOUTDC) (Pin 23) Subaddress 0C Byte 01x11111 6 mV 0 0 -10 % % % BRADj Vertical Output Variation versus DC Breathing Control (Pin 23) V18 > VREF-V V18 = VREF-V V18 = VREF-V - 4V Notes : 7. These parameters are not tested on each unit. They are measured during our internal qualification 8. Refers to Notes 4 & 5 from last section. 9. TH is the Horizontal PLL Period Duration. 9/29 9110-05.TBL BREATHING COMPENSATION TDA9110 Figure 1 : Vertical Dynamic Focus Function Figure 2 : E/W Output B VDFAMP B 9110-03.EPS A A Figure 3 : EWDC Figure 4 : Dynamic Horizontal Phase Control Output 9110-04.EPS VDFDC EWPARA Keystone Effect on E/W Output (PCC Inhibited) B A 10/29 DHPCDC 9110-06.EPS SPBPARA 9110-05.EPS Keyadj TDA9110 TYPICAL VERTICAL OUTPUT WAVEFORMS Function Sub Address Pin Byte Specification VOUTDC Picture Image 2.25V 10000000 Vertical Size 05 23 VOUTDC 3.75V 11111111 Vertical Position DC Control 06 23 x0000000 x1000000 x1111111 3.2V 3.5V 3.8V 0xxxxxxx Inhibited Vertical S Linearity 07 ∆V 23 1x111111 VPP 1x000000 Vertical C Linearity 08 VPP 9110-06.TBL / 9110-07.EPS TO 9110-13.EPS ∆V = 4% V PP ∆V ∆V = 3% V PP 23 ∆V 1x111111 VPP ∆V = 3% V PP 11/29 TDA9110 GEOMETRY OUTPUT WAVEFORMS Function Sub Address Pin Byte Specification Picture Image EWamp Inhibited. Trapezoid Control 09 1X000000 0.9V 2.5V 1X111111 0.9V 2.5V 2.5V 0V 24 Keystone Inhibited Pin Cushion Control 10000000 0A 24 2.5V 11111111 SPB Inhibited 1x000000 0E 1x111111 Parallelogram Inhibited Side Pin Balance Control 12/29 1.4% TH 3.7V 1.4% TH 3.7V 1.4% TH 1x000000 0D Internal 1.4% TH 1x111111 Vertical Dynamic Focus with Horizontal 3.7V Internal 3.7V 32 2V 9110-07.TBL / 9110-14.EPS TO 9110-22.EPS Parrallelogram Control TDA9110 I2C BUS ADDRESS TABLE Sub Address Definition Slave Address (8C) : Write Mode D8 D7 D6 D5 D4 D3 D2 D1 0 x x x x 0 0 0 0 Horizontal Drive Selection / Horizontal Duty Cycle 1 x x x x 0 0 0 1 Horizontal Position 2 x x x x 0 0 1 0 Horizontal Moiré Control 3 x x x x 0 0 1 1 Synchro Priority / Horizontal Focus Amplitude 4 x x x x 0 1 0 0 Refresh / Horizontal Focus Keystone 5 x x x x 0 1 0 1 Vertical Ramp Amplitude 6 x x x x 0 1 1 0 Vertical Position Adjustment 7 x x x x 0 1 1 1 S Correction 8 x x x x 1 0 0 0 C Correction 9 x x x x 1 0 0 1 E/W Keystone A x x x x 1 0 1 0 E/W Amplitude B x x x x 1 0 1 1 Horizontal Size Control C x x x x 1 1 0 0 Vertical Moiré D x x x x 1 1 0 1 Side Pin Balance E x x x x 1 1 1 0 Parallelogram F x x x x 1 1 1 1 Vertical Dynamic Focus Amplitude Slave Address (8D) : Read Mode 0 D8 D7 D6 D5 D4 D3 D2 D1 x x x x 0 0 0 0 Synchro and Polarity Detection 13/29 TDA9110 I2C BUS ADDRESS TABLE (continued) D8 D7 D6 D5 D4 D3 D2 D1 [0] [0] [0] [0] WRITE MODE HDrive 0, off [1], on 00 01 Xray 1, reset [0] 02 HMoire 1, on [0], off 03 Sync 0, Comp [1], Sep 04 Detect Refresh [0], off 05 Vramp 0, off [1], on Horizontal Duty Cycle [0] [0] [0] Horizontal Phase Adjustment [1] [0] [0] [0] [0] Horizontal Moire Amplitude [0] [0] [0] [0] [0] [0] [0] Horizontal Focus Amplitude [1] [0] [0] [0] [0] Horizontal Focus Keystone [1] [0] [0] [0] [0] [0] [0] Vertical Ramp Amplitude Adjustment [1] [0] [0] [0] [0] Vertical Position Adjustment 06 [1] [0] [0] [0] [0] S Correction [0] [0] [1] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] 07 S Select 1, on [0] 08 C Select 1, on [0] [1] [0] 09 EW Key 0, off [1] [1] [0] 0A EW Sel 0, off [1] 0B Test H 1, on [0], off 0C Test V 1, on [0], off 0D SPB Sel 0, off [1] 0E Parallelo 0, off [1] [0] C Correction [0] [0] East/West Keystone [0] East/West Amplitude [1] [0] [0] [0] HSize Control [1] [0] Moire 1, on [0] [0] [0] Vertical Moire [0] [0] [0] Side Pin Balance [1] [0] [0] [0] Parallelogram [1] [0] [1] [0] [0] [0] Vertical Dynamic Focus Amplitude 0F [0] [0] READ MODE 00 Hlock 0, on [1], no Vlock 0, on [1], no Xray 1, on [0], off Polarity Detection H/V pol V pol [1], negative [1], negative [ ] initial value Data are transferred with vertical sawtooth retrace. 14/29 Synchro Detection Vext det [0], no det H/V det [0], no det V det [0], no det TDA9110 OPERATING DESCRIPTION I - GENERAL CONSIDERATIONS I.1 - Power Supply The typical values of the power supply voltages VCC and VDD are 12V and 5V respectively. Perfect operation is obtained for VCC between 10.8 and 13.2V and VDD between 4.5 and 5.5V. In order to avoid erratic operation of the circuit during transient phase of VCC switching on, or off, the value of VCC is monitored and the outputs of the circuit are inhibited if VCC is less than 7.5V typically. Similarly,VDD is monitored and internally set-up until VDD reaches 4V (see I 2C Control Table for power on reset). In order to have a verygood powersupply rejection, the circuit is internally supplied by several voltage references(typical value : 8V).Two of thesevoltage references are externally accessible, one for the vertical and one for the horizontal part. If needed, these voltage references can be used (if ILOAD is less than 5mA). It is necessary to filter the a.m. voltage references by external capacitors connected to ground, in order to minimize the noise and consequently the ”jitter” on vertical and horizontal output signals. I.2 - I2C Control TDA9110 belongs to the I2C controlled device family. Instead of being controlled by DC voltages on dedicated control pins, each adjustment can be done via the I2C Interface. The I2C bus is a serial bus with a clock and a data input. Thegeneral functionand thebus protocolare specified in the Philips-bus data sheets. The interface (Data and Clock) is TTL-level compatible. The internal threshold level of the input comparator is 2.2V (when VDD is 5V). Spikes (up to 50ns) are filtered by an integrator and the clock speed is limited to 400kHz. The data line (SDA) can be used bidirectionally(i.e. in read-mode the IC clocks out a reply information (1 byte) to the micro-processor). The bus protocol prescribes always a full-byte transmission. The first byte after the start condition is used to transmit the IC-address(7 bits-8C) and the read/write bit (0 write - 1 read). I.3 - Write Mode In write mode the second byte sent contains the subaddress of the selected function to adjust (or controlsto affect)and the third byte the corresponding data byte.It is possible to send more than one data byte to the IC. If after the third byte no stop or start condition is detected, the circuit increments automaticallyby one the momentary subaddressin the subaddress counter (auto-increment mode). So it is possible to transmit immediately the next data bytes without sending the IC address or subaddress.It can be useful to reinitialize the whole controls very quickly (flash manner). This procedure can be finished by a stop condition. The circuit has 16 adjustment capabilities : 2 for the Horizontal part, 4 for the Vertical, 2 for the E/W correction, 2 for the Dynamic Horizontal phase control,2 for the Moire options, 3 for the Horizontal and Vertical Dynamic Focus and 1 for the HSize amplitude control. 15 bits are also dedicated to several controls (ON/OFF, Synchro Priority, Detection Refresh and Xray reset). I.4 - Read Mode During the read mode the second byte transmits the reply information. The reply byte contains the Horizontal and Vertical Lock/Unlock status, the Xray activation status and, the Horizontaland Vertical polarity detection.It also contains the Synchro detection status which is used by the MCU to assign the Synchro priority. A stop conditionalways stops all the activities of the bus decoder and switches to high impedance both for the data and the clock line (SDA and SCL). See I2C Subaddress and control tables. I.5 - Synchro Processor TheinternalSynchroProcessor allowsthe TDA9110 to accept any kind of input synchro signals : - separated Horizontal & Vertical TTL-compatible synchro signals, - composite Horizontal &Vertical TTL-compatible synchro signals. I.6 - Synchro Identification Status The MCU can choose via the I2C the synchro priority thanks to the system identification status provided by the TDA9110. The extracted Vertical synchro pulse is available when this identification status has been received and when the 12V is supplied. Even in Power managementmode the IC is able to inform the MCU that synchrosignals were detected due to its 5V supply. We recommend to use the device as following : first, refresh the synchro detection by I2C, then check the status of H/V det and Vdet by I2C read. Sync priority choice should be : Vext H/V det det V det No Yes Yes No Yes Yes Sync priority Subaddress 03 D8 D7 1 0 1 1 Comment Synchro type Separated H & V Composite TTL H&V 15/29 TDA9110 OPERATING DESCRIPTION (continued) Of course, when the choice is done, we can refresh the synchro detectionsand verify that the extracted Vsync is present and that no synchro type change have occured. Synchro processor is also giving synchro polarity information. Figure 7 I.7 - IC status TheIC can inform the MCUabout the 1st Horizontal PLL or Vertical section status (locked or not), and about the Xray protection (activated or not). Resettingthe Xray internal latch can be done either by decreasing the VCC supply or directly resetting via the I2C interface. The last feature performed is the removing of equalizing pulses to avoid parasitic pulses on phase comparator input (which is sensitive to wrong or missing pulses). TRAMEXT d d II.2 - PLL1 The PLL1 consists of a phase comparator, an external filter and a voltage control oscillator (VCO). The phase comparator is a ”phase frequency” type designed in CMOS technology. This kind of phase detector avoids locking on false frequencies. It is followed by a ”charge pump”, composed of two current sources sunk and sourced(Typically I = 1mA when locked and I = 140µA when unlocked). This difference between lock/unlock permits a smooth catching of the horizontal frequency by the PLL1. This effect is reinforced by an internal original slow down system when the PLL1 is locked, avoiding the Horizontal frequency to change too fast. The dynamic behaviour of the PLL1 is fixed by an external filter which integrates the current of the charge pump. A ”CRC” filter is generally used (see Figure 8). I.8 - Synchro Inputs Both H/HVin and Vsyncin inputs are TTL compatible triggers with Hysterisis to avoid erratic detection. It includes pull up resistor to VDD. I.9 - Synchro Processor Output The synchro processor delivers the Hlockout signal on a TTL-compatible CMOS output. Hlockout is the Horizontal 1st PLL status (5V when locked). It allows the MCU to check the Horizontal IC locking. II - HORIZONTAL PART II.1 - Internal Input Conditions A digital signal (Horizontal synchro pulse or TTL composite) is sent by the synchro processor to the horizontal part. Positive or negative signal can be applied to the Horizontal part input (see Figure 6). Using internal integration, both signals are recognized if Z/T < 25%. Synchronization occurs on the leading edge of the internal synchro signal. The minimum value of Z is 0.7µs. Figure 8 PLL1F 7 9110-23.EPS 9110-25.EPS Figure 6 An other integration is able to extract vertical pulse of composite synchro if duty cycle is higher than 25% (typically d = 35%) (see Figure 7). 16/29 9110-24.EPS C ThePLL1isinternallyinhibitedduringextractedvertical synchro (if any) to avoid taking in account missing pulses or wrong pulses on phase comparator.The inhibition results from the opening of a switch located betweenthe chargepumpand thefilter (see Figure 9). The VCO uses an external RC network. It delivers a linear sawtooth obtained by the charge and the discharge of the capacitor, with a current proportionnal to the current in the resistor. The typical thresholds of the sawtooth are 1.6V and 6.4V. TDA9110 OPERATING DESCRIPTION (continued) Figure 9 : Principle Diagram H-LOCKCAP LOCK/UNLOCK STATUS 8 LOCKDET PLL1F R0 C0 7 6 5 TRAMEXT High INPUT INTERFACE HSYNC CHARGE PUMP COMP1 E2 PLL INHIBITION VCO Low OSC PHASE ADJUST I2C HPOS Adj. 9110-26.EPS TRAMEXT Figure 10 : Details of VCO I0 2 6.4V RS FLIP FLOP I0 Loop Filter 7 1.6V 4 I0 6 (1.3V < V7 < 6V) 10 6.4V 9110-27.EPS C0 1.6V 0 0.875TH T The control voltage of the VCO is between 1.33V and 6V (see Figure 10). The theorical frequency range of this VCO is in the ratio of 1 to 4.5. The effective frequency range has to be smaller (1 to 4.2) due to clamp intervention on filter lowest value. In order to increase this effective frequency range, to a possiblerange of 1 to6.0 one canadda resistor from Pin 6 to Href leading. The synchro frequency must always be higher than the free running frequency. For example, when using a synchro range between 31kHz and 96kHz, the suggested free running frequency is 25kHz. The PLL1 ensures the coincidence between the leading edge of the synchro signal and a phase reference obtained by comparison between the sawtooth of the VCO and an internal DC voltage 2 which is I C adjustable between 2.65V and 3.75V (corresponding to ± 10%) (see Figure 11). Figure 11 : PLL1 Timing Diagram H Osc Sawtooth 7/8TH 1/8TH 6.4V 2.60V<Vb<3.80V Vb 1.6V Phase REF1 H Synchro Phase REF1 is obtained by comparison between the sawtooth and a DC voltage adjustable between 2.60V and 3.80V. The PLL1 ensures the exact coincidence between the signals phase REF and HSYNS. A ± T/10 phase adjustment is possible. 17/29 9110-28.EPS R0 TDA9110 OPERATING DESCRIPTION (continued) Figure 12 : LOCK/UNLOCK Block Diagram 5V 20kΩ H-Lock CAP 8 6.5V 220nF B 3 HLOCKOUT 9110-29.EPS A 6V The TDA9110 also includes a Lock/Unlock identification block which senses in real time whether the the PLL1 is locked or not on the incominghorizontal synchro signal. The resulting information is available on Hlockout (see Synchro Processor). The block function is described in Figure 12. The NOR1 gate receive the phase comparator output pulses (which also drive the charge pump). When the PLL1 is locked, we have on point A a very small negative pulse (about 100ns) at each horizontal cycle, so after the RC filter, there is a high level on Pin 14 which forces Hlockout to high level. The hysterisis comparator detects locking when Pin 14 reachs 6.5V and unlocking when Pin 14 decreases to 6.0V. When the PLL1 is unlocked, the 100ns negative pulse on Abecomes much larger and consequently the average level on Pin 14 decreases. It forces Hlockout to low level. The Pin 14 status is approximately the following : - near 0V when there is no H-Sync - between 0 and 4V with H-Sync frequency different from VCO - between 4 to 8 V when VCO frequency reaches H-Sync one (but not already in phase) - near 8V when PLL1 is locked. It is important to notice that Pin 14 is not an output pin but is only used for filtering purpose (see Figure 12). The lock/unlock information is also available through the I2C read. recommanded input current is 5mA (see Figure 14). The duty cycle is adjustable through I2C from 30% to 60%. For Start Up safe operation, the initial duty cycle (afterPower on reset) is 60% in order to avoid to have a too long conduction of the BU transistor. Themaximumstoragetime isabout38% (TFLY/2.TH). Typically, TFLY/TH is around 20% which means that Ts max is around 28%. II.3 - PLL2 The PLL2 ensures a constant position of the shaped flyback signal in comparison with the sawtooth of the VCO (Figure 13). The phase comparator of PLL2 (phase type comparator) is followed by a charge pump (typical output current : 0.5mA). The flyback input consists of an NPN transistor. This input must be current driven. The maximum Figure 14 : Flyback Input Electrical Diagram 18/29 Figure 13 : PLL2 Timing Diagram H Osc Sawtooth 1/8TH 7/8TH 6.4V 3.7V 1.6V Flyback Internally Shaped Flyback H Drive Ts Duty Cycle The duty cycle of H-drive is adjustable between 30% and 60%. 9110-30.EPS NOR1 400Ω Q1 HFLY 12 20kΩ GND 0V 9110-31.EPS From Phase Comparator TDA9110 OPERATING DESCRIPTION (continued) Obviously the power scanning transistor cannot be directly driven by the integrated circuit. An interface has to be added between the circuit and the power transistor either of bipolar or of MOS type. II.4 - Output Section The H-drive signal is sent to the output through a shaping block ensuring Ts and H-drive duty cycle (I2C adjustable) (see Figure 13). In order to secure the scanning power part operation, the output is inhibited in the following cases : - when VCC is too low, - when the Xray protection is activated, - during the Horizontal flyback, - when the HDrive I2C bit control is off. The output stage consists of a NPN bipolar transistor. Only the collector is accessible(see Figure 15). II.5 - X-RAY Protection The X-Ray protection is activated by application of a high level on the X-Ray input (8V on Pin 25). The consequencies of X-Ray protection are : - inhibition of H-Drive output - activation of vertical blanking output. This protection is reset either by VCC switch off or by I2C (see Figure 16). Figure 15 VCC 9110-32.EPS 26 H-DRIVE The output NPN is in off-state when the power scanning transistor is also in off-state. The maximum output current is 30mA, and the corresponding voltage drop of the output VCEsat is 0.4V typically. II.6 - Horizontal and Vertical Dynamic Focus The TDA9110 delivers a horizontalparabola which is added on a vertical parabola waveform on Pin 15. This horizontal parabola comes from a sawtooth. The phase advance versus Horizontal flyback middle is kept constant for each frequency (about 860ns). This sawtooth is present on Pin 16 where the horizontal focus capacitor is the same as C0 to obtain a controlled amplitude (from 2 to 4.7V typically). Symmetry (keystone) and amplitude areI 2C adjustable (see Figure 17). The Vertical dynamic focus is tracked with VPOSand VAMP.Its amplitudecan be adjusted. It is also affected by S and C corrections. This positive signal has to be connectedto the CRT focusing grids. Figure 16 : Safety Functions Block Diagram VCC Checking I2C Drive on/off VCC Ref HORIZONTAL OUTPUT INHIBITION XRAY Protection XRAY VCC off or I2C Reset S R Q I2C Ramp on/off VERTICAL OUTPUT INHIBITION 9110-33.EPS Horizontal Flyback 0.7V 19/29 TDA9110 OPERATING DESCRIPTION (continued) Figure 17 Horizontal Flyback 860ns Internal Trigged Horizontal Flyback 4.7V Horizontal Focus Cap Sawtooth 2V Horizontal Dynamic Focus Parabola Output Moire Output 2V II.7 - Moire Output The moire output is intented to correct a beat between the horizontal video pixel period and the current CRT pixel width. The moire signal is a combination of the Horizontal and the Vertical frequency signals. To achieve a moire cancellation, the moire output has to be connected to any point of the chassis controlling the horizontal position. We recommend to introduce this “ Horizontal Controlled Jitter” on 20/29 the relative ground of PLL2 capacitor where this “controlled jitter” frequency type will directly affect the horizontal position. The amplitude of the signal is I2C adjustable. If the H-Moire feature is not necessary in the application, the H-Moire output (Pin 3) can be used as a 5 bits DAC output (0.3V to 2.2V). If the H-Moire output is not used at all, so the Pin 3 must be either kept to high impedance or grounded via a resistor. 9110-34.EPS 400ns TDA9110 OPERATING DESCRIPTION (continued) III - VERTICAL PART III.1 - Geometric Corrections The principle is represented on Figure 20. Starting from the vertical ramp, a parabola shaped current is generated for E/W correction, dynamic horizontal phase control correction, and vertical dynamic Focus correction. The parabola generator is made by an analog multiplier, the output current of which is equal to : ∆I = k ⋅ (VOUT - VDCOUT)2 where Vout is the vertical output ramp (typically between 2 and 5V) and Vdcout is the vertical DC output adjustable in the range 3.2V to 3.8V which generate a dissymetric parabola if needed (keystone adjustment). In order to keep a good screen geometry for any end user preferencesadjustment,we implemented the ”geometry tracking”. Due to large output stages voltage range (E/W, FOCUS), the combination of tracking function with maximum vertical amplitude max or min vertical position and maximum gain on the DAC control may lead to the output stages saturation. This must be avoided by limiting the output voltage with apropriate I2C registers values. For the E/Wpart and the Dynamic Horizontalphase control part, a sawtooth shaped differential current in the following form is generated: ∆I’ = k’ ⋅ (VOUT - VDCOUT) Then ∆I and ∆I’ are addedand converted into voltage for the E/W part. Each of the two E/W components or the two Dynamic Horizontal phase control ones may be inhibited by their own I2C select bit. The E/W parabola is available on Pin 24 via an emitter follower which has to be biased by an external resistor (10kΩ). It can be DC coupled with external circuitry. The Vertical Dynamic Focus is combined with the Horizontal one on Pin 15. The dynamic Horizontalphasecontrol current drives internally the H-position, moving the Hfly position on the Horizontal sawtooth in the range of ± 1.4% TH both on SidePin Balance and Parallelogram. Figure 20 : Geometric Corrections Principle AMP 2 VDCOUT Internal Vertical Dynamic Focus added to Horizontal one Vertical Ramp V OUT EW amp VDCIN EW Output Keystone Sidepin amp To Horizontal Phase Sidepin Balance Output Current Parallelogram 21/29 9110-37.EPS VDCOUT TDA9110 OPERATING DESCRIPTION (continued) Figure 21 : Vertical Part Block Diagram CHARGE CURRENT TRANSCONDUCTANCE AMPLIFIER REF 22 20 OSC CAP DISCH. V_SYNC 2 SYNCHRO SAMPLING SAMP. CAP S CORRECTION OSCILLATOR VS_AMP SUB07/6bits POLARITY COR_C SUB08/6bits C CORRECTION Vlow Sawth. Disch. 23 VERT_OUT 18 BREATH PARABOLA GENERATOR 24 EW_OUT VERT_AMP SUB05/7bits VMOIRE SUB0C/5bits EW_CENT EW_AMP SUB0A/6bits SUB09/7bits VPOSITION SUB06/7bits SPB_OUT Internal Signal to PLL2 PARAL SUB0E/6bits SPB_AMP SUB0D/6bits AMP 6bits III.2 - EW EWOUT = 2.5V + K1 (VOUT - VDCOUT)2 + K2 (VOUT - VDCOUT) K1 is adjustable by the EW amplitude I2C register K2 is adjustable by the Keystone I2C register III.3 - DC HSize Output Control A 7 bits D/A converter is available on Pin 28. The output is a NPN transistor emitter follower output with an internal 100mA current source from output to ground (max. sunk current). The Max. current the output is able to source is 2.5mA. The output level is between 0.5V to 4.5V. This DAC can be used to control the H-Size. III.4 - Dynamic Horizontal Phase Control 2 IOUT = K5 (VOUT - VDCOUT) + K6 (VOUT - VDCOUT) K5 is adjustable by the SidePin Balance I2C register 22/29 Internal Signal added to H_FOCUS K6 is adjustable by the Parallelogram I2C register III.5 - Function When the synchronization pulse is not present, an internal current source sets the free running frequency. For an external capacitor, COSC = 150nF, the typical free running frequency is 106Hz. The typical free running frequency can be calculated by : 1 f0 (Hz) = 1.6 e−5 ⋅ COSC A negative or positive TTL level pulse applied on Pin 2 (VSYNC)as well as a TTLcomposite synchro on Pin 1 can synchronize the ramp in the range [fmin , fmax]. This frequency range depends on the external capacitorconnectedon Pin 22.A capacitor in the range [150nF, 220nF] ± 5% is recommanded forapplicationin thefollowingrange: 50Hz to 120Hz. 9110-38.EPS V_FOCUS TDA9110 OPERATING DESCRIPTION (continued) Typical maximum and minimum frequency, at 25oC and without any correction (S correction or C correction), can be calculated by : f(Max.) = 2.5 x f0 and f(Min.) = 0.33 x f0 If S or C corrections are applied, these values are slighty affected. If a synchronization pulse is applied, the internal oscillator is automaticaly caught but the amplitude is no more constant. An internal correction is activated to adjust it in less than a half a second : the highest voltage of the ramp Pin 22 is sampled on the sampling capacitor connected on Pin 20 at each clock pulse and a transconductanceamplifier generates the charge current of the capacitor. The ramp amplitude becomes again constant. The read status register enables to have the vertical Lock-Unlock and the vertical Synchro Polarity informations. We recommand to use a AGC capacitor with low leakage current. A value lower than 100nA is mandatory. A good stability of the internal closed loop is reached by a 470nF ± 5% capacitor value on Pin 20 (VAGC). III.6 - I2C Control Adjustments Then, S and C correction shapes can be added to this ramp. These frequence independent S and C corrections are generated internally. Their amplitudes are adjustable by their respective I2C register. They can also be inhibited by their Select bit. Finally, the amplitude of this S and C corrected ramp can be adjusted by the vertical ramp amplitude control register. The adjusted ramp is available on Pin 23 (VOUT) to drive an external power stage. The gain of this stage is typically 25% depending on its register value. The DC value of this ramp is driven by its own I2C r eg is t e r (ve rtic a l P o sit ion ). I ts v a lue is VCDOUT = 7/16 ⋅ VREF ± 300mV. The VDCOUT voltage is correlated with DC value of VOUT. It increases the accuracy when temperature varies. By using the vertical moire, VDCOUT can be modulated from frame to frame. This function is intended to correct slightly the vertical video line to line period from actual CRT line to line width. III.7 - Basic Equations In first approximation,the amplitude of the ramp on Pin 23 (Vout) is : VOUT - VMID = (VOSC - VMID) ⋅ (1 + 0.25 (VAMP)) with VMID = 7/16 ⋅ VREF ; typically 3.5V, the middle value of the ramp on Pin 22 VOSC = V22 , ramp with fixed amplitude VAMP is -1 for minimum vertical amplitude register value and +1 for maximum On VDCOUT, the voltage (in volts) is calculated by : VDCOUT = VMID + 0.3 (VPOS) with VPOS equals -1 for minimum vertical position register value and +1 for maximum The current available on Pin 22 is : 3 IOSC = ⋅ VREF ⋅ COSC ⋅ f 8 with COSC : capacitor connected on Pin 22 f : synchronization frequency 23/29 TDA9110 INTERNAL SCHEMATICS Figure 22 Figure 23 5V 9110-39.EPS HMOIRE 3 Figure 24 9110-40.EPS 200Ω Pins 1 -2 H/HVIN VSYNC-IN 20kΩ 5V Figure 25 12V HREF 13 5V PLL2C 5 HLOCKOUT Figure 26 9110-42.EPS 9110-41.EPS 4 Figure 27 12V 12V HREF 13 13 C0 24/29 7 9110-44.EPS 6 9110-43.EPS FC HREF TDA9110 INTERNAL SCHEMATICS (continued) Figure 28 Figure 29 HREF 13 12V HREF 13 PLL1F 9 Figure 30 9110-46.EPS 9110-45.EPS R0 8 Figure 31 HREF 12V 13 12V HPOS 10 Figure 32 9110-48.EPS 9110-47.EPS HFLY 12 Figure 33 12V HREF 13 12V HLOCKCAP 14 12V HREF 13 9110-50.EPS 9110-49.EPS HFOCUS 15 25/29 TDA9110 INTERNAL SCHEMATICS (continued) Figure 34 Figure 35 HREF 13 12V 12V HFOCUS 16 CAP 9110-51.EPS 9110-52.EPS BREATH 18 Figure 36 Figure 37 12V VCAP 22 12V 9110-53.EPS 9110-54.EPS VAGCCAP 20 Figure 38 Figure 39 12V 12V EWOUT 24 26/29 9110-56.EPS 9110-55.EPS VOUT 23 TDA9110 INTERNAL SCHEMATICS (continued) Figure 40 Figure 41 12V 12V HOUT 26 Figure 42 9110-58.EPS 9110-57.EPS XRAY 25 Figure 43 12V 12V Pins 30-31 SDA - SCL 9110-60.EPS 9110-59.EPS HSIZE 28 27/29 TDA9110 DEMONSTRATION BOARD J15 1 1 J14 IC2 TDA9110 TP1 22pF C40 L1 10µH 1 H/HVIN C39 +5V J11 HSYNC 4 3 2 1 J16 +5V 32 TP13 R39 4.7kΩ +5V C30 100µF C32 100nF C6 100µF C5 100nF R29 4.7kΩ R42 100Ω 22pF R41 100Ω TP16 J12 VSYNC CC2 10µF +12V CC1 100nF PC2 47kΩ CC4 +12V 1 TA1 VCC 16 2 TA2 TB1 15 3 CDA TB2 14 4 IA CDB 13 5 IA VSYNCIN SDA 31 3 MOIRE SCL 30 4 HLOCKOUT R28 +12V 10kΩ ICC1 - MC14528 47pF 2 TP17 PC1 47kΩ CC3 TP10 IB 11 7 QA QB 10 R29 C7 10Ω 22nF +12V +12V R31 27kΩ 5 IB 12 6 QA VCC 29 47pF PLL2C +12V 6 FC1 R53 1kΩ C28 7 R10 10kΩ C0 820pF 5% C25 33pF 8 R0 1kΩ J1 R19 R38 270kΩ 2.2Ω 1W 1 E/W C11 10µF 220pF R45 33kΩ R33 4.7kΩ TP14 R9 470Ω R18 39kΩ Q3 TIP122 R7 10kΩ C13 10nF 9 PLL1F HOUT EWOUT 24 1 J17 R8 10kΩ 4.7µF 10 HPOS C62 HFLY J2 VERTICAL DEFLECTION STAGE VOUT 23 1µF 1 1 11 HGND VCAP 22 1 J3 TP8 C18 100µF 36V R40 12 HFLY TP7 C15 7 100nF VA GCCAP 20 R1 1 470nF C2 100nF C17 14 HLOCKCAP VGND 19 220nF 2 C4 R2 5.6kΩ HREF 13 HREF J18 VREF 21 36kΩ C33 100nF C9 +12V 100nF -12V 150nF 220pF C27 47µF C14 470µF D1 1N4004 C12 C16 C3 47µF 12kΩ 6 IC1 TDA8172 4 C41 470pF R5 3 5 C10 -12V 470µF R3 1.5Ω C1 220nF C8 100nF R11 220Ω 1/2W 1 2 3 V YOKE R4 1Ω 1/2W 5.6kΩ J9 DYNAMIC FOCUS R17 270kΩ Q1 Q2 BC557 C31 R36 1.8kΩ HOUT J8 R34 D2 C48 1N4148 XRAYIN 25 5.9kΩ 1% C22 33pF R15 1kΩ HOUT 26 C49 100nF R23 R56 560Ω GND 27 QB 9 R35 10kΩ R37 27kΩ +12V C61 100nF 8 GND E/W POWER STAGE HSIZE 28 R25 15 HVFOCUS 1 DCBREATH 18 1kΩ R24 10kΩ C34 820pF 5% +12V R73 1MΩ P1 R74 10kΩ 16 HFOCUSCAP GND 17 EHT 10kΩ COMP 28/29 10kΩ R76 47kΩ R77 15kΩ C60 100nF 9110-61.EPS R75 TP8 TDA9110 PMSDIP32.EPS PACKAGE MECHANICAL DATA 32 PINS - PLASTIC SHRINK DIP A A1 A2 B B1 C D E E1 e eA eB L Min. 3.556 0.508 3.048 0.356 0.762 0.203 27.43 9.906 7.620 2.540 Millimeters Typ. 3.759 3.556 0.457 1.016 0.254 27.94 10.41 8.890 1.778 10.16 3.048 Max. 5.080 4.572 0.584 1.397 0.356 28.45 11.05 9.398 Min. 0.140 0.020 0.120 0.014 0.030 0.008 1.080 0.390 0.300 12.70 3.810 0.100 Inches Typ. 0.148 0.140 0.018 0.040 0.010 1.100 0.410 0.350 0.070 0.400 0.120 Max. 0.200 0.180 0.023 0.055 0.014 1.120 0.435 0.370 SDIP32.TBL Dimensions 0.500 0.150 Information furni shed is believed to be accurate and reliable. However, SGS-THOMSON Micr oelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise und erany patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This pu blication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1997 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I 2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 29/29