STMICROELECTRONICS TDA9112

TDA9112
LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR
FOR MULTISYNC MONITOR
FEATURES
General
2
■ ADVANCED I C BUS CONTROLLED
DEFLECTION PROCESSOR DEDICATED
FOR HIGH-END CRT MONITORS
■ SINGLE SUPPLY VOLTAGE 12V
■ VERY LOW JITTER
■ DC/DC CONVERTER CONTROLLER
■ ADVANCED EW DRIVE
■ ADVANCED ASYMMETRY CORRECTIONS
■ AUTOMATIC MULTISTANDARD
SYNCHRONIZATION
■ 2 DYNAMIC CORRECTION WAVEFORM
OUTPUTS
■ X-RAY PROTECTION AND SOFT-START &
STOP ON HORIZONTAL AND DC/DC DRIVE
OUTPUTS
2
■ I C BUS STATUS REGISTER
Horizontal section
■ 150 kHz maximum frequency
■ Corrections of geometric asymmetry: Pin
cushion asymmetry, Parallelogram, separate
Top/Bottom corner asymmetry
■ Tracking of asymmetry corrections with vertical
size and position
■ Fully integrated horizontal moiré cancellation
Vertical section
■ 200 Hz maximum frequency
■ Vertical ramp for DC-coupled output stage with
adjustments of: C-correction, S-correction for
super-flat CRT, Vertical size, Vertical position
■ Vertical moiré cancellation through vertical
ramp waveform
■ Compensation of vertical breathing with EHT
variation
EW section
■ Symmetrical geometry corrections: Pin cushion,
Keystone, Top/Bottom corners separately
■ Horizontal size adjustment
■ Tracking of EW waveform with Vertical size and
position and adaptation to frequency
■ Compensation of horizontal breathing through
EW waveform
Dynamic correction section
■ Generates waveforms for dynamic corrections
like focus, brightness uniformity, ...
■ 1 output with vertical dynamic correction
waveform
■ 1 output with composite HV dynamic correction
waveform
■ Fixed on screen by means of tracking system
DC/DC controller section
■ Step-up and step-down conversion modes
■ Internal and external sawtooth configurations
■ Bus-controlled output voltage
■ Synchronization on hor. frequency with phase
selection
■ Selectable polarity of drive signal
DESCRIPTION
The TDA9112 is a monolithic integrated circuit assembled in a 32-pin shrink dual-in-line plastic
package. This IC controls all the functions related
to horizontal and vertical deflection in multimode
or multi-frequency computer display monitors.
The internal sync processor, combined with the
powerful geometry correction block, makes the
TDA9112 suitable for very high performance monitors, using few external components.
Combined with other ST components dedicated
for CRT monitors (microcontroller, video preamplifier, video amplifier, OSD controller) the TDA9112
allows fully I2C bus-controlled computer display
monitors to be built with a reduced number of external components.
SHRINK 32 (Plastic Package)
ORDER CODE: TDA9112
Version 4.2
November 2001
1/51
1
TABLE OF CONTENTS
1
2
3
4
5
6
-PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
-BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
-PIN FUNCTION REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
-QUICK REFERENCE DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
-ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
-ELECTRICAL PARAMETERS AND OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . 9
6.1 -THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.2 -SUPPLY AND REFERENCE VOLTAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.3 -SYNCHRONIZATION INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.4 -HORIZONTAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.5 -VERTICAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.6 -EW DRIVE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.7 -DYNAMIC CORRECTION OUTPUTS SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.8 -DC/DC CONTROLLER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.9 -MISCELLANEOUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 -TYPICAL OUTPUT WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2
8 -I C BUS CONTROL REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9 -OPERATING DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.1 -SUPPLY AND CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.1.1 -Power supply and voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.1.2 -I2C Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.2 -SYNC. PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.2.1 -Synchronization signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.2.2 -Sync. presence detection flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.2.3 -MCU controlled sync. selection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.2.4 -Automatic sync. selection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.3 -HORIZONTAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.3.1 -General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.3.2 -PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.3.3 -Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.3.4 -PLL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.3.5 -Dynamic PLL2 phase control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.3.6 -Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.3.7 -Soft-start and soft-stop on H-drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.3.8 -Horizontal moiré cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.4 -VERTICAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.4.1 -General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.4.2 -Vertical moiré . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.5 -EW DRIVE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.6 -DYNAMIC CORRECTION OUTPUTS SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.6.1 -Composite horizontal and vertical dynamic correction output HVDyCor . . . . . . . . . 36
9.6.2 -Vertical dynamic correction output VDyCor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.7 -DC/DC CONTROLLER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.7.1 -External sawtooth configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.7.2 -Internal sawtooth configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.8 -MISCELLANEOUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3
9.8.1 -Safety functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.8.2 -Soft start and soft stop functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2/51
9.8.3 -X-ray protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.8.4 -Composite output HLckVBk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 -INTERNAL SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 -PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12 -GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
41
43
47
48
3/51
TDA9112
1 - PIN CONFIGURATION
H/HVSyn
VSyn
HLckVBk
HOscF
HPLL2C
CO
HGND
RO
HPLL1F
HPosF
HVDyCor
HFly
RefOut
BComp
BRegIn
BISense
4/51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDyCor
SDA
SCL
Vcc
BOut
GND
HOut
XRay
EWOut
VOut
VCap
VGND
VAGCCap
VOscF
VEHTIn
HEHTIn
1
HPosF
HPLL1F
R0
7
10
9
8
H-sync
detection
Polarity
handling
C0 HOscF
6
Horizontal
VCO
Phase/frequency
comparator
3
PLL1
V-blank
H-lock
HFly
HPLL2C
12
5
Phase comparator
Phase shifter
H duty controller
Horizontal position
Lock detection
HLckVBk
4
Pin cushion asymm.
Parallelogram
Top corner asymm.
Bottom corner asymm.
Hor. duty cycle
H-moiré controller
PLL2
H-moiré amplitude
SDA
31
SCL
30
Vcc
29
RefOut
I2C Bus
interface
13
Supply
supervision
Reference
generation
26
HOut
Safety
processor
25
XRay
28
BOut
16
BIsense
15
BRegIn
14
BComp
11
HVDyCor
24
EWOut
B+
DC/DC
converter
controller
B+ ref.
I2C Bus registers
:
H-drive
buffer
2 - BLOCK DIAGRAM
H/HVSyn
HGND
2
Functions controlled via I C Bus
V-dynamic
correction
(focus, bright.)
V-sync
extraction
& detection
HV-dynamic
correction
(focus,brightness)
Geometry
tracking
HVDyCor V-amplitude
HVDyCor H-amplitude
HVDyCor H-symmetry
VDyCor amplitude
Internal
ref.
GND
V-sync detection
Input selection
Polarity handling
2
VGND
Vertical oscillator
with AGC
Vertical size
Vertical position
Vertical moiré
S-correction
C-correction
19
20
22
H size
Pin cushion
Keystone
Top corners
Bottom corners
32
VOscF
VCap VDyCor
VAGCCap
23
18
17
VOut
VEHTIn
HEHTIn
TDA9112
5/51
TDA9112
VSyn
21
EW generator
V-ramp control
Tracking EHT
27
TDA9112
3 - PIN FUNCTION REFERENCE
Pin
Name
Function
1
H/HVSyn
TTL compatible Horizontal / Horizontal and Vertical Sync. input
2
VSyn
TTL compatible Vertical Sync. input
3
HLckVBk
Horizontal PLL1 Lock detection and Vertical early Blanking composite output
4
HOscF
High Horizontal Oscillator sawtooth threshold level Filter input
5
HPLL2C
Horizontal PLL2 loop Capacitive filter input
6
CO
Horizontal Oscillator Capacitor input
7
HGND
Horizontal section GrouND
8
RO
Horizontal Oscillator Resistor input
9
HPLL1F
Horizontal PLL1 loop Filter input
10
HPosF
Horizontal Position Filter and soft-start time constant capacitor input
11
HVDyCor
Horizontal and Vertical Dynamic Correction output
12
HFly
Horizontal Flyback input
13
RefOut
Reference voltage Output
14
BComp
B+ DC/DC error amplifier (Comparator) output
15
BRegIn
Regulation feedback Input of the B+ DC/DC converter controller
16
BISense
B+ DC/DC converter current (I) Sense input
17
HEHTIn
Input for compensation of Horizontal amplitude versus EHT variation
18
VEHTIn
Input for compensation of Vertical amplitude versus EHT variation
19
VOscF
Vertical Oscillator sawtooth low threshold Filter (capacitor to be connected to VGND)
20
VAGCCap
Input for storage Capacitor for Automatic Gain Control loop in Vertical oscillator
21
VGND
Vertical section GrouND
22
VCap
Vertical sawtooth generator Capacitor
23
VOut
Vertical deflection drive Output for a DC-coupled output stage
24
EWOut
E/W Output
25
XRay
X-Ray protection input
26
HOut
Horizontal drive Output
27
GND
Main GrouND
28
BOut
B+ DC/DC converter controller Output
29
Vcc
Supply voltage
30
SCL
I2C bus Serial CLock Input
31
SDA
I2C bus Serial DAta input/output
32
VDyCor
Vertical Dynamic Correction output
6/51
TDA9112
4 - QUICK REFERENCE DATA
Characteristic
General
Package
Supply voltage
Supply current
Application category
Means of control/Maximum clock frequency
EW drive
DC/DC converter controller
Horizontal section
Frequency range
Autosync frequency ratio (can be enlarged in application)
Positive/Negative polarity of horizontal sync signal/Automatic adaptation
Duty cycle range of the drive signal
Position adjustment range with respect to H period
Soft start/Soft stop feature
Hardware/Software PLL lock indication
Parrallelogram
Pin cushion asymmetry correction (also called Side pin balance)
Top/Bottom/Common corner asymmetry correction
Tracking of asymmetry corrections with vertical size & position
Horizontal moiré cancellation (int.) for Combined/Separated architecture
Vertical section
Frequency range
Autosync frequency range (150nF at VCap and 470nF at VAGCCap)
Positive/Negative polarity of vertical sync signal/Automatic adaptation
S-correction/C-correction/Super-flat tube characteristic
Vertical size/Vertical position adjustment
Vertical moiré cancellation (internal)
Vertical breathing compensation
EW section
Pin cushion correction
Keystone correction
Top/Bottom/Common corner correction
Horizontal size adjustment
Tracking of EW waveform with Frequency/Vertical size & position
Breathing compensation on EW waveform
Dynamic correction section (dyn. focus, dyn. brightness,...)
Vertical dynamic correction output VDyCor
Horizontal dynamic correction output HDyCor
Composite HV dynamic correction output HVDyCor
Tracking of horizontal waveform component with Horizontal size/EHT
Tracking of vertical waveforms (component) with V. size & position
DC/DC controller section
Step-up/Step-down conversion mode
Internal/External sawtooth configuration
Bus-controlled output voltage
Soft start/Soft stop feature
Positive (N-MOS)/Negative(P-MOS) polarity of BOut signal
Value
SDIP 32
12
65
High-end
I2C Bus/400
Yes
Yes
Unit
V
mA
kHz
15 to 150
4.28
Yes/Yes/Yes
30 to 65
±10
Yes/Yes
Yes/Yes
Yes
Yes
Yes/Yes/No
Yes
Yes/Yes
kHz
35 to 200
50 to 180
Yes/Yes/Yes
Yes/Yes/Yes
Yes/Yes
Yes
Yes
Hz
Hz
%
%
Yes
Yes
Yes/Yes/No
Yes
Yes/Yes
Yes
Yes
No
Yes
Yes/Yes
Yes
Yes/Yes
Yes/Yes
Yes
Yes/Yes
Yes/Yes
7/51
TDA9112
5 - ABSOLUTE MAXIMUM RATINGS
All voltages are given with respect to ground.
Currents flowing from the device (sourced) are signed negative. Currents flowing to the device are signed
positive.
Symbol
8/51
Parameter
Value
Min
Max
Unit
VCC
Supply voltage (pin Vcc)
-0.4
13.5
V
V(pin)
Pins HEHTIn, VEHTIn, XRay, HOut, BOut
Pins H/HVSyn, VSyn, SCL, SDA
Pins HLckVBk, CO, RO, HPLL1F, HPosF, HVDyCor, BRegIn,
BISense, VAGCCap, VCap, VDyCor, HOscF, VOscF
Pin HPLL2C
Pin HFly
-0.4
-0.4
-0.4
VCC
5.5
VRefO
V
V
V
-0.4
-0.4
VRefO/2
VRefO
V
V
-2000
2000
V
-40
150
°C
150
°C
VESD
ESD susceptibility
(human body model: discharge of 100pF through 1.5kΩ)
Tstg
Storage temperature
Tj
Junction temperature
TDA9112
6 - ELECTRICAL PARAMETERS AND OPERATING CONDITIONS
Medium (middle) value of an I2C Bus control or adjustment register composed of bits D0, D1,...,Dn is the
one having Dn at ”1” and all other bits at ”0”. Minimum value is the one with all bits at 0, maximum value
is the one with all at ”1”.
Currents flowing from the device (sourced) are signed negative. Currents flowing to the device are signed
positive.
TH is period of horizontal deflection.
6.1 - THERMAL DATA
Symbol
Tamb
R th(j-a)
Value
Parameter
Operating ambient temperature
0
Unit
°C
70
Junction-ambience thermal resistance
°C/W
65
6.2 - SUPPLY AND REFERENCE VOLTAGES
Tamb = 25°C
Symbol
Parameter
Value
Test Condit ions
Min.
VCC
Supply voltage at Vcc pin
ICC
Supply current to Vcc pin
VCC = 12V
10.8
VRefO
Reference output voltage at RefOut pin
VCC = 12V, IRefO= -2mA
IRefO
Current sourced by RefOut output
Units
Typ.
Max.
12
13.2
65
7.65
8.0
-5
V
mA
8.2
V
0
mA
6.3 - SYNCHRONIZATION INPUTS
Vcc = 12V, Tamb = 25°C
Symbol
Parameter
Value
Test Condit ions
Min.
VLoH/HVSyn
LOW level voltage on H/HVSyn
0
VHiH/HVSyn
HIGH level voltage on H/HVSyn
Typ.
Units
Max.
0.8
V
V
2.2
5
VLoVSyn
LOW level voltage on VSyn
0
0.8
V
V HiVSyn
HIGH level voltage on VSyn
2.2
5
V
R PdSyn
Internal pull-down on H/HVSyn, VSyn
100
250
kΩ
tPulseHSyn
H sync. pulse duration on H/HVSyn pin
0.5
tPulseHSyn/T H
tPulseVSyn
tPulseVSyn/T V
Proportion of H sync pulse to H period
Pin H/HVSyn
V sync. pulse duration
Pins H/HVSyn, VSyn
Proportion of V sync pulse to V period
Pins H/HVSyn, VSyn
µs
0.2
0.5
750
µs
0.15
textrV/T H
Proportion of sync pulse length to H peri- Pin H/HVSyn,
od for extraction as V sync pulse
cap. on pin CO = 820pF
0.21
tHPolDet
Polarity detection time (after change)
0.75
Pin H/HVSyn
175
0.3
ms
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TDA9112
6.4 - HORIZONTAL SECTION
Vcc = 12V, Tamb = 25°C
Symbol
Parameter
Value
Test Condit ions
Min.
Typ.
Units
Max.
PLL1
IRO
Current load on RO pin
C CO
Capacitance on CO pin
fHO
Frequency of hor. oscillator
fHO(0)
fHOCapt
(4)
∆f H O ( 0 )
----------------------------f HO ( 0) ⋅ ∆T
Temperature drift of free-running freq. (3)
∆fHO/∆VHO
Average horizontal oscillator sensitivity
R RO=5.23kΩ, CCO=820pF
27
fHO(0) = 28.5kHz
29
150
kHz
29.9
kHz
122
kHz
pF
28.5
-150
fHO(0) = 28.5kHz
VHOThrfr
H. oscill. control voltage on pin HPLL1F VRefO=8V
Threshold on H. oscill. control voltage on
V
=8V
HPLL1F pin for tracking of EW with freq. RefO
VHPosF
Control voltage on HPosF pin
VHO
mA
390
Free-running frequency of hor. oscill. (1)
Hor. PLL1 capture frequency
1.5
HPOS (Sad01):
1111111xb
1000000xb
0000000xb
ppm/°C
19.6
1.4
kHz/V
6.0
5.0
2.6
3.2
3.8
2.8
3.4
4.0
V
V
3.0
3.6
4.2
V
V
V
VHOThrLo
Bottom of hor. oscillator sawtooth(6)
1.6
V
V HOThrHi
Top of hor. oscillator sawtooth(6)
6.4
V
PLL2
RIn(HFly)
IInHFly
VThrHFly
V S(0)
Input impedance on HFly input
V(HFly) >VThrHFly (2)
Current into HFly input
At top of H flyback pulse
Voltage threshold on HFly input
300
0.6
No PLL2 phase modulation
H flyback lock middle point (6)
500
700
Ω
5
mA
0.7
V
4.0
V
1.6
V
VBotHPLL2C
Low clamping voltage on HPLL2C pin(5)
V TopHPLL2C
High clamping voltage on HPLL2C pin
(5)
tph(min)/TH
Min. advance of H-drive OFF before
middle of H flyback(7)
Null asym. correction
0
%
tph(max)/T H
Max. advance of H-drive OFF before
middle of H flyback(8)
Null asym. correction
44
%
3.9
4.05
4.2
V
H-drive output on pin HOut
IHOut
tHoff/T H
Current into HOut output
Output driven LOW
30
mA
Duty cycle of H-drive signal
HDUTY (Sad00):
x1111111b
x0000000b
Soft-start/Soft-stop value
27
65
85
%
%
%
HPOS (Sad01):
1111111xb
0000000xb
+11
-11
%
%
Picture geometry corrections throug h PLL1 & PLL2
tHph/T H
10/51
H-flyback (centre) static phase vs. sync
signal (via PLL1), see Figure 7
TDA9112
Symbol
Parameter
Value
Test Condit ions
Min.
Typ.
Units
Max.
PCAC (Sad11h) full span
(9)
tPCAC/T H
Contribution of pin cushion asymmetry
correction to phase of H-drive vs. static
phase (via PLL2), measured in corners
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
±1.0
±1.8
±2.8
%
%
%
±1.75
±2.2
±2.8
%
%
%
±1.75
%
±0.8
±2.0
±4.4
%
%
%
±0.8
±2.0
±4.4
%
%
%
PARAL (Sad12h) full span
(9)
tParalC/T H
Contribution of parallelogram correction
to phase of H-drive vs. static phase (via
PLL2), measured in corners
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
VPOS at max. or min.
VSIZE at minimum
TCAC (Sad13h) full
span(9)
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
tTCAC/TH
Contribution of top corner asymmetry
correction to phase of H-drive vs. static
phase (via PLL2), measured in corners
tBCAC/T H
BCAC (Sad14h) full
span(9)
Contribution of bottom corner asymmetry
correction to phase of H-drive vs. static VPOS at medium
phase (via PLL2), measured in corners VSIZE at minimum
VSIZE at medium
VSIZE at maximum
Note 1: Frequency at no sync signal condition. For correct operation, the frequency of the sync signal applied must
always be higher than the free-running frequency. The application must consider the spread of values of real
electrical components in RRO and CCO positions so as to always meet this condition. The formula to calculate
the free-running frequency is fHO(0)=0.12125/(R RO C CO)
Note 2: Base of NPN transistor with emitter to ground is internally connected on pin HFly through a series resistance of
about 500Ω and a resistance to ground of about 20kΩ.
Note 3: Evaluated and figured out during the device qualification phase. Informative. Not tested on every single unit.
Note 4: This capture range can be enlarged by external circuitry.
Note 5: The voltage on HPLL2C pin corresponds to immediate phase of leading edge of H-drive signal on HOut pin with
respect to internal horizontal oscillator sawtooth. It must be between the two clamping levels given. Voltage
equal to one of the clamping values indicates a marginal operation of PLL2 or non-locked state.
Note 6: Internal threshold. See Figure 6.
Note 7: The tph(min)/T H parameter is fixed by the application. For correct operation of asymmetry corrections through
dynamic phase modulation, this minimum must be increased by maximum of the total dynamic phase required
in the direction leading to bending of corners to the left. Marginal situation is indicated by reach of VTopHPLL2C
high clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 6.
Note 8: The tph(max)/T H parameter is fixed by the application. For correct operation of asymmetry corrections through
dynamic phase modulation, this maximum must be reduced by maximum of the total dynamic phase required in
the direction leading to bending of corners to the right. Marginal situation is indicated by reach of VBotHPLL2C
low clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 6.
Note 9: All other dynamic phase corrections of picture asymmetry set to their neutral (medium) positions.
11/51
TDA9112
6.5 - VERTICAL SECTION
VCC = 12V, Tamb = 25°C
Symbol
Parameter
Value
Test Conditions
Min.
AGC-controlled vertical oscillator sawtooth; VRefO = 8V
Ext. load resistance on
∆Vamp/Vamp(R=∞) ≤1%
R L(VAGCCap)
VAGCCap pin(10)
Typ.
Units
Max.
65
MΩ
VVOB
Sawtooth bottom voltage on
VCap pin(11)
No load on VOscF pin (11)
VVOT
Sawtooth top voltage on VCap
pin
AGC loop stabilized
V sync present
No V sync
tVODis
Sawtooth Discharge time
C VCap=150nF
80
µs
fVO(0)
Free-running frequency
C VCap=150nF
100
Hz
AGC loop capture frequency
CVCap=150nF
Sawtooth non-linearity (12)
AGC loop stabilized, (12)
0.5
%
S-correction range
AGC loop stabilized, (13)
tVR=1/4 TVR(15)
tVR=3/4 TVR
-5
+5
%
%
tVR=1/2 TVR(15)
CCOR (Sad0A):
x0000000b
x1000000b
x1111111b
-3
0
+3
%
%
%
AGC loop stabilized
fVOCapt(min)≤fVO≤fVOCapt(max)
200
ppm/Hz
VPOS (Sad08):
x0000000b
x1000000b
x1111111b
3.3
3.65
3.2
3.5
3.8
V
V
V
2.5
3.5
2.25
3.0
3.75
V
V
V
fVOCapt
∆V V Odev
--------------------------------V
( 16 )
1.85
1.95
2.1
5
4.9
50
V
V
V
185
Hz
V Oamp
∆V V OS – cor
-------------------------------V VOamp
AGC loop stabilized, (14)
∆V V OC – cor
-------------------------------V VOamp
∆V V Oamp
----------------------------------------V V Oamp ⋅ ∆fV O
C-correction range
Frequency drift of sawtooth
amplitude(17)(18)
Vertical output drive signal (on pin VOut);VRefO = 8V
Vmid(VOut)
Vamp
VoffVOut
Middle point on VOut sawtooth
Amplitude of VOut sawtooth
(peak-to-peak voltage)
VSIZE (Sad07):
x0000000b
x1000000b
x1111111b
2
Level on VOut pin at V-drive ”off” I Cbit VOutEn at 0
3.8
V
IVOut
Current delivered by VOut output
-5
5
mA
VVEHT
Control input voltage range on
VEHTIn pin
1
VRefO
V
∆V amp
-----------------------------------------V amp ⋅ ∆V V E HT
Breathing compensation
V VEHT>VRefO
V VEHT(min)≤VVEHT≤VRefO
0
2.5
%/V
%/V
Note 10: Value of acceptable cumulated parasitic load resistance due to humidity, AGC storage capacitor leakage, etc.,
for less than 1% of Vamp change.
12/51
TDA9112
Note 11: The threshold for VVOB is generated internally and routed to VOscF pin. Any DC current on this pin will
influence the value of VVOB.
Note 12: Maximum of deviation from an ideally linear sawtooth ramp at null SCOR (Sad09 at x0000000b) and null
CCOR (Sad0A at x1000000b). The same rate applies to V-drive signal on VOut pin.
Note 13: Maximum SCOR (Sad09 at x1111111b), null CCOR (Sad0A at x1000000b).
Note 14: Null SCOR (Sad09 at x0000000b).
Note 15: ”tVR” is time from the beginning of vertical ramp of V-drive signal on VOut pin. ”TVR” is the duration of this ramp,
see chapter TYPICAL OUTPUT WAVEFORMS and Figure 16.
Note 16: VVOamp = VVOT -VVOB
Note 17: The same rate applies to V-drive signal on VOut pin.
Note 18: Informative, not tested on each unit.
6.6 - EW DRIVE SECTION
VCC = 12V, Tamb = 25°C
Symbol
Parameter
Value
Test Conditions
Min.
Typ.
Units
Max.
Output voltage on EWOut pin
1.8
6.5
V
IEWOut
Current sourced by EWOut output
-1.5
0
mA
VHEHT
Control voltage range on HEHTIn pin
1
VRefO
V
VEW
(19)(22)(23)(30)
VEW-DC
∆V E W – DC
----------------------------∆V HE H T
∆V E W – DC
------------------------------------V E W – D C ⋅ ∆T
DC component of the EW-drive
signal on EWOut pin
Breathing compensation on
VEW-DC
tVR=1/2 TVR(15)
HSIZE (Sad10h):
0000000xb
1000000xb
1111111xb
(19)(20)(21)(22)
tVR=1/2 TVR(15)
VHEHT>VRefO
VHEHT(min)≤ VHEHT≤VRefO
Temperature drift of DC compo- (18)(19)(21)(23)(30)
nent of the EW-drive signal on
tVR=1/2 TVR(15)
EWOut pin
2
3.25
4.5
V
V
V
0
-0.125
V/V
V/V
100
ppm/°C
0
0.7
1.5
V
V
V
0.25
0.5
V
V
(19)(20)(21)(23)(24)(25)
(26)(30)
VEW-PCC
Pin cushion correction component of the EW-drive signal on
EWOut pin
VSIZE at maximum
PCC (Sad0C):
x0000000b
x1000000b
x1111111b
Tracking with VSIZE:
PCC at x1000000b
VSIZE (Sad07):
x0000000b
x1000000b
(19)(20)(21)(24)(27)(29)(30)
Tracking of PCC component of
V
[t = 0 ]
E W – P C C vr
----------------------------------------------------------------- the EW-drive signal with vertical
V
[t = T
]
E W – P C C vr
V R position adjustment
PCC at x1111111b
VPOS (Sad08):
x0000000b
x1111111b
0.52
1.92
13/51
TDA9112
Symbol
Parameter
Value
Test Conditions
Min.
Typ.
Units
Max.
(20)(21)(22)(23)(24)(27)(28)(30)
VEW-Key
Keystone correction component
of the EW-drive signal on
EWOut pin
VEW-TCor
Top corner correction component of the EW-drive signal on
EWOut pin
KEYST (Sad0D):
x0000000b
x1111111b
0.4
-0.4
V
V
-1.25
0
+1.25
V
V
V
-1.25
0
+1.25
V
V
V
0
20
%/V
%/V
0
1.75
%/V
%/V
(19)(21)(22)(23)(24)(25)(27)(30)
TCC (Sad0E):
x0000000b
x1000000b
x1111111b
(19)(20)(22)(23)(24)(26)(27)(30)
VEW-BCor
Bottom corner correction compo- BCC (Sad0F):
nent of the EW-drive signal on
x0000000b
EWOut pin
x1000000b
x1111111b
∆V
Tracking of EW-drive signal with VHO>VHOThrfr
EW
--------------------------------------------------------horizontal frequency (32)
VHO(min)≤VHO≤V HOThrfr
V
[f
] ⋅ ∆V
EW m ax
HO
∆V E W – A C
----------------------------------------------------V E W – A C ⋅ ∆V H EH T
(25)(26)
Breathing compensation on
VEW-AC(31)
VHEHT>VRefO
VHEHT(min)≤ VHEHT≤VRefO
Note 19: KEYST at medium (neutral) value.
Note 20: TCC at medium (neutral) value.
Note 21: BCC at medium (neutral) value.
Note 22: PCC at minimum value.
Note 23: VPOS at medium (neutral) value.
Note 24: HSIZE at minimum value.
Note 25: Defined as difference of (voltage at tVR=0) minus (voltage at tVR=1/2 TVR).
Note 26: Defined as difference of (voltage at tVR=TVR) minus (voltage at tVR=1/2 TVR).
Note 27: VSIZE at maximum value.
Note 28: Difference (voltage at tVR=0) minus (voltage at tVR=TVR).
Note 29: Ratio ”A/B”of parabola component voltage at tVR=0 versus parabola component voltage at tVR=TVR.
See Figure 2.
Note 30: VHEHT>VRefO, VVEHT>VRefO
Note 31: VEW-AC is sum of all components other than VEW-DC (contribution of PCC, keystone correction and corner
corrections).
Note 32: More precisely tracking with voltage on HPLL1F pin which itself depends on frequency at a rate given by
external components on PLL1 pins. VEW[fmax] is the value at condition VHO>VHOThrfr.
14/51
TDA9112
6.7 - DYNAMIC CORRECTION OUTPUTS SECTION
VCC = 12V, Tamb = 25°C
Symbol
Parameter
Value
Test Conditi ons
Min.
Typ.
Units
Max.
Composite Horizontal and Vertical Dynamic Correction output HVDyCor
IHVDyCor
Current delivered by HVDyCor
output
V HVD-DC
DC component of the drive signal
on HVDyCor output
∆V HV D – DC
---------------------------------------V H V D – D C ⋅ ∆T
-2
RL(HVDyCor)=10kΩ
Temperature drift of DC component (18)
of the drive signal on HVDyCor
0
mA
2.1
V
200
ppm/°C
3.7
1.5
0.9
V
V
V
(33)(34)
V HVD-H
Amplitude of H-parabola component of the drive signal on HVDyCor output
HDyCorTr Off
HVDC-HAMP (Sad04):
x0000000b
x1000000b
x1111111b
V
[ Tr H SOn ]
HV D – H
--------------------------------------------------------V
[ Tr H SOf f]
HV D – H
Impact of horizontal size adjustment on HVDyCor H-parabola
component (tracking) (35)
VHEHT constant
HSIZE (Sad10h):
0000000xb
1111111xb
(1.34)2
1
V
[ T rE H TOn]
HV D – H
------------------------------------------------------------V
[ T rE H TOf f]
HVD – H
Impact of voltage on HEHTIn input HSIZE constant
VHEHT>VRefO
on HVDyCor H-parabola component (36)
VHEHT=VRefO-4V
1
(1.07)2
tHVD-Hoffset/T H
tHVD-Hflat
Offset (phase) of H-parabola component of the drive signal on HVDyCor output (38)
HVDC-HSYM (Sad05):
x0000000b
x1000000b (39)
x1111111b
Duration of the flat part at the start
of H-parabola component of the
fHO=31kHz
drive signal on HVDyCor output (38)
+24.5
0
-24.5
%
%
%
500
ns
0
0.5
1
V
V
V
0.5
1.6
V
V
(23)
VHVD-V
VH V D – V [ t vr = 0 ]
----------------------------------------------------------V
[t = T
]
H V D – V vr
VR
Amplitude of V-parabola component of the drive signal on HVDyCor output
VSIZE at x1000000b
HVDC-VAMP (Sad06):
x0000000b
x1000000b
x1111111b
HVDC-VAMP at maximum
VSIZE (Sad07):
x0000000b
x1111111b
HVDC-VAMP at maxiTracking of V-parabola component mum
of the drive signal on HVDyCor out- VPOS (Sad08):
put with vertical position (37)
x0000000b
x1111111b
0.52
1.92
15/51
TDA9112
Symbol
Parameter
Value
Test Conditi ons
Min.
Typ.
Units
Max.
Vertical Dynamic Correction outpu t VDyCor
IVDyCor
Current delivered by VDyCor output
V VD-DC
DC component of the drive signal
on VDyCor output
-1.5
RL(VDyCor)=10kΩ
0
mA
4
V
0
0.5
1
V
V
V
0.6
1.6
V
V
(23)
IVVD-VI
V VD – V [ tvr = 0 ]
-------------------------------------------------V V D – V [ t vr = TV R ]
Amplitude of V-parabola on VDyCor output (40)
VSIZE at medium
VDC-AMP (Sad15h):
x0000000b
x1000000b
x1111111b
VDC-AMP at maximum
VSIZE (Sad07):
x0000000b
x1111111b
VDC-AMP at maximum
Tracking of V-parabola on VDyCor VPOS (Sad08):
output with vertical position (37)
x0000000b
x1111111b
0.52
1.92
Note 33: HVDC-VAMP at minimum.
Note 34: HVDC-HSYM at medium.
Note 35: Ratio of the amplitude at HDyCorTr=1 to the amplitude at HDyCorTr=0 (refer to chapter ”I2C Bus control
register map”) as a quadratic function of horizontal size adjustment.
Note 36: Ratio of the amplitude at HDyCorTr=1 to the amplitude at HDyCorTr=0 (refer to chapter ”I2C Bus control
register map”) as a quadratic function of VHEHT.
Note 37: Ratio ”A/B”of vertical parabola component voltage at tVR=0 versus vertical parabola component voltage at
tVR=TVR.
Note 38: Refer to Figure 14.
Note 39: Taken for reference at given position of HDyCorPh flag.
Note 40: Unsigned value. Polarity selection by VDyCorPol I2C Bus bit. Refer to section I2C Bus control register map.
16/51
TDA9112
6.8 - DC/DC CONTROLLER SECTION
VCC = 12V, Tamb = 25°C
Symbol
Parameter
Value
Test Condit ions
Min.
R B+FB
Ext. resistance applied between
BComp output and BRegIn input
AOLG
Open loop gain of error amplifier on
BRegIn input
Low frequency(18)
fUGBW
Unity gain bandwidth of error amplifier
on BRegIn input
(18)
IRI
Bias current delivered by regulation input BRegIn
IBComp
Output current capability of BComp
output.
ABIsense
Voltage gain on BISense input
VThrBIsCurr
Input current sourced by BISense input
tBOn
Conduction time of the power transistor
IBOut
Output current capability of BOut output
HBOutEn = ”Enable”
HBOutEn = ”Disable” (41)
100
dB
6
MHz
-0.2
µA
-0.5
2.0
mA
mA
2.22
V
0.5
1.98
2.1
µA
-1
TH - tHVD-Hflat
0
Saturation voltage of the internal output
IBOut=10mA
transistor on BOut
VBReg
Regulation reference for BRegIn voltage (42)
tBTrigDel / TH
kΩ
3
VBOSat
VThrBIsConf
Units
Max.
5
Threshold voltage on BISense input
corresponding to current limitation
IBIsense
Typ.
VRefO=8V
BREF (Sad03):
x0000000b
x1000000b
x1111111b
3.65
4.65
5.65
10
mA
0.25
0.4
V
3.85
4.9
5.9
4.05
5.15
6.15
V
V
V
Threshold on pin BISense to define the
VRefO=8V
DC/DC controller configuration (43)
6
V
Delay of BOut “Off-to-On” edge after
middle of flyback pulse, as part of TH
16
%
(44)
V(BIsense)≤VThrBIsConf
BOutPh = ”0”
Note 41: A current sink is provided by the BComp output while BOut is disabled.
Note 42: Internal reference related to VRefO. The same values to be found on pin BRegIn, while regulation loop is
stabilized.
Note 43: External sawtooth configuration is assumed for V(BIsense)≤VThrBIsConf, internal sawtooth configuration for
V(BIsense)>VThrBIsConf.
Note 44: Only applies to configuration specified in ”Test conditions” column, i.e. synchronization of BOut “Off-to-On”
edge with horizontal flyback signal. Refer to chapter ”DC/DC controller” for more details.
17/51
TDA9112
6.9 - MISCELLANEOUS
VCC = 12V, Tamb = 25°C
Symbol
Parameter
Value
Test Condit ions
Min.
Typ.
Units
Max.
Vertical blanking and horizontal lock indication composite output HLckVBk
ISinkLckBk
VOLckBk
Sink current to HLckVBk pin
Output voltage on HLckVBk output
(45)
V. blank
No
Yes
No
Yes
H. lock
Yes
Yes
No
No
100
µA
0.1
V
1.1
5
6
V
V
V
0
0.04
%
%
0
3
mV
mV
Horizontal moiré canceller
∆T H ( H – moi re )
--------------------------------------TH
Modulation of TH by H. moiré function
HMOIRE (Sad02):
x0000000b
x1111111b
Vertical moiré canceller
VV-moiré
Amplitude of modulation of V-drive
signal on VOut pin by vertical moiré.
VMOIRE (Sad0Bh):
x0000000b
x1111111b
Protection functions
VThrXRay
Input threshold on XRay input(46)
tXRayDelay
Delay time between XRay detection
event and protection action
2TH
VCCEn
VCC value for start of operation at VCC
ramp-up(47)
8.5
V
VCCDis
VCC value for stop of operation at VCC
ramp-down (47)
6.5
V
7.65
7.9
8.2
V
(18)(48)
Control voltages on HPosF pin for Soft start/stop operation
VHOn
Threshold for start/stop of H-drive signal
1
V
VBOn
Threshold for start/stop of B-drive signal
1.7
V
VHBNorm f
Threshold for full operational duty cycle
of H-drive and B-drive signals
2.4
VHPosF
Normal operation
Voltage on HPosF pin as function of ad- HPOS (Sad01)
justment of HPOS register
0000000xb
1111111xb
3.8
2.6
4.0
2.8
4.2
3.0
V
V
Note 45: Current sunk by the pin if the external voltage is higher than one the circuit tries to force.
Note 46: The threshold is equal to actual VRefO.
Note 47: In the regions of V CC where the device’s operation is disabled, the H-drive, V-drive and B+-drive signals on
HOut, VOut and BOut pins, resp., are inhibited, the I2C Bus does not accept any data and the XRayAlarm flag
is reset. Also see Figure 10
Note 48: See Figure 10
18/51
TDA9112
7 - TYPICAL OUTPUT WAVEFORMS
Note (49)
Function
Vertical Size
Sad
07
Pin
Byte
Waveform
x0000000
Vamp(min)
x1111111
Vamp(max)
Vmid(VOut)
VOut
Vmid(VOut)
3.5V
x0000000
Vertical
Position
08
VOut
Vmid(VOut)
x1000000
Vmid(VOut)
x0000000:
Null
09
3.5V
Vmid(VOut)
x1111111
S-correction
Effect on Screen
3.5V
VVOamp
VVOS-cor
VOut
x1111111:
Max.
VVOamp
0
1/4TVR
3/4TVR TVR t
VR
VVOamp
x0000000
VVOC-cor
0
C-correction
0A
VOut
x1000000 :
Null
1/2TVR
TVR t
VR
VVOamp
VVOamp
VVOC-cor
x1111111
0
1/2TVR
TVR t
VR
19/51
TDA9112
Function
Sad
Pin
Byte
x0000000:
Null
Vertical moiré
amplitude
Waveform
Vamp
nTV
(n-1)TV
0B
Effect on Screen
(n+1)TV
VOut
t
VV-moiré
x1111111: Vamp
Max.
nTV
(n-1)TV
0000000x
10h
TVR t
VR
1/2TVR
TVR t
VR
VEW-DC(max)
0
0D
1/2TVR
EWOut
1111111x
Keystone
correction
t
VEW-DC(min)
0
Horizontal size
(n+1)TV
x0000000
VEW-key
x1111111
VEW-key
VEW-DC
EWOut
VEW-DC
VEW-PCC(min)
x0000000
Pin cushion
correction
0
0C
EWOut
1/2TVR
T VR t
VR
VEW-PCC(max)
x1111111
0
1/2TVR
T VR tVR
VEW-TCor(max)
x1111111
Top corner
correction
0E
0
EWOut
1/2TVR
T VR t
VR
VEW-TCor(min)
x0000000
0
1/2TVR
T VR t
VR
VEW-TBot(max)
x1111111
Bottom corner
correction
0F
0
EWOut
1/2TVR
T VR t
VR
VEW-TBot(min)
x0000000
0
20/51
1/2TVR
T VR t
VR
TDA9112
Function
Sad
Pin
Byte
Waveform
Effect on Screen
static phase
tParalC(min)
x0000000
1/2TVR
0
12h
Internal
Parallelogram
correction
tParalC(max)
static phase
x1111111
1/2TVR
0
tPCAC(max)
x0000000
1/2TVR
0
11h
Internal
Pin cushion
asymmetry
correction
T VR t
VR
T VR t
VR
static
H-phase
T VR t
VR
tPCAC(max)
static
H-phase
x1111111
1/2TVR
0
T VR t
VR
tTCAC(min)
static
H-phase
x0000000
0
13h
Internal
Top corner
asymmetry
correction
1/2TVR
tTCAC(max)
x1111111
0
1/2TVR
T VR t
VR
static
H-phase
T VR tVR
tBCAC(min)
static
H-phase
x0000000
14h
0
Internal
Bottom corner
asymmetry
correction
x1111111
1/2TVR
static
H-phase
tBCAC(max)
0
1/2TVR
VVD-V(max)
0
1/2TVR
VVD-V(max)
15h
VDyCor
T VR t
VR
VDyCorPo
VVD-DC
01111111
Vertical
dynamic
correction
amplitude
T VR t
VR
x0000000
0
1/2TVR
VVD-V(max)
11111111
0
1/2TVR
T VR t
VR
VVD-DC
Application dependent
T VR t
VR
VDyCorPo
VVD-DC
T VR t
VR
21/51
TDA9112
Function
Sad
Pin
Byte
x0000000
HVDyCor
vertical
amplitude
Waveform
T VR t
VR
Application dependent
HVDyCor
VHVD-DC
VHVD-V(max)
0
04
&
05
1/2TVR
HVDyCor
x1111111
HVDyCor
horizontal
adjustments
VHVD-DC
VHVD-V(min)
0
06
Effect on Screen
1/2TVR
T VR t
VR
See Figure 14 on page 37
Application dependent
Note 49: For any H and V correction component of the waveforms on EWOut and VOut pins and for internal waveform
for corrections of H asymmetry, displayed in the table, the weight of the other relevant components is nullified
(minimum for parabola, S-correction, medium for keystone, all corner corrections, C-correction, parallelogram,
parabola asymmetry correction, written in corresponding registers).
22/51
TDA9112
8 - I2C BUS CONTROL REGISTER MAP
The device slave address is 8C in write mode and 8D in read mode.
Bold weight denotes default value at Power-On-Reset.
I2C Bus data in the adjustment register is buffered and internally applied with discharge of the vertical oscillator (50).
In order to ensure compatibility with future devices, all “Reserved” bits should be set to 0.
Sad
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
Reserved
0
0
0
0
0
0
WRITE MODE (SLAVE ADDRESS = 8C)
00
01
HDutySyncV
1: Synchro.
0: Asynchro.
HDUTY
0
0
0
1
0
0
0
0
0
0
03
B+SyncV
0: Asynchro.
1
0
0
04
HDyCorTr
0: Not active
1
0
0
HDyCorPh
1: Middle
0: Start
06
BOutPol
0: Type N
07
BOutPh
0: H-flyback
1: H-drive
1
0
0
08
EWTrHFr
0: No tracking
1
0
0
09
Reserved
1
0
0
0A
Reserved
1
0
0
0B
Reserved
0
0
0
0C
Reserved
1
0
0
0E
0F
10
Reserved
Reserved
Reserved
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
0
0
(Keystone correction)
0
0
(Top corner correction)
BCC
(Bottom corner correction)
0
0
0
0
0
TCC
HSIZE
1
0
(Pin cushion correction)
0
KEYST
0
(Vertical moiré amplitude)
0
PCC
0
(C-correction)
0
VMOIRE
0
(S-correction)
0
CCOR
0
(Vertical position)
0
SCOR
0
(Vertical size)
0
VPOS
0
(HVDyCor vertical amplitude)
0
VSIZE
0
(HVDyCor horizontal symmetry)
0
HVDC-VAMP
1
(HVDyCor horizontal amplitude)
0
HVDC-HSYM
05
(B+reference)
0
HVDC-HAMP
0
(Horizontal moiré amplitude)
0
BREF
0
(Horizontal position)
0
HMOIRE
02
0D
0
HPOS
HMoiré
1: Separated
0: Combined
(Horizontal duty cycle)
0
0
(Horizontal size)
0
23/51
TDA9112
Sad
11
D7
Reserved
12
Reserved
13
Reserved
14
Reserved
15
VDyCorPol
0: ”∪”
16
XRayReset
0: No effect
1: Reset
17
TV
0: Off(52)
D6
D5
D4
D3
PCAC
1
0
0
0
PARAL
D2
D1
D0
(Pin cushion asymmetry correction)
0
0
0
0
0
(Parallelogram correction)
1
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
VSyncAuto
1: On
VSyncSel
0:Comp
1:Sep
SDetReset
0: No effect
1: Reset
0
PLL1Pump
1: Fast
0: Slow
PLL1InhEn
1: On
HLockEn
1: On
TH
0: Off(52)
TVM
0: Off(52)
THM
0: Off(52)
BOHEdge
0: Falling
HBOutEn
0: Disable
VOutEn
0: Disable
BlankMode
1: Perm.
TCAC
(Top corner asymmetry correction)
0
BCAC
0
0
0
(Bottom corner asymmetry correction)
0
VDC-AMP
0
0
0
0
(Vertical dynamic correction amplitude)
READ MODE (SLAVE ADDRESS = 8D)
XX
(51)
HLock
0: Locked
1: Not locked
VLock
0: Locked
1: Not lock.
XRayAlarm
1: On
0: Off
Polarity detection
HVPol
1: Negative
VPol
1: Negative
Sync detection
VExtrDet
0: Not det.
HVDet
0: Not det.
VDet
0: Not det.
Note 50: With exception of HDUTY and BREF adjustments data that can take effect instantaneously if switches
HDutySyncV and B+SyncV are at 0 respectively.
Note 51: In Read Mode, the device always outputs data of the status register, regardless of sub address previously
selected.
Note 52: The TV, TH, TVM and THM bits are for testing purposes and must be kept at 0 by application.
Description of I2C Bus switches and flags
Write-to bits
Sad00/D7 - HDutySyncV
Synchronization of internal application of Horizontal Duty cycle data, buffered in I2C Bus latch,
with internal discharge of Vertical oscillator
0: Asynchronous mode, new data applied
with ACK bit of I2C Bus transfer on this sub
address
1: Synchronous mode
Sad02/D7 - HMoiré
Horizontal Moiré characteristics
0: Adapted to an architecture with EHT generated in deflection section
1: Adapted to an architecture with separated
deflection and EHT sections
24/51
Sad03/D7 - B+SyncV
Same as HDutySyncV , applicable for B+ reference data
Sad04/D7 - HDyCorTr
Tracking of Horizontal Dynamic Correction
waveform amplitude with Horizontal Size at adjustment and EHT variation (voltage of HEHTIn).
0: Not active
1: Active
Sad05/D7 - HDyCorPh
Phase of start of Horizontal Dynamic Correction
waveform (and B+ drive if in internal sawtooth
configuration) in relation to horizontal flyback
pulse.
0: Start of the flyback
1: Middle of the flyback
TDA9112
Sad06/D7 - BOutPol
Polarity of B+ drive signal on BOut pin
0: adapted to N type of power MOS - high
level to make it conductive
1: adapted to P type of power MOS - low level
to make it conductive
Sad07/D7 - BOutPh
Phase of start of B+ drive signal on BOut pin,
while in external sawtooth configuration
0: Just after horizontal flyback pulse
1: With one of edges of line drive signal on
HOut pin, selected by BOHEdge bit
Sad08/D7 - EWTrHFr
Tracking of all corrections contained in waveform on pin EWOut with Horizontal Frequency
0: Not active
1: Active
Sad15/D7 - VDyCorPol
Polarity of Vertical Dynamic Correction waveform (parabola)
0: Concave (minimum in the middle of the parabola)
1: Convex (maximum in the middle of the parabola)
Sad16/D0 - HLockEn
Enable of output of Horizontal PLL1 Lock/unlock
status signal on pin HLckVBk
0: Disabled, vertical blanking only on the pin
HLckVBk
1: Enabled
Sad16/D1 - PLL1InhEn
Enable of Inhibition of horizontal PLL1 during
extracted vertical synchronization pulse
0: Disabled, PLL1 is never inhibited
1: Enabled
Sad16/D2 - PLL1Pump
Horizontal PLL1 charge Pump current
0: Slow PLL1, low current
1: Fast PLL1, high current
Sad16/D4 - SDetReset
Reset to 0 of Synchronization Detection flags
VDet , HVDet and VExtrDet of status register effected with ACK bit of I2C Bus data transfer into register containing the SDetReset bit. Also see description of the flags.
0: No effect
1: Reset with automatic return of the bit to 0
Sad16/D5 - VSyncSel
Vertical Synchronization input Selection between the one extracted from composite HV signal on pin H/HVSyn and the one on pin VSyn.
No effect if VSyncAuto bit is at 1.
0: V. sync extracted from composite signal on
H/HVSyn pin selected
1: V. sync applied on VSyn pin selected
Sad16/D6 - VSyncAuto
Vertical Synchronization input selection Automatic mode. If enabled, the device automatically
selects between the vertical sync extracted from
composite HV signal on pin H/HVSyn and the
one on pin VSyn, based on detection mechanism. If both are present, the one coming first is
kept.
0: Disabled, selection done according to bit
VSyncSel
1: Enabled, the bit VSyncSel has no effect
Sad16/D7 - XRayReset
Reset to 0 of XRay flag of status register effected with ACK bit of I2C Bus data transfer into register containing the XRayReset bit. Also see description of the flag.
0: No effect
1: Reset with automatic return of the bit to 0
Sad17/D0 - BlankMode
Blanking operation Mode
0: Blanking pulse starting with detection of
vertical synchronization pulse and ending
with end of vertical oscillator discharge
(start of vertical sawtooth ramp on the VOut
pin)
1: Permanent blanking - high blanking level in
composite signal on pin HLckVBk is permanent
Sad17/D1 - VOutEn
Vertical Output Enable
0: Disabled, VoffVOut on VOut pin (see 6.5 Vertical section)
1: Enabled, vertical ramp with vertical position
offset on VOut pin
25/51
TDA9112
Sad17/D2 - HBOutEn
Horizontal and B+ Output Enable
0: Disabled, levels corresponding to “power
transistor off” on HOut and BOut pins (high
for HOut, high or low for BOut, depending
on BOutPol bit).
1: Enabled, horizontal deflection drive signal
on HOut pin providing that it is not inhibited
by another internal event (activated XRay
protection). B+ drive signal on BOut pin.
Programming the bit to 1 after prior value of 0,
will initiate soft start mechanism of horizontal
drive and of B+ DC/DC convertor if this is in external sawtooth configuration.
Sad17/D3 - BOHEdge
Selection of Edge of Horizontal drive signal to
phase B+ drive Output signal on BOut pin. Only
applies if DC/DC convertor is in external sawtooth configuration and the bit BOutPh is set to 1,
otherwise BOHEdge has no effect.
0: Falling edge
1: Rising edge
Sad17/D4,D5,D6,D7 - THM, TVM, TH, TV
Test bits. They must be kept at 0 level by application S/W.
Read-out flags
SadXX/D0 - VDet(53)
Flag indicating Detection of V synchronization
pulses on VSyn pin.
0: Not detected
1: Detected
SadXX/D1 - HVDet (53)
Flag indicating Detection of H or HV synchronization pulses applied on H/HVSyn pin. Once the
sync pulses are detected, the flag is set and
latched. Disappearance of the sync signal will
not lead to reset of the flag.
0: Not detected
1: Detected.
SadXX/D2 - VExtrDet (53)
Flag indicating Detection of Extracted Vertical
synchronization signal from composite H+V signal applied on H/HVSyn pin
0: Not detected
1: Detected
SadXX/D3 - VPol
Flag indicating Polarity of V synchronization
pulses applied on VSyn pin with respect to mean
level of the sync signal
0: Positive
1: Negative
SadXX/D4 - HVPol
Flag indicating Polarity of H or HV synchronization pulses applied on H/HVSyn pin with respect
to mean level of the sync signal
0: Positive
1: Negative
SadXX/D5 - XRayAlarm
Alarm indicating that an event of excessive voltage has passed on XRay pin. Can only be reset
to 0 through I2C Bus bit XRayReset or by poweron reset.
0: No excess since last reset of the bit
1: At least one event of excess appeared
since the last reset of the bit, HOut inhibited
SadXX/D6 - VLock
Status of “Locking” or stabilizing of Vertical oscillator amplitude to an internal reference by AGC
regulation loop.
0: Locked (amplitude stabilized)
1: Not locked (amplitude non-stabilized)
SadXX/D7 - HLock
Status of Locking of Horizontal PLL1
0: Locked
1: Not locked
Note 53: This flag, by its value of 1, indicates an event of detection of at least one synchronization pulse since its last
reset (by means of the SDetReset I2C Bus bit). This is to be taken into account by application S/W in a way that
enough time (at least the period between 2 synchronization pulses of analyzed signal) must be provided
between reset of the flag through SDetReset bit and validation of information provided in the flag after read-out
of status register.
26/51
TDA9112
9 - OPERATING DESCRIPTION
9.1 - SUPPLY AND CONTROL
9.1.1 - Power supply and voltage references
The device is designed for a typical value of power
supply voltage of 12 V.
In order to avoid erratic operation of the circuit at
power supply ramp-up or ramp-down, the value of
VCC is monitored. See Figure 1 and electrical
specifications. At switch-on, the device enters a
“normal operation” as the supply voltage exceeds
VCCEn and stays there until it decreases bellow
VCCDis. The two thresholds provide, by their difference, a hysteresis to bridge potential noise. Outside the “normal operation”, the signals on HOut,
BOut and VOut outputs are inhibited and the I2C
bus interface is inactive (high impedance on SDA,
SCL pins, no ACK), all I2C bus control registers
being reset to their default values (see chapter
I2C BUS CONTROL REGISTER MAP on
page 23).
Figure 1. Supply voltage monitoring
V(Vcc)
V CC
VCCEn
Disabled
hysteresis
Normal operation
V CCDis
Disabled
t
Internal thresholds in all parts of the circuit are derived from a common internal reference supply
VRefO that is lead out to RefOut pin for external filtering against ground as well as for external use
with load currents limited to IRefO. The filtering is
necessary to minimize interference in output signals, causing adverse effects like e.g. jitter.
9.1.2 - I2C Bus Control
The I2C bus is a 2 line bi-directional serial communication bus introduced by Philips. For its general
description, refer to corresponding Philips I2C bus
specification.
This device is an I2C bus slave, compatible with
fast (400kHz) I2C bus protocol, with write mode
slave address of 8C (read mode slave address
8D). Integrators are employed at the SCL (Serial
Clock) input and at the input buffer of the SDA (Serial Data) input/output to filter off the spikes up to
50ns.
The device supports multiple data byte messages
(with automatic incrementation of the I2C bus subaddress) as well as repeated Start Condition for
I2C bus subaddress change inside the I2C bus
messages. All I2C bus registers with specified I2C
bus subaddress are of WRITE ONLY type, whereas the status register providing a feedback information to the master I2C bus device has no attributed I2C bus subaddress and is of READ ONLY
type. The master I2C bus device reads this register
sending directly, after the Start Condition, the
READ device I2C bus slave address (8D) followed
by the register read-out, NAK (No Acknowledge)
signal and the Stop Condition.
For the I2C bus control register map, refer to chapter I2C BUS CONTROL REGISTER MAP on
page 23.
9.2 - SYNC. PROCESSOR
9.2.1 - Synchronization signals
The device has two inputs for TTL-level synchronization signals, both with hysteresis to avoid erratic
detection and with a pull-down resistor. On H/
HVSyn input, pure horizontal or composite horizontal/vertical signal is accepted. On VSyn input,
only pure vertical sync. signal is accepted. Both
positive and negative polarities may be applied on
either input, see Figure 2. Polarity detector and
programmable inverter are provided on each of
the two inputs. The signal applied on H/HVSyn pin,
after polarity treatment, is directly lead to horizontal part and to an extractor of vertical sync. pulses,
working on principle of integration, see Figure 3.
The vertical sync. signal applied to the vertical deflection processor is selected between the signal
extracted from the composite signal on H/HVSyn
input and the one applied on VSyn input. The selector is controlled by VSyncSel I2C bus bit.
Besides polarity detection, the device is capable of
detecting presence of sync. signals on each of the
inputs and at the output of vertical sync. extractor.
The information from all detectors is provided in
the I2C bus status register (5 flags: VDet, HVDet,
VExtrDet, VPol, HVPol). The device is equipped
with an automatic mode (switched on or off by
VSyncAuto I2C bus bit) that also uses the detection information.
27/51
TDA9112
Figure 2. Horizontal sync signal
Positive
TH
tPulseHSyn
Negative
show in real time the presence or absence of corresponding sync. signal. They are latched to 1 as
soon as a single sync. pulse is detected. In order
to reset them to 0 (all at once), a 1 must be written
into SDetReset I2C bus bit, the reset action taking
effect with ACK bit of the I2C bus transfer to the
register containing SDetReset bit. The detection
circuits are ready to capture another event (pulse).
See Note 53.
9.2.2 - Sync. presence detection flags
The sync. signal presence detection flags in the
status register (VDet, HVDet, VExtrDet) do not
Figure 3. Extraction of V-sync signal from H/V-sync signal
H/V-sync
TH
tPulseHsyn
Internal
Integration
textrV
Extracted
V-sync
9.2.3 - MCU controlled sync. selection mode
I2C bus bit VSyncAuto is set to 0. The MCU reads
the polarity and signal presence detection flags,
after setting the SDetReset bit to 1 and an appropriate delay, to obtain a true information of the signals applied, reads and evaluates this information
and controls the vertical signal selector accordingly. The MCU has no access to polarity inverters,
they are controlled automatically.
See also chapter I2C BUS CONTROL REGISTER
MAP.
9.2.4 - Automatic sync. selection mode
I2C bus bit VSyncAuto is set to 1. In this mode, the
device itself controls the I2C bus bits switching the
polarity inverters (HVPol, VPol) and the vertical
sync. signal selector (VSyncSel), using the information provided by the detection circuitry. If both
extracted and pure vertical sync. signals are
present, the one already selected is maintained.
No intervention of the MCU is necessary.
9.3 - HORIZONTAL SECTION
9.3.1 - General
The horizontal section consists of two PLLs with
various adjustments and corrections, working on
horizontal deflection frequency, then phase shift-
28/51
ing and output driving circuitry providing H-drive
signal on HOut pin. Input signal to the horizontal
section is output of the polarity inverter on H/
HVSyn input. The device ensures automatically
that this polarity be always positive.
9.3.2 - PLL1
The PLL1 block diagram is in Figure 5. It consists
of a voltage-controlled oscillator (VCO), a shaper
with adjustable threshold, a charge pump with inhibition circuit, a frequency and phase comparator
and timing circuitry. The goal of the PLL1 is to
make the VCO ramp signal match in frequency the
sync. signal and to lock this ramp in phase to the
sync. signal. On the screen, this offset results in
the change of horizontal position of the picture.
The loop, by tuning the VCO accordingly, gets and
maintains in coincidence the rising edge of input
sync. signal with signal REF1, deriving from the
VCO ramp by a comparator with threshold adjustable through HPOS I2C bus control. The coincidence is identified and flagged by lock detection
circuit on pin HLckVBk as well as by HLock I2C
bus flag.
The charge pump provides positive and negative
currents charging the external loop filter on HPosF
pin. The loop is independent of the trailing edge of
sync. signal and only locks to its leading edge. By
design, the PLL1 does not suffer from any dead
band even while locked. The speed of the PLL1
TDA9112
depends on current value provided by the charge
pump. While not locked, the current is very low, to
slow down the changes of VCO frequency and
thus protect the external power components at
sync. signal change. In locked state, the currents
are much higher, two different values being selectable via PLL1Pump I2C bus bit to provide a
means to control the PLL1 speed by S/W. Lower
value make the PLL1 slower, but more stable.
Higher values make it faster and less stable. In
general, the PLL1 speed should be higher for high
deflection frequencies. The response speed and
stability (jitter level) depend on the choice of external components making up the loop filter. A “CRC”
filter is generally used (see Figure 4 on page 29).
Figure 4. H-PLL1 filter configuration
HPLL1F
9
R2
C1
C2
The PLL1 is internally inhibited during extracted
vertical sync. pulse (if any) to avoid taking into account missing or wrong pulses on the phase comparator. Inhibition is obtained by forcing the charge
pump output to high impedance state. The inhibition mechanism can be disabled through
PLL1InhEn I2C bus bit.
The Figure 7, in its upper part, shows the position
of the VCO ramp signal in relation to input sync.
pulse for three different positions of adjustment of
horizontal position control HPOS.
Figure 5. Horizontal PLL1 block diagram
PLL1InhEn
V-sync (extracted)
(I2C)
Lock
Status
(pin & I2C)
PLL1
HPLL1F R0 C0 HOscF
9
Sync
Polarity
LOCK
DETECTOR
H/HVSyn
1
INPUT
INTERFACE
8
CHARGE
PUMP
VCO
HPosF
Low
Extracted
V-sync
REF1
4
PLL
INHIBITION
High
COMP
6
PLL1Pump
(I2C)
HOSC
10
SHAPER
HPOS
(I2C)
29/51
TDA9112
Figure 6. Horizontal oscillator (VCO) schematic diagram
I0
I0
(PLL1 filter)
HPLL1F 9
VHO
4
V HOThrHi
2
+
4 I0
VHOThrLo
HOscF
+
+
RS
Flip-Flop
RO 8
from charge pump
VCO discharge
control
6 CO
VHOThrHi
VHOThrLo
9.3.3 - Voltage controlled oscillator
The VCO makes part of both PLL1 and PLL2
loops, being an “output” to PLL1 and “input” to
PLL2. It delivers a linear sawtooth. Figure 6 explains its principle of operation. The linears are obtained by charging and discharging an external capacitor on pin CO, with currents proportional to the
current forced through an external resistor on pin
RO, which itself depends on the input tuning voltage VHO (filtered charge pump output). The rising
and falling linears are limited by VHOThrLo and
VHOThrHi thresholds filtered through HOscF pin.
At no signal condition, the VHO tuning voltage is
clamped to its minimum (see chapter ELECTRICAL PARAMETERS AND OPERATING CONDITIONS, part horizontal section), which corresponds to the free-running VCO frequency fHO(0).
Refer to Note 1 for formula to calculate this frequency using external components values. The ratio between the frequency corresponding to maximum VHO and the one corresponding to minimum
VHO (free-running frequency) is about 4.5. This
range can easily be increased in the application.
The PLL1 can only lock to input frequencies falling
inside these two limits.
9.3.4 - PLL2
The goal of the PLL2 is, by means of phasing the
signal driving the power deflection transistor, to
lock the middle of the horizontal flyback to a certain threshold of the VCO sawtooth. This internal
threshold is affected by geometry phase corrections, like e.g., parallelogram. The PLL2 is much
faster than PLL1 to be able to follow the dynamism
of phase modulation. The PLL2 control current
(see Figure 7) is significantly increased during discharge of vertical oscillator (during vertical retrace
period) to be able to make up for the difference of
dynamic phase at the bottom and at the top of the
picture. The PLL2 control current is integrated on
30/51
the external filter on pin HPLL2C to obtain
smoothed voltage, used, in comparison with VCO
ramp, as a threshold for H-drive rising edge generation.
As both leading and trailing edges of the H-drive
signal in the Figure 7 must fall inside the rising part
of the VCO ramp, an optimum middle position of
the threshold has been found to provide enough
margin for horizontal output transistor storage time
as well as for the trailing edge of H-drive signal
with maximum duty cycle. Yet, the constraints
thereof must be taken into account while considering the application frequency range and H-flyback
duration. The Figure 7 also shows regions for rising and falling edges of the H-drive signal on HOut
pin. As it is forced high during the H-flyback pulse
and low during the VCO discharge period, no edge
during these two events takes effect.
The flyback input configuration is in Figure 8.
9.3.5 - Dynamic PLL2 phase control
The dynamic phase control of PLL2 is used to
compensate for picture asymmetry versus vertical
axis across the middle of the picture. It is done by
modulating the phase of the horizontal deflection
with respect to the incoming video (synchronization). Inside the device, the threshold VS(0) is compared with the VCO ramp, the PLL2 locking the
middle of H-flyback to the moment of their match.
The dynamic phase is obtained by modulation of
the threshold by correction waveforms. Refer to
Figure 12 and to chapter TYPICAL OUTPUT
WAVEFORMS. The correction waveforms have
no effect in vertical middle of the screen (for middle vertical position). As they are summed, their effect on the phase tends to reach maximum span at
top and bottom of the picture. As all the components of the resulting correction waveform (linear
for parallelogram correction, parabola of 2nd order
for Pin cushion asymmetry correction and half-pa-
TDA9112
rabolas of 4th order for corner corrections independently at the top and at the bottom) are generated from the output vertical deflection drive waveform, they all track with real vertical amplitude and
position (including breathing compensation), thus
being fixed on the screen. Refer to I2C BUS CONTROL REGISTER MAP for details on I2C bus controls.
Figure 7. Horizontal timing diagram
tHph
min
HPOS
(I2C)
max
H-sync
(polarized)
PLL1 lock
REF1
(internal)
VHOThrHi
VHPosF
max.
med.
min.
H-Osc
(VCO)
PLL1
max.
med.
min.
VS(0)
Figure 9. HOut configuration
26 HOut
int.
ext.
VHOThrLo
7/8T H
TH
tS
PLL2
control
current
PLL2
VThrHFly
H-flyback
H-drive
(on HOut)
flag set to 1) and when I2C bus bit HBOutEn is set
to 0 (default position).
The duty cycle of the H-drive signal is controlled
via I2C bus register HDUTY. This is overruled during soft-start and soft-stop procedures (see sub
chapter Soft-start and soft-stop on H-drive on
page 31 and Figure 10).
The PLL2 is followed by a rapid phase shifting
which accepts the signal from H-moiré canceller
(see sub chapter Horizontal moiré cancellation on
page 31)
The output stage consists of a NPN bipolar transistor, the collector of which is routed to HOut pin
(see Figure 9).
+
-
ON
OFF
ON
tHoff
forced high
H-drive
region
forced low
tph(max)
H-drive
region
inhibited
tS: HOT storage time
Figure 8. HFly input configuration
~500Ω
HFly 12
~20kΩ
ext.
int.
GND
9.3.6 - Output Section
The H-drive signal is inhibited (high level) during
flyback pulse, and also when VCC is too low, when
X-ray protection is activated (XRayAlarm I2C bus
Non-conductive state of HOT (Horizontal Output
Transistor) must correspond to non-conductive
state of the device output transistor.
9.3.7 - Soft-start and soft-stop on H-drive
The soft-start and soft-stop procedure is carried
out at each switch-on or switch-off of the H-drive
signal, either via HBOutEn I2C bus bit or after reset of XRayAlarm I2C bus flag, to protect external
power components. By its second function, the external capacitor on pin HPosF is used to time out
this procedure, during which the duty cycle of Hdrive signal starts at its maximum (“tHoff/TH for soft
start/stop” in electrical specifications) and slowly
decreases to the value determined by the control
I2C bus register HDUTY (vice versa at soft-stop).
This is controlled by voltage on pin HPosF. See
Figure 10 and sub chapter Safety functions on
page 39.
9.3.8 - Horizontal moiré cancellation
The horizontal moiré canceller is intended to blur a
potential beat between the horizontal video pixel
period and the CRT pixel width, which causes visible moiré patterns in the picture.
It introduces a microscopic indent on horizontal
scan lines by injecting little controlled phase shifts
to output circuitry of the horizontal section. Their
amplitude is adjustable through HMOIRE I2C bus
control.
The behaviour of horizontal moiré is to be optimised for different deflection design configurations
using HMoiré I2C bus bit. This bit is to be kept at 0
31/51
TDA9112
for common architecture (B+ and EHT common
regulation) and at 1 for separated architecture (B+
and EHT each regulated separately).
Figure 10. Control of HOut and BOut at start/stop at nominal Vcc
minimum value
VHPosMin
V(HPosF)
HPOS (I2C)
range
VHPosMax
maximum value
VHBNorm
V BOn
V HOn
Soft start
Start
HOut
Normal operation
Soft stop
Stop
BOut
Start
BOut
Stop
HOut
t
HOut
100%
H-duty cycle
BOut (positive)
B-duty cycle
9.4 - VERTICAL SECTION
9.4.1 - General
The goal of the vertical section is to drive vertical
deflection output stage. It delivers a sawtooth
waveform with an amplitude independent of deflection frequency, on which vertical geometry corrections of C- and S-type are superimposed (see
chapter TYPICAL OUTPUT WAVEFORMS).
Block diagram is in Figure 11. The sawtooth is obtained by charging an external capacitor on pin
VCap with controlled current and by discharging it
via transistor Q1. This is controlled by the CONTROLLER. The charging starts when the voltage
across the capacitor drops below VVOB threshold.
The discharging starts either when it exceeds VVOT
threshold or a short time after arrival of synchronization pulse. This time is necessary for the AGC
loop to sample the voltage at the top of the sawtooth. The V VOB reference is routed out onto VOscF pin in order to allow for further filtration.
The charging current influences amplitude and
shape of the sawtooth. Just before the discharge,
the voltage across the capacitor on pin VCap is
sampled and stored on a storage capacitor connected on pin VAGCCap. During the following ver-
32/51
0%
tical period, this voltage is compared to internal
reference REF (VVOT), the result thereof controlling the gain of the transconductance amplifier providing the charging current. Speed of this AGC
loop depends on the storage capacitance on pin
VAGCCap. The VLock I2C bus flag is set to 1
when the loop is stabilized, i.e. when the voltage
on pin VAGCCap matches VVOT value. On the
screen, this corresponds to stabilized vertical size
of picture. After a change of frequency on the
sync. input, the stabilization time depends on the
frequency difference and on the capacitor value.
The lower its value, the shorter the stabilization
time, but on the other hand, the lower the loop stability. A practical compromise is a capacitance of
470nF. The leakage current of this capacitor results in difference in amplitude between low and
high frequencies. The higher its parallel resistance
RL(VAGCCap), the lower this difference.
When the synchronization pulse is not present, the
charging current is fixed. As a consequence, the
free-running frequency fVO(0) only depends on the
value of the capacitor on pin VCap. It can be
roughly calculated using the following formula
fVO(0) =
150nF
C(VCap)
. 100Hz
TDA9112
The biasing voltage for external DC-coupled vertical power amplifier is to be derived from VRefO
voltage provided on pin RefOut, using a resistor divider, this to ensure the same temperature drift of
mean (DC) levels on both differential inputs and to
compensate for spread of VRefO value (and so
mean output value) between particular devices.
9.4.2 - Vertical moiré
To blur the interaction of deflection lines with CRT
mask grid pitch that can generate moiré pattern,
the picture position is to be alternated at frame frequency. For this purpose, a square waveform at
half-frame frequency is superimposed on the output waveform’s DC value. Its amplitude is adjustable through VMOIRE I2C bus control.
The frequency range in which the AGC loop can
regulate the amplitude also depends on this capacitor.
The C- and S-corrections of shape serve to compensate for the vertical deflection system non-linearity. They are controlled via CCOR and SCOR
I2C bus controls.
Shape-corrected sawtooth with regulated amplitude is lead to amplitude control stage. The discharge exponential is replaced by VVOB level,
which, under control of the CONTROLLER, creates a rapid falling edge and a flat part before beginning of new ramp. DC value of the waveform
output on pin VOut is adjusted by means of VPOS
I2C bus control, its amplitude through VSIZE I2C
bus control. Vertical moiré is superimposed.
Figure 11. Vertical section block diagram
Transconductance amplifier
Charge current
OSC
Cap.
REF
VCap
22
Sampling
Discharge
VSyn 2
Synchro
Controller
Q1
20 VAGCCap
Sampling
Capacitance
S-correction
SCOR (I2C)
Polarity
CCOR (I2C)
C-correction
sawtooth
discharge
18 VEHTIn
23 VOut
VVOB
VSIZE
(I2C)
19
VOscF
VMOIRE (I2C)
VPOS (I2C)
9.5 - EW DRIVE SECTION
The goal of the EW drive section is to provide, on
pin EWOut, a waveform which, used by an external DC-coupled power stage, serves to compensate for those geometry errors of the picture that
are symmetric versus vertical axis across the middle of the picture.
The waveform consists of an adjustable DC value,
corresponding to horizontal size, a parabola of 2nd
order for “pin cushion” correction, a linear for “keystone” correction and independent half-parabolas
of 4th order for top and bottom corner corrections.
All of them are adjustable via I2C bus, see I2C
BUS CONTROL REGISTER MAP chapter.
Refer to Figure 12, Figure 13 and to chapter TYPICAL OUTPUT WAVEFORMS. The correction
33/51
TDA9112
waveforms have no effect in the vertical middle of
the screen (if the VPOS control is adjusted to its
medium value). As they are summed, the resulting
waveform tends to reach its maximum span at top
and bottom of the picture. The voltage at the
EWOut is top and bottom limited (see parameter
VEW). According to Figure 13, especially the bottom limitation seems to be critical for maximum
horizontal size (minimum DC). Actually it is not
critical since the parabola component must always
be applied. As all the components of the resulting
correction waveform are generated from the output vertical deflection drive waveform, they all
track with real vertical amplitude and position (including breathing compensation), thus being fixed
vertically on the screen. They are also affected by
C- and S-corrections. The sum of components other than DC is affected by value in HSIZE I2C bus
control in reversed sense. Refer to electrical spec-
34/51
ifications for value. The DC value, adjusted via
HSIZE control, is also affected by voltage on HEHTIn input, thus providing a horizontal breathing
compensation (see electrical specifications for value). The resulting waveform is conditionally multiplied with voltage on HPLL1F, which depends on
frequency. Refer to electrical specifications for value and more precision. This tracking with frequency provides a rough compensation of variation of
picture geometry with frequency and allows to fix
the adjustment ranges of I2C bus controls throughout the operating range of horizontal frequencies.
It can be switched off by EWTrHFr I2C bus bit (off
by default).
The EW waveform signal is buffered by an NPN
emitter follower, the emitter of which is directly
routed to EWOut output, with no internal resistor to
ground. It is to be biased externally.
TDA9112
Figure 12. Geometric corrections’ schematic diagram
Controls:
HVDC-HAMP (I2C)
HVDC-HSYM (I2C)
one-quadrant
Tracking
HEHTIn/HSize
HDyCorTr (I2C)
VDC-AMP (I2C)
VDyCorPol (I2C)
two-quadrant
H-dynamic
correction
32
VDyCor
Vmid(VOut)
HVDC-VAMP
(I2C)
2
VOut
HVDyCor
11
23
Vertical ramp
Top parabola
generator
2
TCC (I2C)
PCC (I2C)
Tracking
HEHTIn/HSize
17
BCC (I2C)
2
HSize
KEYST (I2C)
Tracking
with Hor
Frequency
HEHTIn
PCAC (I2C)
Bottom parabola
generator
TCAC (I2C)
To horizontal
dyn. phase control
24 EWOut
BCAC (I2C)
PARAL (I2C)
35/51
TDA9112
Figure 13. EWOut output waveforms
V(EWOut)
VEW(max)
VEW-DC
VEW-Key
VEW-TCor
VEW-PCC
ma
xim
VEW operating range
HSIZE (I2C)
um
non-authorized region
VEW-BCor
me
diu
min
im
m
um
VEW(min)
Top
Keystone
alone
PCC
alone
Bottom
Corners
alone
Breathing
compensation
VHEHT(min)
VRefO
V(VCap)
V(HEHT)
Vertical sawtooth
0
T VR
0
TVR
9.6 - DYNAMIC CORRECTION
OUTPUTS SECTION
9.6.1 - Composite horizontal and vertical
dynamic correction output HVDyCor
A composite waveform is output on pin HVDyCor.
It consists of a parabola of vertical deflection frequency, on which a parabola of horizontal deflection frequency is superimposed. The two parabolic
components can independently be adjusted via
I2C bus, the vertical parabola in amplitude (HVDCVAMP I2C bus control), the horizontal parabola in
amplitude and phase (HVDC-HAMP and HVDCHSYM I2C bus controls). See also I2C BUS CONTROL REGISTER MAP chapter. The influence of
the vertical component can be nullified by adjusting its control to minimum. The minimum value in
horizontal parabola amplitude I2C bus control
does not correspond to null horizontal amplitude.
Refer to Figure 14. The phase of the horizontal parabola can roughly be adjusted via HDyCorPh I2C
bus bit to coincide either with the beginning or the
36/51
0
T VR
tVR
middle of the H-flyback pulse. Moreover, its centre
can be offset via HVDC-HSYM I2C bus control.
There is a flat part of a quasi-constant length at the
beginning of the horizontal parabola. Refer to electrical specifications for values.
As the vertical parabola component is generated
from the output vertical deflection drive waveform
(see Figure 12), it tracks with real vertical amplitude and position (including breathing compensation). It is also affected by C- and S-corrections.
The horizontal parabola component tracks with
value in HSIZE control and is horizontal breathing
compensated if HDyCorTr I2C bit is set to 1 (0 by
default).
9.6.2 - Vertical dynamic correction output
VDyCor
A parabola at vertical deflection frequency is available on pin VDyCor. Its amplitude is adjustable via
VDC-AMP I2C bus control and polarity controlled
via VDyCorPol I2C bus bit. It tracks with real vertical
amplitude and position (including breathing com-
TDA9112
pensation). It is also affected by C- and S-corrections.
The use of both correction waveforms is up to the
application (e.g. dynamic focus).
Figure 14. HVDyCor output horizontal component waveform
VHVD-H
TH
tHVD-Hflat
tHVD-Hoffset
tHVD-Hoffset
(min)
(max)
V HVD-DC
1
Shaped H-flyback
0
HDyCorPh (I2C)
9.7 - DC/DC CONTROLLER SECTION
The section is designed to control a switch-mode
DC/DC converter. A switch-mode DC/DC convertor generates a DC voltage from a DC voltage of
different value (higher or lower) with little power
losses. The DC/DC controller is synchronized to
horizontal deflection frequency to minimize potential interference into the picture.
Its operation is similar to that of standard UC3842.
The schematic diagram of the DC/DC controller is
in Figure 15. The BOut output controls an external
switching circuit (a MOS transistor) delivering
pulses synchronized on horizontal deflection frequency, the phase of which depends on H/W and
I2C bus configuration, see the table at the end of
this chapter. Their duration depends on the feedback provided to the circuit, generally a copy of
DC/DC converter output voltage and a copy of current passing through the DC/DC converter circuitry
(e.g. current through external power component).
The polarity of the output can be controlled by
BOutPol I2C bus bit. A NPN transistor open-collector is routed out to the BOut pin.
9.7.1 - External sawtooth configuration
External sawtooth configuration is assumed when
the voltage on BISense pin is lower than VThrBIsConf
threshold. During the operation, a sawtooth is to
be found on pin BISense, generated externally by
the application. The switches S1 and S2 are in
“ext.” position. According to BOutPh I2C bus bit,
the R-S flip-flop is set either at H-drive signal edge
(rising or falling, depending on BOHEdge I2C bus
bit), or a certain delay (tBTrigDel / TH) after middle
of H-flyback. The output is set On at the end of the
short pulse generated by the monostable trigger.
Timing of reset of the R-S flip-flop affects duty cycle of the output square signal and so the energy
transferred from DC/DC converter input to its output. A reset edge is provided by comparator C3 if
37/51
TDA9112
the voltage on pin BISense exceeds the internal
threshold VThrBIsCurr. This represents current limitation if a voltage proportional to the current
through the power component or deflection stage
is available on pin BISense. This threshold is affected by voltage on pin HPosF, which rises at soft
start and descends at soft stop. This ensures selfcontained soft control of duty cycle of the output
signal on pin BOut. Refer to Figure 10. Another
condition for reset of the R-S flip-flop, OR-ed with
the one described before, is that the voltage on pin
BISense exceeds the voltage VC2, which depends
on the voltage applied on input BISense of the error amplifier O1. The two voltages are compared,
and the reset signal generated by the comparator
C2. The error amplifier amplifies (with a factor defined by external components) the difference between the input voltage proportional to DC/DC
convertor output voltage and internal reference
VBReg. The internal reference and so the output
voltage is I2C bus adjustable by means of BREF
I2C bus control.
Both step-up (DC/DC converter output voltage
higher than its input voltage) and step-down (output voltage lower than input) are possible in this
configuration.
DC/DC controller Off-to-On edge timing
Configuration
Internal sawtooth
38/51
9.7.2 - Internal sawtooth configuration.
In internal sawtooth configuration, the voltage on
BISense pin is set higher than VThrBIsConf threshold, switching the switches S1 and S2 to “int.” position. Internal sawtooth needed to generate the
horizontal parabola component on HVDyCor output is used as reference for the comparison with
the regulated output voltage, and so for the timing
of the signal on BOut output. The R-S flip-flop is
set at the sawtooth discharge, which ends at the
beginning of a new sawtooth ramp. The high level
at the Q output of the R-S flip-flop only passes at
that moment thanks to invertor I1 and the NAND
gate. The Off-to-On edge at the output is thus synchronized to the beginning of the HVDyCor output
horizontal parabola. This can be positioned to the
beginning or middle of the H-flyback pulse, see
paragraph Composite horizontal and vertical dynamic correction output HVDyCor on page 36.
Timing of the R-S flip-flop reset only depends on
the voltage VC1 from the error amplifier, which operates in the same way like in external sawtooth
configuration, including reference voltage adjustment. As no current limitation is carried out, only a
step-down operation is possible in this configuration.
BOutPh
BOHEdge
(Sad07/D7)
(Sad17/D3)
Timing of Off-to-O n transition on BOut
output
don’t care
don’t care
Start of H-parab. on HVDyCor
External sawtooth
0
don’t care
Middle of H-flyback plus tBTrigDel
External sawtooth
1
0
Falling edge of H-drive signal
External sawtooth
1
1
Rising edge of H-drive signal
TDA9112
Figure 15. DC/DC converter controller block diagram
BOHEdge
BOutPh
(I2C)
(I2C)
int. Internal sawtooth configuration
ext. External sawtooth configuration
HDyCor sawtooth
discharge
S2
int.
H-drive edge
ext.
Monostable
I1
~500ns
H-flyback
(+delay)
VCC
HDyCor
sawtooth
VBReg
Feedback
+
O1
-
+
2R
R
VC1
-
VC2
-
BRegIn
I2
C1
C2
+
N type
int.
S1
S
BOut
Q
R
ext.
C3
+
VThrBIsCurr
I3
BOutPol
(I2C)
-
BComp
P type
HBOutEn
+
C4
-
Soft start
XRayAlarm
(I2C)
V ThrBIsConf
HPosF
BIsense
9.8 - MISCELLANEOUS
9.8.1 - Safety functions
The safety functions comprise supply voltage
monitoring with appropriate actions, soft start and
soft stop features on H-drive and B-drive signals
on HOut and BOut outputs and X-ray protection.
For supply voltage supervision, refer to paragraph
Power supply and voltage references on page 27
and Figure 1. A schematic diagram putting together all safety functions and composite PLL1 lock
and V-blanking indication is in Figure 16.
9.8.2 - Soft start and soft stop functions
For soft start and soft stop features for H-drive and
B-drive signal, refer to paragraph Soft-start and
soft-stop on
H-drive on
page 31
and
subchapter DC/DC CONTROLLER SECTION on
page 37, respectively. See also the Figure 10. Regardless why the H-drive or B-drive signal are
switched on or off (I2C bus command, power up or
down, X-ray protection), the signals always phase-
in and phase-out in the way drawn in the figure,
the first to phase-in and last to phase-out being the
H-drive signal, which is to better protect the power
stages at abrupt changes like switch-on and off.
The timing of phase-in and phase-out only depends on the capacitance connected to HPosF pin
which is virtually unlimited for this function. Yet it
has a dual function (see paragraph PLL1 on
page 28), so a compromise thereof is to be found.
9.8.3 - X-ray protection
The X-ray protection is activated if the voltage level on XRay input exceeds VThrXRay threshold. As a
consequence, the H-drive and B-drive signals on
HOut and BOut outputs are inhibited (switched off)
after a 2-horizontal deflection line delay provided
to avoid erratic excessive X-ray condition detection at short parasitic spikes. The XRayAlarm I2C
bus flag is set to 1 to inform the MCU.
This protection is latched; it may be reset either by
VCC drop or by I2C bus bit XRayReset(see chapter
I2C BUS CONTROL REGISTER MAP).
39/51
TDA9112
Figure 16. Safety functions - block diagram
HBOutEn
I2C
V CCEn
V CCDis
29
Vcc
HPosF
(timing) 10
VCC supervision
+
SOFT START
& STOP
_
XRayReset
I 2C
R
XRayAlarm
In
XRay
25
Out
S
:2
+
B-drive inhibit
R
_
H-drive inhibit
VThrXRay
HFly
12
I 2C
Q
+
H-drive inhibition
(overrule)
H-VCO
discharge
control
_
VThrHFly
V-drive inhibition
VOutEn
I 2C
B-drive inhibition
BlankMode
I 2C
HlockEn
I2C
L1=No blank/blank level
H-lock detector
V-sawtooth
discharge
Σ
HLckVbk
3
L3=L1+L2
L2=H-lock/unlock level
R
HLock
I2C
Q
S
V-sync
I2C I2C bit/flag
40/51
Int. signal
3 Pin
TDA9112
9.8.4 - Composite output HLckVBk
The composite output HLckVBk provides, at the
same time, information about lock state of PLL1
and early vertical blanking pulse. As both signals
have two logical levels, a four level signal is used
to define the combination of the two. Schematic diagram putting together all safety functions and
composite PLL1 lock and V-blanking indication is
in Figure 16, the combinations, their respective
levels and the HLckVBk configuration in Figure 17.
The early vertical blanking pulse is obtained by a
logic combination of vertical synchronization pulse
and pulse corresponding to vertical oscillator discharge. The combination corresponds to the drawing in Figure 17. The blanking pulse is started with
the leading edge of any of the two signals, whichever comes first. The blanking pulse is ended with
the trailing edge of vertical oscillator discharge
pulse. The device has no information about the
vertical retrace time. Therefore, it does not cover,
by the blanking pulse, the whole vertical retrace
period. By means of BlankMode I2C bus bit, when
at 1 (default), the blanking level (one of two according to PLL1 status) is made available on the
HLckVBk permanently. The permanent blanking,
irrespective of the BlankMode I2C bus bit, is also
provided if the supply voltage is low (under VCCEn
or VCCDis thresholds), if the X-ray protection is active or if the V-drive signal is disabled by VOutEn
I2C bus bit.
Figure 17. Levels on HLckVBk composite output
L1 - No blank/blank level
L2 - H-lock/unlock level
VCC
L1(H)+L2(H)
3 HLckVBk
L1(L)+L2(H)
ISinkLckBlk
L1(H)+L2(L)
V OLckBlk
L1(L)+L2(L)
V-early blanking
No
Yes
No
Yes
HPLL1 locked
Yes
Yes
No
No
41/51
TDA9112
Figure 18. Ground layout recommendations
32
1
2 TDA9112 31
30
3
29
4
28
5
27
6
26
7
8
25
24
9
23
10
11
22
21
12
20
13
19
14
18
15
16
17
42/51
General Ground
TDA9112
10 - INTERNAL SCHEMATICS
Figure 19.
Figure 22.
RefOut
12V
13
5V
5
Pins 1-2
H/HVSyn
VSyn
HPLL2C
200Ω
Figure 20.
Figure 23.
12V
12V
13 RefOut
RefOut
13
C0 6
HLckVBkl 3
Figure 21.
Figure 24.
12V
RefOut
13
12V
Pin 13
R0 8
HOSCF
Pin 4
43/51
TDA9112
Figure 25.
Figure 28.
12V
HPLL1F 9
HFly 12
Figure 26.
Figure 29.
12V RefOut
HPosF 10
BComp 14
Figure 27.
Figure 30.
12V
12V
12V
BRegIn 15
HVDyCor 11
44/51
TDA9112
Figure 31.
Figure 34.
12V
12V
BIsense 16
VAGCCap 20
Figure 32.
Figure 35.
12V
VCap 22
12V
18 VEHTIn
17 HEHTIn
Figure 33.
Figure 36.
12V
Pin 13
12V
VOSCF
19
VOut 23
45/51
TDA9112
Figure 37.
Figure 40.
12V
30 SCL
31SDA
24 EWOut
32 VDyCor
Figure 38.
12V
XRay
25
Figure 39.
12V
26 HOut
28 BOut
46/51
TDA9112
11 - PACKAGE MECHANICAL DATA
32 PINS - PLASTIC SHRINK
E
A
A1
A2
E1
L
C
B
e
B1
Stand-off
eA
eB
D
32
17
1
16
Dimensions
Millimeters
Inches
Min.
Typ.
Max.
Min.
Typ.
Max.
A
3.556
3.759
5.080
0.140
0.148
0.200
A1
0.508
0.020
A2
3.048
3.556
4.572
0.120
0.140
0.180
B
0.356
0.457
0.584
0.014
0.018
0.023
B1
0.762
1.016
1.397
0.030
0.040
0.055
C
.203
0.254
0.356
0.008
0.010
0.014
D
27.43
27.94
28.45
1.080
1.100
1.120
E
9.906
10.41
11.05
0.390
0.410
0.435
E1
7.620
8.890
9.398
0.300
0.350
0.370
e
1.778
0.070
eA
10.16
0.400
eB
L
12.70
2.540
3.048
3.810
0.500
0.100
0.120
0.150
47/51
TDA9112
12 - GLOSSARY
AC
ACK
Alternate Current
ACKnowledge bit of I2C-bus transfer
AGC
Automatic Gain Control
COMP
CRT
COMParator
Cathode Ray Tube
DC
Direct Current
EHT
EW
Extra High Voltage
East-West
H/W
HardWare
HOT
I2C
Horizontal Output Transistor
Inter-Integrated Circuit
IIC
Inter-Integrated Circuit
MCU
NAND
Micro-Controller Unit
Negated AND (logic operation)
NPN
Negative-Positive-Negative
OSC
PLL
OSCillator
Phase-Locked Loop
PNP
Positive-Negative-Positive
REF
RS, R-S
REFerence
Reset-Set
S/W
SoftWare
TTL
VCO
Transistor Transistor Logic
Voltage-Controlled Oscillator
48/51
TDA9112
revision follow-up
PRELIMINARY DATA
November 1999
corrections
version 3.1
December 1999
corrections
version 3.1
February 2000
some pin names changed
March 2000
corrections of pin names
April 2000
I2C register table
Few figures redone
version 3.2
May 2000
version 3.2
Few figure modified
Use of cross reference for electrical parameters
June 2000
version 3.4
Few changes on figures and text, intranet display
November 2000
version 3.4
New value for Horizontal moiré canceller: 0.02% instead of 0.04 previously
July 2000
version 3.5
Bloc diagram : addition of Hsize under E/W correction
Quick Reference Data: Addition of parrallelogram
Register Map: subaddress 08: 0:No tracking
Few corrections in text.
September 2000
Version 3.6
In Horizontal Moiré Cancellation: HMOIRE (pin) becomes HMOIRE (field register).
In vertical Dynamic correction Output: VDyCorPol (register) becomes VDyCorPol (bit).
January 2001
version 3.7
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TDA9112
page 7: value for autosync frequency ratio replaced : 4.28 instead of 4.5 previously
April 19, 2001
version 3.8
First display on Internet
Page 14: parameter VEW-BCor: correction of test condition: saOF instead of OE previously.
DATASHEET
April 27, 2001
version 4.0
New values from some electrical characteristics
page 9: VRefO
page10: VHPosF and VTopHPLL2C
page 12: VVOB
page 15: TBD mentions deleted
page 16: VThBlsCurr and VBReg
page 18: VThrXRay
and VPos changed to VHPosF + new values
May 14, 2001
version 4.1
page 18: horizontal moiré canceller: value corrected (0.04% instead of 0.02%)
June 29, 2001
version 4.1
July 2001
page32
9.4.1. right column”The higher its value,...” ---> ”The lower its value”
page 34 Section 9.5.”...at the vertical middle...” ---> ”...in the vertical middle...”
page 14EW DRIVE SECTION parameter ”∆VEW/VEW.∆VHO”, added [fmax]. and changed its
value to 20
Note 32: added: “VEW[fmax] is the value at condition VHO>VHOThrfr”.
page 32:
section 9.4 - “stabilizing time” changed to “stabilization time”
page 18
section 6.9 : max values for vertical and horizontal moiré cancellers moved to typ. values
November 5, 2001
version 4.2
page 13
last line in table, decreased font size in the formulae to make it readable
page 23
I2C bus control register map: two bits are reserved (sad 01D0 and sad 10D0)
page 35
figure 13 replaced
page 39
figure 15 corrected
pages 10, 18 replaced bit 0 value with x for HPOS
pages 13,15,20 replaced bit 0 value with x for HSIZE
TDA9112
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products are not authorized for use as critical components in life support devices or systems witho ut the express written approval of STMicroelectronics.
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2001 STMicroelectronics - All Rights Reserved.
2
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components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined
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