TDA9209 150 MHz PIXEL VIDEO CONTROLLER FOR MONITORS INCLUDING CUT-OFF INPUTS AND VIDEO DETECTION FEATURE ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 150 MHZ PIXEL RATE 2.7 ns RISE AND FALL TIME I2C BUS CONTROLLED GREY SCALE TRACKING VERSUS BRIGHTNESS OSD MIXING NEGATIVE FEED-BACK FOR DC COUPLING APPLICATION INTERNAL POSITIVE FEED-BACK FOR LCD APPLICATION 0.5~4.5 V DACs FOR BLACK LEVEL RESTORATION (AC-COUPLING APPLICATION) OR CUT-OFF CONTROLS (FOR DC-COUPLING APPLICATION USING THE ST AMPLIFIERS TDA9533/9530) BEAM CURRENT ATTENUATION (ABL) PEDESTRAL CLAMPING ON OUTPUT STAGE POSSIBILITY OF LIGHT OR DARK GREY OSD BACKGROUND OSD INDEPENDENT CONTRAST CONTROL ADJUSTABLE BANDWIDTH INPUT BLACK LEVEL CLAMPING WITH BUILT-IN CLAMPING PULSE STAND-BY MODE 5 V TO 8 V POWER SUPPLY SYNC CLIPPING FUNCTION (SOG) VIDEO DETECTION DESCRIPTION The TDA9209 is an I2C Bus controlled RGB preamplifier designed for Monitor application, able to mix the RGB signals coming from any OSD device. The usual Contrast, Brightness, Drive and Cut-Off Controls are provided. In addition, it includes the following features: – OSD contrast, – Bandwidth adjustment, – Grey background, – Internal back porch clamping pulse generator. SHRINK DIP24 (Shrink Plastic Package) ORDER CODE: TDA9209 The RGB incoming signals are amplified and shaped to drive any commonly used video amplifiers without intermediate follower stages. Even though encapsulated in a 24-pin package only, this IC allows any kind of CRT Cathode coupling : – AC coupling with DC restore, – DC coupling with Feed-back from Cathodes, – DC coupling with Cut-Off controls of the Video amplifier (ST Amplifiers TDA9533/9530). As for any ST Video pre-amplifier, the TDA9209 is able to drive a real load without any external interface. One of the main advantages of ST devices is their ability to sink and source currents while most of the devices from our competitors have problems to sink large currents. These driving capabilities combined with an original output stage structure suppress any static current on the output pins and therefore reduce dramatically the power dissipation of the device. Extensive integration combined with high performance and advanced features make the TDA9209 one of the best choice for any CRT Monitor in the 14” to 17” range. Perfectly matched with the ST Video Amplifiers TDA9530/33, these 2 products offer a complete solution for high performance and cost-optimized Video Board Application. Version 4.2 March 2000 1/22 1 TDA9209 1 - PIN CONNECTIONS IN1 ABL IN2 GNDL IN3 GNDA VCCA AV OSD1 OSD2 OSD3 FBLK 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 BLK HSYNC or BPCP CO1/FB1 OUT1 VCCP OUT2 GNDP OUT3 CO3/FB3 CO2/FB2 SDA SCL 2 - PIN DESCRIPTION Pin Number Symbol 1 2 IN1 ABL 3 4 IN2 GNDL Green Video Input Logic Ground 5 6 7 IN3 GNDA VCCA Blue Video Input Analog Ground Analog VCC (5V) 8 9 AV OSD1 Active Video Output Red OSD Input 10 11 OSD2 OSD3 Green OSD Input Blue OSD Input 12 13 14 FBLK SCL SDA Fast Blanking SCL SDA 15 16 17 CO2/FB2 CO3/FB3 OUT3 18 GNDP Power Ground 19 20 21 OUT2 VCCP OUT1 Green Video Output Power VCC (5 V to 8 V) Red Video Output 22 23 CO1/FB1 HSYNC BPCP 24 BLK 2/22 Description Red Video Input ABL Input Green Cut-off Output/Feedback Input Blue Cut-off Output/Feedback Input Blue Video Output Red Cut-off Output/Feedback Input HSYNC BPCP Blanking Input TDA9209 3 - BLOCK DIAGRAM TDA9209 BLK FBLK 24 12 VCCP 20 Output Clamp Pulse (OCL) Drive Contrast VREF 21 OUT1 Output Stage IN1 1 22 CO1/FB1 Clamp 19 OUT2 Green Channel IN2 3 15 CO2/FB2 16 CO3/FB3 Contrast/8bit ABL 2 Brightness Drive 8bits 3x8bits BPCP GNDL 17 OUT3 Blue Channel IN3 5 18 GNDP Latches I2C Bus Decoder 4 Cut-off 8bits GNDA 6 D/A IC Output DC Level 4bits OSD Cont. 4bits VCCA 7 VREF AV 8 23 HSYNC or BPCP 14 13 SDA SCL 9 OSD1 10 OSD2 11 OSD3 see Figure 12 for complete BPCP and OCL generation diagram 4 - FUNCTIONAL DESCRIPTION 4.1 RGB Input The three RGB inputs have to be supplied through coupling capacitors (100 nF). The maximum input peak-to-peak video amplitude is 1 V. The input stage includes a clamping function. The clamp uses the input serial capacitor as a ”memory capacitor”. To avoid a discharge of the serial capacitor during the line (due to leakage current), the input voltage is referenced to the ground. The clamp is gated by an internally generated ”Back Porch Clamping Pulse” (BPCP). Register 8 allows to choose the way to generate this BPCP (see Figure 1). When bit 0 is set to 0, the BPCP is synchronized on the trailing or leading edge of HSYNC (Pin 23) (bit 1 = 0: trailing edge, bit 1 = 1: leading edge). 3/22 TDA9209 Additionally, the IC automatically works with either positive or negative HSYNC pulses. – When bit 0 is set to 1, BPCP is synchronized on the leading edge of the blanking pulse BLK (Pin 24). One can use a positive or negative blanking pulse by programming bit 0 in Register 9 (See I 2C Table 3). – BPCP width can be adjusted with bit 2 and 3 (see Register 8, I2C table 2). – If the application already provides the Back Porch Clamping Pulse, bit 4 must be set to 1 (providing a direct connection between Pin 23 and internal BPCP). put) the synchro clipping function must be activated (bit 7 set to 1 in register 9) in order to keep the right green output levels and avoid unbalanced colours. 4.2 Synchro Clipping Function The contrast adjustment is made by controlling simultaneously the gain of the three internal amplifiers through the I2C bus interface. Register 1 allows the adjustment in a range of 48 dB. This function is available on channel 2 (Green Channel). When using the Sync On Green (SOG) (Synchro pulse included in the green channel in- 4.3 Blanking Input The Blanking pin (FBLK) is TTL compatible. The Blanking pulse can be: – positive or negative – line or Composite-type (but not Frame-type). 4.4 Contrast Adjustment (8 bits) Figure 1. R8b0=0 and R8b1=0 HSYNC/BPCP (Pin23) Internal BPCP R8b0=0 and R8b1=1 HSYNC/BPCP (Pin23) Internal BPCP R8b0=1 BLK (Pin24) Internal BPCP R8b4 =1 HSYNC/BPCP (Pin23) Internal BPCP 4.5 ABL Control The TDA9209 includes an ABL (automatic beam limitation) input to attenuate the RGB Video signals depending on the beam intensity. 4/22 The operating range is 2 V (from 3 V to 1 V). A typical 15 dB maximum attenuation is applied to the output signal whatever the contrast adjustment is. (See Figure 2 ). When the ABL feature is not used, the ABL input (Pin 2) must be connected to a 5 V supply voltage. TDA9209 Figure 2. Attenuation (dB) 0 -2 -4 -6 -8 -10 -12 -14 -16 0 VABL (V) 1 2 3 4 5 4.6 Brightness Adjustment (8 bits) Brightness adjustment is controlled by the I2C Bus via Register 2. It consists of adding the same DC voltage to the three RGB signals, after contrast adjustment. When the blanking pulse equals 0, the DC voltage is set to a value which can be adjusted between 0 and 2V with 8mV steps (see Figure 3). The DC output level is forced to the ”Infra Black” level (VDC) when the blanking pulse is equal to 1. 4.7 Drive Adjustment (3 x 8 bits) In order to adjust the white balance, the TDA9209 offers the possibility of adjusting separately the overall gain of each channel thanks to the I2C bus (Registers 3, 4 and 5). The very large drive adjustment range (48 dB) allows different standards or custom color temperatures. It can also be used to adjust the output voltages at the optimum amplitude to drive the CRT drivers, keeping the whole contrast control for the enduser only. The drive adjustment is located after the Contrast, Brightness and OSD switch blocks, so it does not affect the white balance setting when the BRT is adjusted. It also operates on the OSD portion of the signal. 4.8 OSD Inputs The TDA9209 allows to mix the OSD signals into the RGB main picture. The four pins dedicated to this function are the following: – Three TTL RGB inputs (Pins 9, 10, 11) connected to the three outputs of the corresponding OSD processor. – One TTL fast blanking input (Pin 12) also connected to the FBLK output of the OSD processor. When a high level is present on the FBLK, the IC acts as follows: – The three main picture RGB input signals (IN1, IN2, IN3) are internally switched to the internal input clamp reference voltage. – The three output signals are set to the voltage corresponding to the three OSD input logic states (0 or 1). (See Figure 3). If the OSD input is at low level, the output and brightness voltages (VBRT) are equal. If the OSD input is at high level, the output voltage is VOSD, where V OSD = VBRT + OSD and OSD is an I2C bus-controlled voltage. OSD varies between 0 V to 4.9 V by 320 mV steps via Register 7 (4 bits). The same variation is applied simultaneously to the three channels providing the OSD contrast. The grey color can be obtained on output signals when: – OSD1 = 1, OSD2 = 0 and OSD3 = 1, – A special bit (bit 5 or 6) in Register 9 is set to 1. If R9b5 is set to 1, light grey is obtained on output. If R9b6 is set to 1, dark grey is obtained on output. In the case where R9b5 and R9b6 are set to 0, the normal operation is provided on output signals. 4.9 Output Stage The overall waveforms of the output signal are shown in Figure 3 and Figure 4. The three output stages, which are large bandwidth output amplifiers, are able to deliver up to 4.4 VPP for 0.7 V PP on input. When a high level is applied on the BLK input (Pin 24), the three outputs are forced to ”Infra Black” level (VDC) thanks to a sample and hold circuit (described below). The black level (which is the output voltage outside the blanking pulse with minimum brightness and no Video input signals) is 400 mV higher than VDC. The brightness level (VBRT) is then obtained by programming register 2 (see I2C table 1). The sample and hold circuit is used to control the ”Infra Black” level in the range of 0.5 V to 2.5 V via Register 6 (in case of AC coupling) or Registers 10, 11, 12 (in case of DC coupling) . This sampling occurs during an internal pulse (OCL) generated inside the blanking pulse window. Refer to “CRT cathode coupling” part for further details. 5/22 TDA9209 Functioning with 5 V Power VCC To simplify the application, it is possible to supply the power VCC with 5 V (instead of 8 V nominal) at the expense of output swing voltage. Functioning without Blanking Pulse If no blanking pulse is applied to the TDA9209, the internal BPCP can be connected to the sample and hold circuit (Register 8, bit 7 = 1 and BLK pin grounded) so that the output DC level is still controlled by I2C. To ensure the device correct behavior in the worst possible conditions, the Brightness Register must be set to 0. Figure 3. Waveforms VOUT, BRT, CONT, OSD HSYNC BPCP BLK Video IN FBLK OSD IN (4) CONT (5) V OSD (3) VBRT (2) V BLACK VDC (1) VOUT1 , VOUT2 , VOUT3 V 6/22 OSD CONT BRT 0.4V fixed Notes : 1. VDC = 0.5 to 2.5V 2. VBLACK = V DC + 0.4V 3. VBRT = V BLACK + BRT (with BRT = 0 to 2V) 4. VCONT = V BRT + CONT = k x Video IN (CONT = 4.4VPP max. for VIN = 0.7V PP) 5. VOSD = V BRT + OSD (OSD max. = 4.9VPP , OSD min = 0VPP) TDA9209 Figure 4. Waveforms (Drive adjustment) HSYNC BPCP BLK Video IN BFLK OSD IN VOUT1, VOUT2, VOUT3 VCONT V OSD VBRT VBLACK VDC Two examples of drive adjustment (1) Note : 1.Drive adjustment modifies the following voltages : VCONT, VBRT and V OSD. Drive adjustment doesn’t modify the following voltages : VDC and VBLACK. 4.10 Bandwidth Adjustment A new feature: Bandwidth adjustment, has been implemented on the TDA9209. This function has several advantages: – Depending on the external capacitive load and on the peak-to-peak output voltage, the bandwidth can be adjusted to avoid any slew-rate phenomenon. – The preamp bandwidth can be adjusted in order to reduce electromagnetic radiation, since it is possible to slow down the signal rise/fall time at the CRT driver input without too much affecting the rise/fall time at the CRT driver output. – It is possible to optimize the ratio of the frequency response versus the CRT driver power consumption for any kind of chassis, as the preamp bandwidth adjustment also allows the adjustment of the rise/fall time on the cathode (through the CRT driver). – In still picture mode, when a high Video swing voltage is of greater interest than rise/fall time, bandwidth adjustment is used to avoid any slewrate phenomenon at the CRT driver output and to meet electromagnetic radiation requirements. 4.11 CRT Cathode Coupling The powerfull multiplex capability of the TDA9209 allows to use the device with several kinds of CRT cathode coupling. 4.11.1 AC coupling with DC restore ( Figure 5) In this mode the output DC level (VDC) is adjusted simultaneously for the 3 channels from 0.5 V to 2.35 V via Register 6 (4 bits). The cut-off voltage is programmed independently for each channel from 0.17 V to 4.6 V using registers 10, 11, 12 (8 bits each, see I2C Table 1). 7/22 TDA9209 4.11.2 DC Coupling with cut-off controls on Video Amplifier (with TDA9533/ 9530, Figure 6) The functioning and programming of the TDA9209 are the same as for the previous mode, except for 4.11.3 DC Coupling Mode (Figure 7) This is the most commonly used configuration enabling to build a powerful video system on a small PCB Board and giving a substantial cost saving compared with any other solution available on the market. The preamplifier outputs control directly the cut-off levels. The output DC level (VDC) is adjusted independently for each channel from 0.5 V to 2.5 V via registers 10, 11 and 12. In DC coupling mode, bit 2 must be set to 1 and bit3 to 0 in Register 9. the cut-off control which is now performed via the Video amplifier cut-off input . In AC coupling and DC coupling with cut-off control, bits 2, 3 and 4 in Register 9 must be set to 1. 4.11.4 DC Coupling with feedback mode (Fig. 8) In this mode, the feedback voltage issued from the cathode is sent to the TDA9209. This voltage is compared to a reference from the cut-off DC level DAC by the sample and hold circuit who also controls the DC voltage of the feedback input in a range of 0.5 V to 2.5 V. Each channel is independently controlled via Registers 10, 11 and 12. In DC coupling with feedback mode, bit 2 and bit 4 must be set to 0 in Register 9. Figure 5. AC Coupling TDA9209 Pins 17-19-21 CRT Driver CRT DC LEVEL (4bits) 0.5V to 2.35V CUT-OFF 1,2,3 DC LEVEL 0.17V to 4.6V(8bits) Pins15-16-22 Cut-off Control Figure 6. DC Coupling with Cut-off Control TDA9209 CRT Pins 17-19-21 TDA9533/9530 DC LEVEL (4bits) 0.5V to 2.35V CUT-OFF 1,2,3 DC LEVEL 0.17V to 4.6V (8bits) 8/22 Pins 15-16-22 TDA9209 Figure 7. DC Coupling TDA 9209 Pins17-19-21 CRT Driver CRT OUTPUT 1,2,3 DC LEVEL 0.5V to 2.5V (8bits) Figure 8. DC Coupling with Feedback (LCD mode) TDA 9209 Pins 17-19-21 CRT Driver CRT Pins 15-16-22 CUT-OFF 1,2,3 DC LEVEL 0.5V to 2.5V (8bits) 4.12 Stand-by Mode The TDA9209 has a stand-by mode. As soon as the VCC power (Pin 20) gets lower than 3V (typ.), the device is set in stand-by mode whatever the voltage on analog VCCA (Pin 7) is. The analog blocks are internally switched-off while the logic parts (I2C bus, power-on reset) are still supplied. In stand-by mode, the power consumption is below 20 mW. 4.13 Serial Interface The 2-wire serial interface is an I2C interface. The slave address of TDA9209 is DC hex. A6 A5 A4 A3 A2 A1 A0 W 1 1 0 1 1 1 0 0 The host MCU can write into the TDA9209 registers. Read mode is not available. In order to write data into the TDA9209, after the “start” message, the MCU must send the following data (see Figure 9): – the I2C address slave byte with a low level for the R/W bit, – the byte to the internal register address where the MCU wants to write data, – the data. All bytes are sent with MSB bit first. The transfer of written data is ended with a “stop” message. When transmitting several data, the register addresses and data can be written with no need to repeat the start and slave addresses. 9/22 TDA9209 4.14 Power-on Reset threshold for a rising supply on VCCA (Pin 7) is 3.8 V (typ.) and 3.2V when the VCC decreases. A power-on reset function is implemented on the TDA9209 so that the I2C registers have a determined status after power-on. The Power-on reset Figure 9. I2C Write Operation SCL W SDA Start I2C Slave Address A7 ACK A6 A5 A4 A3 A2 Register Address A1 D7 A0 D6 D5 D4 D3 D2 D1 Data Byte ACK D0 ACK Stop 4.15 Video detection (see Figure 10) The video detection consists of three fast comparators and a OR function. The positive input of each comparator is connected to the input video pin (R, G, or B). The negative inputs are connected together to a reference voltage. This voltage is the threshold of the comparators. The typical threshold voltage is 120 mV. The three comparator outputs are con- nected to the OR inputs. Active Video output can be inhibited by using bit 7 in Register 13 : R13b7 = 0 AV inhibited R13b7 = 1 AV validated When AV output is validated, the AV output reaches 5V when at least one of the 3 video inputs gets higher than 3.8V (typ.), and decreases to 0V if the 3 input voltages get lower than 3.2V (typ.). Figure 10. Video Detection IN1 1 IN2 3 8 IN3 5 120mV 10/22 R13b7=0 AV TDA9209 5 - ABSOLUTE MAXIMUM RATINGS Symbol Parameter Pin Value Units 7 20 5.5 8.8 V V - 5.5 V VCCA Max. VCCP Max. Supply Voltage on Analog VCC Supply Voltage on Power VCC Vin Max. Voltage at any Input Pins (except Video inputs) and Input/Output Pins VI Max. Voltage at Video Inputs 1, 3, 5 1.4 V Tstg Storage Temperature - - °C Toper Operating Junction Temperature - +150 °C 6 - THERMAL DATA Symbol Value Units R th(j-a) Max. Junction-ambient Thermal Resistance Parameter 69 °C/W Tj Typ. Junction Temperature at Tamb = 25°C 80 °C 7 - DC ELECTRICAL CHARACTERISTICS T amb = 25°C, VCCA = 5V, VCCP = 8V, unless otherwise specified. Symbol Parameter Test Conditions Min. Typ. Max. Units VCCA Analog Supply Voltage Pin 7 4.5 5 5.5 V VCCP Power Supply Voltage Pin 20 4.5 8 8.8 V ICCA Analog Supply Current VCCA = 5V 70 mA ICCP Power Supply Current VCCP = 8V 55 mA VI Video Input Voltage Amplitude 0.7 Vo Output Voltage Range 0.5 VI L VI H Low Level Input Voltage High Level Input Voltage OSD, FBLK, BLK, HSYNC IIN Input Current OSD, FBLK, BLK RHS Input Resistor HSYNC 1 V V CCP -0.5V V 0.8 V V 1 µA 2.4 -1 40 kΩ 11/22 TDA9209 8 - AC ELECTRICAL CHARACTERISTICS Tamb = 25°C, VCCA = 5V, VCCP= 8V, V i = 0.7 VPP, CLOAD = 5pF RS = 100Ω, serial between output pin and CLOAD, unless otherwise specified. Symbol Parameter Test Condit ions Min. Typ. Max. Units VIDEO INPUTS (PINS 1, 3, 5) VI Video Input Voltage Amplitude Max. Contrast and Drive 0.7 1 V VIDEO OUTPUT SIGNAL (PINS 17, 19, 21) - GENERAL GAM Maximum Gain Max Contrast and Drive (CRT = DRV = 254 dec) 16 dB VOM Maximum Video Output Voltage (Note) Max Contrast and Drive (CRT = DRV = 254 dec) 4.4 V Nominal Video Output Voltage Contrast and Drive at POR (CRT = DRV = 180 dec) 2.2 V Contrast Attenuation Range From max. Contrast (CRT=254 dec) 48 dB 48 dB ± 0.1 dB VON CAR to min. Contrast (CRT = 1 dec) DAR Drive Attenuation Range From Max. Drive (DRV = 254 dec) to min Drive (DRV = 1 dec) GM Gain Matching Contrast and Drive at POR tR, tF Rise Time, Fall Time (Note) BW Large Signal Bandwidth BW Bandwidth Adjustment Range CT Crosstalk between Video Outputs VOUT = 2 VPP (BW = 15 dec) VOUT = 2 VPP (BW = 0 dec) VOUT = 2 V PP 2.7 4.3 ns ns 130 MHz VOUT = 2 V PP Minimum bandwidth (BW = 0 dec) Maximum bandwidth (BW =15 dec) 80 130 MHz MHz 60 35 dB dB VOUT = 2 V PP @ f = 10 MHz @ f = 50 MHz VIDEO OUTPUT SIGNAL — BRIGHTNESS BRTmax Maximum Brightness Level Max. Brightness (BRT = 255 dec) and Max. Drive (DRV = 254 dec) 2 V BRTmin Minimum Brightness Level Min. Brightness (BRT = 0 dec) and Max. Drive (DRV = 254 dec) 0 V VIP Insertion Pulse 0.4 V BRTM Brightness Matching Brightness and Drive at POR ± 10 mV Max. Drive (DRV = 254 dec) Max. OSD (OSD = 15 dec) Min. OSD (OSD = 0 dec) 4.9 0 V V 2.35 0.5 V V 155 mV 2.5 0.4 V V 10 mV VIDEO OUTPUT SIGNAL — OSD OSDmax OSDmin Maximum OSD Output Level Minimum OSD Output Level VIDEO OUTPUT SIGNAL — DC LEVEL (AC COUPLING MODE) DCLmax DCLmin Maximum Output DC Level Minimum Output DC Level DCLstep Output DC Level Step Max. DCL (DCL= 15 dec) Min. DCL (DCL = 3 dec) VIDEO OUTPUT SIGNAL — DC LEVEL (DC COUPLING MODE) DCLmax DCLmin Maximum Output DC Level Minimum Output DC Level DCLstep Output DC Level Step Max. Cut-off (Cut-off = 255 dec) Min. Cut-off (Cut-off = 40 dec) Assuming that VOM remains within the range of Vo (between 0.5V and VCCP - 0.5V) tR, tF are calculated values, assuming an ideal input rise/fall time of 0ns (tR = tROUT2 + tRIN2 , tF = tFOUT2 + tFIN2 12/22 TDA9209 AC ELECTRICAL CHARACTERISTICS (continued) Tamb = 25°C, VCCA = 5V, VCCP= 8V, Vi = 0.7 VPP, C LOAD = 5 pF, unless otherwise specified Symbol Parameter Test Condit ions Min. Typ. Max. Units CUT-OFF OUTPUTS (AC COUPLING MODE) - (Pins 15, 16, 22) COmax Maximum Cut-off Output Level Max. Cut-off (Cut-off = 255 dec) and Sourced Current = 200µA 4.7 V COmin Minimum Cut-off Output Level Min. Cut-off (Cut-off = 0 dec) and Sinked Current = 2mA 0.1 V COTD Cut-off Output Voltage Drift Tj Variation = 100°C 0.5 % COHIin Maximum Cut-off Output Voltage (linear region) Cut-off =235dec (Sourced Current = 200µA) 4.6 V COLIin Minimum Cut-off Output Voltage (linear region) Cut-off = 10 dec (Sinked current = 2mA) 0.17 V COstep Cut-off Output Step (linear region) 20 mV Max. Cut-off (Cut-off = 255 dec) Min. Cut-off (Cut-off = 1 dec) 2.5 20 V mV 10 mV 50 µA FEEDBACK INPUTS (DC WITH FEEDBACK MODE) VFBmax VFBmin Controlled Feedback Input Level Maximum Minimum VFBstep Controlled Feedback Input Level Step IFB input Current on Feedback inputs V ≤ 2.5V GABLmin GABLmax ABL Mini Attenuation ABL Maxi Attenuation VABL = 1 V 0 15 dB dB VABL ABL Threshold Voltage For output attenuation 3 V IABLhigh IABLlow High ABL Input Current Low ABL Input Current VABL = 3.2V VABL = 1V 0 -2 µA µA 120 mV ABL (PIN 2) VABL ≥ 3.2 V VIDEO DETECTION VTHAV Comparator Threshold DELAY Delay between Video Output and AV output 3pF load on AV out (Pin8) 10 ns Pix AV Minimum pixel width Vin = 0.7VPP 10 ns 13/22 TDA9209 9 - I2C ELECTRICAL CHARACTERISTICS T amb = 25°C, VCCA = 5V, unless otherwise specified Symbol Parameter Test Conditi ons VIL Low Level Input Voltage VIH High Level Input Voltage IIN Input Current (Pins SDA, SCL) fSCL(Max.) SCL Maximum Clock Frequency VOL Min. Typ. On Pins SDA, SCL Max. Units 1.5 V -10 +10 µA 200 0.25 kHz 0.6 V 3 0.4 V < VIN < 4.5 V V SDA Pin Low Level Output Voltage when ACK Sink Current = 6mA 10 - I 2C INTERFACE TIMING REQUIREMENTS (see Figure 11) Symbol Parameter Min. Typ. Max. Units tBUF Time the bus must be free between two accesses 1300 ns tHDS Hold Time for Start Condition 600 ns tSUP Set-up Time for Stop Condition 600 ns tLOW The Low Period of Clock 1300 ns tHIGH The High Period of Clock 600 ns tHDAT Hold Time Data 300 ns tSUDAT Set-up Time Data 250 ns tR, tF Rise and Fall Time of both SDA and SCL 20 Figure 11. I2C Timing Diagram t t BUF HDAT SDA t t HDS SUDAT t SUP SCL t 14/22 HIGH t LOW 300 ns TDA9209 11 - I 2C REGISTER DESCRIPTION Register Sub-addressed - I2C Table 1 Sub-address Max. Value POR Value Register Names Hex Dec 01 01 Contrast (CRT) 02 02 Brightness (BRT) 8-bit DAC B4 180 FF 255 03 03 Drive 1 (DRV) 8-bit DAC B4 180 FE 254 04 04 Drive 2 (DRV) 8-bit DAC B4 180 FE 254 05 05 Drive 3 (DRV) 8-bit DAC B4 180 FE 254 06 06 Output DC Level (DCL) 4-bit DAC 09 09 0F 15 07 07 OSD Contrast (OSD) 4-bit DAC 09 09 0F 15 08 08 BPCP & OCL Refer to the I2C table 2 04 04 09 09 Miscellaneous Refer to the I2C table 3 1C 28 0A 10 Cut Off Out 1 DC Level (Cut-off) 8-bit DAC B4 180 FF 255 8-bit DAC Hex Dec Hex Dec B4 180 FE 254 0B 11 Cut Off Out 2 DC Level (Cut-off) 8-bit DAC B4 180 FF 255 0C 12 Cut Off Out 3 DC Level (Cut-off) 8-bit DAC B4 180 FF 255 0D 13 Bandwidth Adjustment (BW) 4-bit DAC 07 07 0F 15 For Contrast & Drive adjustment, code 00 (dec) and 255 (dec) are not allowed. For Output DC Level, code 00(dec), 01(dec), 02(dec) are not allowed (Register 06). For Cut Off Output DC Level, output voltage is linear between code 10 and code 235 (Registers 0A, 0B, 0C). BPCP & OCL Register (R8) - I2C Table 2 (see also Figure12) b7 b6 b5 b4 b3 b2 b1 b0 Function 0 0 Internal BPCP triggered by HSYNC 0 1 Internal BPCP triggered by BLK 0 0 Internal BPCP synchronized by the trailing edge 0 1 Internal BPCP synchronized by the leading edge 0 0 0 Internal BPCP Width = 0.33 µs 0 0 1 Internal BPCP Width = 0.66 µs 0 1 0 Internal BPCP Width = 1 µs 0 1 1 Internal BPCP Width = 1.33 µs 1 POR Value x x x Internal BPCP = BPCP input (Pin 23) 0 Normal Operation 1 Reserved (Force BPCP to 1 in test) 0 Normal Operation 1 Reserved (Force OCL to 1 in test) 0 Internal OCL pulse triggered by BLK (pin 24) 1 Internal OCL pulse = Internal BPCP x x x 15/22 TDA9209 Miscellaneous Register (R9) - I2C Table 3 b7 b6 b5 b4 b3 b2 b1 b0 Function 0 Positive Blanking Polarity 1 Negative Blanking Polarity 0 Soft Blanking = OFF 1 Soft Blanking = ON POR Value x x 1 1 1 AC Coupling Mode or DC with Cut-off control x 0 1 DC Coupling Mode 0 x 0 x DC Coupling with Feedback Mode 0 0 Light Grey on OSD Outputs = OFF 0 1 Light Grey on OSD Outputs = ON 0 0 Dark Grey on OSD Outputs = OFF 1 0 Dark Grey on OSD Outputs = ON 0 SOG Clipping = OFF 1 SOG Clipping = ON x x x Bandwidth Adjustment (R13) - I2C Table 4 b7 b6 b5 b4 b3 b2 b1 b0 Function 1 1 1 1 130 MHz 0 1 1 1 100 MHz 0 0 0 0 80 MHz POR Value x 0 0 Normal Operation x 0 1 BW DAC output connected to BLK input (for test) 1 0 BW DAC complementary output connected to BLK input (for test) 0 0 Active Video Output Inhibited 1 0 Active Video Output Validated x Figure 12. BPCP and OCL Generation Source Selection R8b0 HS/BPCP (External) 23 Automatic Polarity HS edge Selection R8b1 24 Edge Pulse Generation OCL (Internal) Polarity Pulse Selection Generation BLK Polarity Selection R9b0 16/22 BPCP Source Selection R8b4 BPCP (Internal) Selection BLK (External) Width Selection R8b2b3 OCL Source Selection R8b7 TDA9209 12 - INTERNAL SCHEMATICS Figure 13. Figure 16. VCC5 VCCA 7 30k (8V) LOGIC PART HIGH IMPEDANCE IN (Pins 1-3-5) GNDA 6 GNDA Figure 14. Figure 17. VCCA V CCA 200kΩ 1k ABL AV 8 2 GNDA GNDA Figure 15. Figure 18. VCCA VCCA GNDL OSD-FBLK-HS-BLK Pins 9-10-11 12-23-24 4 GNDA GNDL GNDA 17/22 2 TDA9209 Figure 19. Figure 22. VCCP 20 OUT Pins 17-19-21 HSYNC 23 (20V) GNDL GNDA Figure 20. GNDA GNDP Figure 23. VCCP 30kΩ SCL 13 4pF GNDA (8V) GNDL GNDP 18 30kΩ SCA 14 GNDA 4pF GNDL GNDA Figure 21. V CCA CO/FB Pins 15-16-22 GNDA 18/22 TDA9209 Figure 24. TDA9209/9207 - TDA9533/9530 Demonstration Board: Silk Screen and Trace (scale 1:1) 19/22 1 2 75R R17 75R R25 1N4148 D8 1N4148 D7 5V 75R R12 A Video Bi n J2 1 3 Gin 2 VSYNC HSYNC 20/22 3 4 5 6 7 8 9 10 11 12 4 A D2 D4 S7 FBLK C22 47uF C21 47uF Jump Jump Jump Jump Jump 47uF C23 12V S6 OSD3 5-8V S5 OSD2 5V S4 S3 33R 33R 33R OSD1 AV R15 R9 R23 100nF 100nF 100nF C7 C13 1N4148 D5 1N4148 5V 1N4148 D3 1N4148 C4 5V R5 R6 C6(1) C9(1) B HSYNC BLANK 5-8V J6 U1 VFly HFly VSYNC 5-8V 5V HSYNC BLANK HEAT G1 110V 12V 100pF C1(1) 13 14 15 16 17 18 19 C17 100nF OSD J7 100pF 100pF C16 20 C8(1) 21 22 1 2 3 4 5 6 7 8 9 10 11 12 100nF C14(1) AV OSD1 OSD2 OSD3 FBLK SDA SCL HSYNC HFly VFly 5V SCL SDA J4 C G1 R28 10 R29 D OUT1 GND1 VDD OUT2 GND2 VCC GND3 OUT3 2K7 R2 D Date: Size A4 Title 150R 6 7 8 9 G2 KR 10nF / 2KV C20 J5 Monday,January17, 2000 DocumentNumber <Doc> Sheet E 1 L3 .33uH CRT4 TDA9207/09+TDA9533 KG G2 R H2 R22 FDH400 of F2(2) F1(2) R27 FDH400 D9(2) 110V L2 .33uH D6(2) 110V 1 Rev F3(2) 150R / 0.5W 150R / 0.5W R11 150R / 0.5W FDH400 D1(2) 110V L1 .33uH 10nF / 400V C19 HEAT R26 120R / 0.5W 10nF / 400V C25 G 5 H1 10 G1 B 11 KB 47uF R21 120R / 0.5W 100nF C11 12V R10 120R / 0.5W C10(1) 1 GND 12 100nF/250V Bout Rout 100nF/250V C12(1) Gout 4.7uF / 150V E transient response optimisation 33R C24 R19(2) 110V GND J3 1 3 5 7 9 11 13 15 SDA SCL C18 110V TDA9530/33 C_OFF1 IN1 C_OFF2 GNDS IN2 IN3 100nF 2: The purpose of all components followed by (2) is to ensure a good protection against overvoltage(arcing protection) U2 2K7 R1 C_OFF3 C15(1) 2 4 6 8 10 GND_CRT 100R 15R/50R R20 R24 100R R18 15R/50R R16 12 14 100nF 15R/50R 100R 1 2 3 4 C3(1) R14 R13 I2C J1 5V 1: All capacitorsfollowed by (1) are decoupling capacitors which must be connected as close as possible to the device 12 11 10 9 8 7 6 5 4 3 2 1 SCL SDA CUT3 CUT2 OUT3 GNDP OUT2 VCCP OUT1 CUT1 2R7 R3 C 23 C5(1) 100pF 24 100R Hs/BPCP R8 100R BLK Jump Jump R7 S1 TDA9207/09 FBLK OSD3 OSD2 OSD1 VDDL/AV VCCA GNDA IN3 S2 5V GNDL IN2 ABL IN1 Supply 12 11 10 9 8 7 6 5 4 3 Notes: 100nF 100nF 2 1 C2(1) 100nF 2R7 2R7 2R7 R4 5V B 1 2 3 4 TDA9209 Figure 25. TDA9209/9207 - TDA9533/9530 Demonstration Board Schematic Rin TDA9209 PACKAGE MECHANICAL DATA 24 Pins — Plastic Dip (Shrink)) E A L A2 A1 E1 Stand-off B B1 e e1 e2 c D E 13 .015 F 24 0,38 Gage Plane 1 12 e3 SDIP24 Millimeters e2 Inches Dimensions Min. Typ. A Max. Min. Typ. 5.08 Max. 0.20 A1 0.51 0.020 A2 3.05 3.30 4.57 0.120 0.130 0.180 B 0.36 0.46 0.56 0.0142 0.0181 0.0220 B1 0.76 1.02 1.14 0.030 0.040 0.045 C 0.23 0.25 0.38 0.0090 0.0098 0.0150 D 22.61 22.86 23.11 0.890 0.90 0.910 E 7.62 8.64 0.30 E1 6.10 6.86 0.240 6.40 0.340 0.252 e 1.778 0.070 e1 7.62 0.30 0.270 e2 10.92 0.430 e3 1.52 0.060 21/22 TDA9209 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this public ation are subject to change witho ut notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics. 2000 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philip s I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philip s. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www .st.com 22/22 3