TEA2164 SWITCH MODE POWER SUPPLY PRIMARY CIRCUIT . . . .. .. POSITIVE AND NEGATIVE OUTPUT CURRENT UP TO 1.2A AND – 1.7A A TWO LEVEL COLLECTOR CURRENT LIMITATION COMPLETE TURN OFF AFTER LONG DURATION OVERLOADS UNDER AND OVER VOLTAGE LOCK-OUT SOFT START BY PROGRESSIVE CURRENT LIMITATION DOUBLE PULSE SUPPRESSION BURST MODE OPERATION UNDER STANDBY CONDITIONS DESCRIPTION In a master slave architecture, the TEA2164 control IC achieves the slave function. Primarily designed for TV receivers and monitors applications, this circuit provides an easy synchronization and smart solution for low power stand by operation. Located at the primary side the TEA2164 Control IC ensures : - the power supply start-up - the power supply control under stand-by conditions - the process of the regulation signals sent by the master circuit located at the secondary side - directbase drive of the bipolar switching transistor - the protection of the transistor and the power supply under abnormal conditions. For more details, refer to application note AN409. POWERDIP16 (Plastic Package) ORDER CODE : TEA2164 PIN CONNECTIONS GROUND 1 16 V CC SUPPLY VOLTAGE I COPY 2 15 OUTPUT STAGE POSITIVE SUPPLY VOLTAGE LONG CAPACITOR OVERLOAD CAPACITO R 3 14 OUTPUT (BASE CURRENT) SUBSTRATE 4 13 SUBSTRATE SUBSTRATE 5 12 SUBSTRATE PULSE INPUT 6 11 IC OSCILLATOR TIMING RESISTOR 7 10 LOW FREQUENCY OSCILLATOR CAPACITOR OSCILLATOR TIMING CAPACITOR 8 9 December 1992 SENSE 2164-01.EPS (max.) FEEDBACK INPUT IS BURST MODE 1/15 TEA2164 2164-02.EPS BLOCK DIAGRAM 2/15 TEA2164 2164-03.EPS Figure 1 : Simplified Application Diagram Symbol VCC Parameter Positive Power Supply V16-V1 Value Unit 18 V V+ Positive Power Supply of the Output Stage V15-V1 18 V V– Negative Power Supply V4, 5, 12, 13-V1 –5 V Total Power Supply V16-V4, 5, 12, 13 or V15-V4, 5, 12, 13 20 V Iout+ Positive Output Current 1.5 A Iout– Negative Output Current VCC - V– V+ - V– Tj Tstag Operating Junction Temperature Storage Temperature Range 2 A 150 °C – 40, + 150 °C Value Unit 11 °C/W 2164-01.TBL ABSOLUTE MAXIMUM RATINGS Symbol Rth(j-c) Parameter Junction Case Thermal Resistance 2164-04.EPS MAXIMUM POWER DISSIPATION 3/15 2164-02.TBL THERMAL DATA TEA2164 RECOMMANDED OPERATING CONDITIONS Positive Power Supply V– VCC – V– Iout+ Iout– Fsw Ro Negative Power Supply (absolute value) (note 1) Total Power Supply Positive Output Current Negative Output Current Switching Frequency Oscillator Resistor Range Co C1 Oscillator Capacitor Range Starting Oscillator Capacitor Range C2 Repetitive Overload Protection Capacitor 1 22 Vin Toper Parameter Min. Typ. 10 Max. 14 Unit V V V A A khz 30 5 18 1.2 1.7 50 150 470 0.1 2700 4.7 0 Input Pulses Amplitude (peak) (derivated pulses - time constant = 1 µs) Operating Ambiant Temperature kΩ pF µF 0.5 1 µF V – 20 70 °C 2164-03.TBL Symbol VCC V CC- TEA2164 4 V CC- IB > 0 13 5 12 14 1 13 TEA2164 4 IB < 0 14 5 IB I 1 capacitive coupling 2164-05.EPS 12 IB < 0 IB < 0 ELECTRICAL OPERATING CHARACTERISTICS Tamb = 25oC, VCC = 10V, VCC- = 0V, potentials referenced to ground (Pin 1) (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit 8 5 2 9 6.2 2.8 9.6 7.4 3.5 V V V 14.8 0.5 15.5 0.8 16.2 1.5 V mA POWER SUPPLY VCC (start) VCC (stop) ∆VCC Vccmax Iccstart Starting Voltage (VCC increasing) Stopping Voltage (VCC decreasing) Hysteresis (VCC start – VCC stop) Overvoltage Lock-out Starting Positive Supply Current CURRENT LIMITATION AND PROTECTION (pin 11) VCM1 Pulse by Pulse Current Limitation Threshold 720 840 970 mV VCM2 Current Monitoring 2nd Threshold 1200 300 1350 500 1500 700 mV mV 700 – 20 2.4 10 900 50 3 20 1100 130 3.6 30 mV mV V µA 50 80 110 µA 19.3 21 22.7 60 70 85 µs % ∆VCM ∆VCM = VCM2 – VCM1 VCM3 VCM3-VCM1 VC2 I3 disch I3 ch. Repetitive Overcurrent Threshold (pin 11) (VCM3-VCM1) Lock-out Voltage on Pin 3 Capacitor C2 Discharge Current (synchronized mode) Capacitor C2 Charge Current OSCILLATOR, MAX DUTY CYCLE, SYNCHRONIZATION To Ton(max) 4/15 Oscillator Initial Accuracy RT = 50 K, CT = 1 nF Maximum Duty Cycle (Tsyn = 1.05 To) 2164-04.TBL REPETITIV E OVERCURRENT PROTECTION TEA2164 ELECTRICAL OPERATING CHARACTERISTICS (continued) Symbol Parameter Min. Typ. Max. Unit OSCILLATOR, MAX DUTY CYCLE, SYNCHRONIZATION (continued) Tsyn TO Synchronization Window 1.0 1.5 I14/I 2 IBON Ic Copy Current Gain Base Current Starting Pulse 1000 300 mA 13 % VERY LOW FREQUENCY OSCILLATOR Burst Duty Cycle I. FIELD OF APPLICATION The TEA2164 control circuit has been designed primarily for discontinuous mode flyback built with a master-slave architecture, whatever the field of application. But due to its capability to synchronize the transistor switching-off with an external signal (line flyback) and due to an adaptedburst-mode operation for a low power stand-by operation, the TEA2164 offers a smart solution for monitors and TV sets applications. Power supply main features : - maximum output power 140W (transistor forced gain : 3.5) Figure 2 : Master Slave Power Supply Architecture 2164-05.TBL OUTPUT STAGE - stand-by mode output power (1W ≤ Psb ≤ 6W ; efficiency > 50%) - operating frequency up to 50kHz - power-switch : bipolar transistor Adapted master-circuit : Monitor application → Standard TV application → Digital TV application → TEA5170 TEA2028B TEA2029C TEA2128 TEA5170 TEA5170 (TEA2028B, TEA2029C and TEA2128 are deflection processors with built-in PWM generator). AUDIO OUTPUT STAGE Muting Control R P1 MAINS INPUT Synchronization SCANNING DEVICE Remote Stand-by P2 C VOLTAGE REGULATOR Remote Stand-by V CC TEA2164 µP TEA5170 V CC INFRA-RED RECEIVER PWM Small signal primary ground Power primary ground Secondary ground (isolated from mains) 2164-06.EPS P1 : Output voltage adjustement in normal mode P2 : Output voltage adjustement in stand-by 5/15 TEA2164 II. GENERAL DESCRIPTION In a master slave architecture, the TEA2164 Control IC, located at the primary side of an off line power supply achieves the slave function ; whereas the master circuit is located at the secondary side. The link between both circuits is realized by a small pulse transformer (Figure 3). 2164-07.EPS Figure 3 : System Description Waveforms 6/15 TEA2164 In the operation of the master-slave architecture, four majors cases must be considered : - normal operating - stand-by mode - power supply start-up - abnormal conditions : off load, short circuit, ... II.1. Normal Operating (master slave mode) In this configuration, the master circuit generates a pulse width modulatedsignal issued from the monitoring of the output voltage which needs the best accuracy (in TV applications : the horizontal deflection stage supplyvoltage). The master circuit power supply can be supplied by another output. The PWM signal are sent towards the primary side through small differentiating transformer. For the TEA2164 positive pulses are transistor switchingon commands ; and negative pulses are transistor switching-off commands (Figure 4). In this configuration, only by synchronizing the master oscillator, the switching transistor may be synchronized with an external signal. II.2. Stand-by Mode In this configuration the master circuit no longer sends PWM signals, the structure is not synchronized ; and the TEA2164 operates in burst mode. The average power consumption at the secondary side may be very low 1W ≤ P ≤ 6W (as it is consumed in TV set during stand by). By action on the maximum duty cycle control, a primary loop maintains a semi-regulation of the output voltages. Voltage on feed-back is applied on Pin 9. Burst period is externally programmed by capacitor C1. II.3. Power Supply Start-up After the mains have been switched-on, the VCC storage capacitor of the TEA2164 is charged through a high value resistor connected to the rectified high voltage. When Vcc reaches VCC start threshold (9V typ), the TEA2164 starts operating in burst mode. Since available output power is low in burst mode the output power consumption must remain low before complete setting-up of output voltage. In TV application it can be achieved by maintaining the TV in stand-by mode during startup (Figure 6). Figure 4 : Master Slave Mode Waveforms Sync. Pulses Synchro. PWM Signal MASTER CIRCUIT Pulse Input Base Current 2164-08.EPS SLAVE CIRCUIT 7/15 TEA2164 2164-09.EPS Figure 5 : Burst Mode Waveforms Figure 6 : Power Supply Start-up Tstart-up = Tch + T1 T1 : necessary time for voltage setting-up d) Abnormal conditions : safety functions Overvoltage Protection When VCC exceeds VCC max, an internal flip-flop stops output conduction signals. The circuit will start again after the capacitor C1 discharge ; it means : after loss of synchronization or after Vcc stop crossing (Figure 7). In flyback converters, this function protects the power supply against output voltage runaway. Under Voltage Lock-out The TEA2164 control circuit stops operating when VCC goes under VCC stop. 8/15 2164-10.EPS Tch ≈ 1s (typ) T1 ≈ 0.3s (typ) Power Limitation, Current Protection, Long Duration Overload Protection - Output power limitation : by a pulse by pulse collector current limitation the TEA2164 limits the maximum output power. VCM1 is the corresponding voltage threshold, its detection is memorized up to the next period. - Current protection (transistor protection) Under particular conditions a hard overload or short circuit may induce a flux runaway in spite of the current limitation (VCM1). The TEA2164 control circuit features a second current protection, VCM2. When this threshold is reached an internal flip-flop memorizes it and TEA2164 output conduction signals are inhibited. The circuit will send base drives again after capacitor C1 discharge (Figure 7). - Long duration overload protection : (Figure 8) An overload is detected when the sense-voltage on Pin 11 reaches VCM3 before a negative pulse has been applied to Pin 6. In this case the capacitor C2 (connected to Pin 3) is charged with I3 ch up to the end of the period and discharged with I3 disch until a next VCM3 detector. By this way in case of long duration overload, the capacitor keeps charging at each period and its voltage encreases gradually. When the voltage on Pin 3 exceeds VC2, the TEA2164 control circuit stops sending base drives and memorizes this event. No restart is allowed as long as Vpin 3 is higher than VC2 and VCC higher than 4.8V. * Remark : - The harder is the overload the faster is the protection - The capacitor keeps charging between two burst after VCM2 detection. 2164-11.EPS Figure 7 : Overvoltages Lock-out 2164-11.EPS Figure 8 : Long Duration Overload Monitoring Circuit 2164-13.EPS Figure 9 : Long Duration Overload Detection 9/15 TEA2164 2164-14.EPS Figure 10 : Repetitive Over-current Protection III. SWITCHING OSCILLATOR AND SYNCHRONIZATION III.1. Switching oscillator When the TEA2164 control circuit operates in burst mode, the switching frequency is fixed by the free frequency oscillator. The period is determined by two external components CO and RO. III.2. Synchronization When the master-circuit starts to send pulses both oscillators are not synchonuous. In order to avoid any erratic conduction of the power transistor, the first synchronization pulse will arrive simultanously with the sawtooth return of the TEA2164 oscillator. To get synchronization the free frequency must be higher than the synchronization frequency. TO < Tsync. < 1.50 TO 2164-15.EPS Figure 11 : Free Frequency Running 2164-16.EPS Figure 12 : Synchronization Pulse Shaper and Synchronization 10/15 TEA2164 (1) NORMAL OPERATION (2) NEGATIVE PULSE MISSING ∆T : synchronization window Transistor turn-off is ensured by VCM1 current limi tation crossing or by an internal tON (max.) limitation set by a 2.5V threshold 2164-17.EPS / 2164-18.EPS Operation after synchronization (3) ERRATIC POSITIVE PULSES (4) Fsynchro < 0.65 Fo P1 and P2 are masked due to the synchronization window Signal S1 triggers burst oscillator capacitor discharge. The TEA2164 restarts in burst-mode 2164-19.EPS Operation after synchronization Cases (2) (3) (4) do not occur in normal operating. IV - MAXIMUM DUTY CYCLE LIMITATION Burst mode : The maximum duty cycle is controlled by the voltage on Pin 9 (Figure 13). Synchronized mode : Normally the maximum duty cycle is set by the master circuit. Oowever the maximum conducting time will never exceed the value given by the comparison of the oscillator wave-form with the 2.5V internal threshold. V - OUTPUT STAGE TEA2164 output stage has been designed to drive switching bipolar transistor. - Each base drive begins with a positive pulse IBON that realizes an efficient transistor turn-on. - After the starting pulse I BON, the base current is proportional to the collector current. The current gain is easily fixed by a resistor R (Figure 14). - A fast and safe transistor turn-off is realized by a fast positive base current cut-off and by applying a negative base drive which draws stored carriers. A typical 0.7s delay prevents from cross-conduction of positive and negative output stages. Remark : In order to reduce power dissipation on the positive output stage with the low gain transistors, for high base currents the positive output stage operates in saturated mode (Figure 15). This can be achieved by using a resistor between VCC and V+. 11/15 TEA2164 2164-20.EPS Figure 13 : Maximum Duty Cycle Limitation Figure 14 : Output Stage Architecture and Base Drive IB I BON V 16 t 15 CURRENT MIRROR I Cmax IB 14 IC Virtual Ground t RS V 2 I COPY 4-5-12-13 IC RB IB ≅ GF RS = IC RB IC GF = VI - MONITOR APPLICATIONS In most of monitor applications, the power supply must start-up under full load conditions and the stand -by mode is no longer useful. IB = V CM1 I Cmax 1000 x R S 2164-21.EPS V CC The energy of the starting burst must be high enough to ensure start-up, then the capacitor C1 must be higher in these applications than on TV application (typ. : 1µF). 2164-22.EPS Figure 15 : Power Supply Start-up and Normal Operation 12/15 13 12 10 5 4 470kΩ 300kΩ 1nF 3 2 2164-23.EPS 2 µH 10Ω 220µ F 100kΩ (2W) 1N4444 14 16 100Ω 6 15 2 x 47µF (385V) 6.8Ω 1 330 Ω 390 Ω 11 TEA2164 4.7µF 9 7 8 12kΩ Primary Ground (connected to mains) Secondary ground(isolated from mains) 2.2µF 1.2nF 110kΩ 2.2Ω 2.2Ω 0.27Ω 100Ω 47µF 3 x 1N404 BA157 BA157 220Ω BU508A 2 1 7 9 6 470Ω 10µ F BA159 2.2nF 4.7µF V CC 470µF 1000µF 100µF V CC 1N4148 24 20 7 22 19 18 17 15 16 100nF VIDEO INPUT 27 23 VCR Switch 13V 2N1711 MUTE OUT & 50/60Hz IDENTIFICATION 8.2k Ω AGC PULSE 15kΩ 1.5nF 15nF 330Ω 5.6kΩ 1.8kΩ 220Ω 3.9kΩ 5.6kΩ 503 kHz 150pF +25V 470kΩ 10kΩ 680Ω 27Ω 33kΩ +135V / 0.6A HorizontalPhase Adjust BY218 BY218 BY218 220Ω VCC 22 21 19 20 13 22nF 100nF 3 OREGA G.4173.04 3.3nF 220nF 4 x 1N4007 26 150kΩ 14 22nF 220 µF V CC 8 25 1.5kΩ 11 28 21 10kΩ 5 3 1 2 6 4 10 100kΩ 220pF SUPER SANDCASTLE LINE OUTPUT FLYBACK 12 9 1k Ω 220pF SMPS Output Voltage Adjust TEA2029C 13 3.32kΩ (1%) 100nF 1kΩ 1k Ω 220VAC MAINS INPUT 4.7nF 820 Ω 220Ω 1kΩ 100nF 1nF 1kΩ FramePhase Adjust 220 Ω 6.8kΩ 33 Ω ESM 740 82kΩ 220Ω BA157 EHT TRANSFORMER 3.3kΩ 3.3kΩ 47nF LINE YOKE E/W CORRECTION 2.2kΩ 220kΩ 470nF 2.7MΩ 820 Ω 1kΩ 390Ω 6.8kΩ FUSE 1.6A 200V +24V 4.7 Ω Frame Amplitude Adjust FRAME YOKE 120mH 60Ω 0.47µF 500µH LINE FLYBACK +24V +200V TEA2164 COMPLETE APPLICATION DIAGRAM (SMPS + DEFLECTION) (with stand-by function) 13/15 14/15 6 8 7 2164-24.EPS f : 32kHz 560 pF 2% 4 9 10 P OUT : 120W 100kΩ 1% 100nF 1nF V IN = 220 V AC 12 1nF 1 16V 330 Ω 2 15 18Ω 2.2µF 1N4148 14 16 120kΩ (2W) 5.6Ω (1W) 4 x 1N4007 150µ F (385V) 330 Ω 11 13 68kΩ 4.7µF 3 TEA2164 5 P2 22kΩ 20% 0.24Ω (1W) 47µF BZX85C-3V0 220µF 25V 4.7Ω (2W) BA157 100Ω BA159 SGSF344 7 9 6 3 21 22 17 14 19 20 13 Pulse Transformer 2.7nF 1kV 470Ω (8W) G4453-02 270Ω BY218-100 BY218-100 PLR811 BY218-600 10µF 16V 1000µF (40V) 1000µF (25V) 470µF (25V) 100µF (250V) 25V 3 2 6 100kΩ 7 8 2.2kΩ 6.8kΩ 150pF 47nF Stand-by Control 1N4148 1 5 75kΩ TEA5170 4 560 pF 560 pF BC550C 10kΩ 7.5V 100kΩ P1 100kΩ Sync. Input 135V TEA2164 STAND-ALONE 32kHz POWER SUPPLY ELECTRICAL DIAGRAM TEA2164 I b1 L a1 PACKAGE MECHANICAL DATA 16 PINS - PLASTIC POWERDIP b B e E Z e3 D 9 1 8 a1 B b b1 D E e e3 F i L Z Min. 0.51 0.85 Millimeters Typ. Max. 1.4 Min. 0.020 0.033 0.5 0.38 Inches Typ. Max. 0.055 0.020 0.5 20 0.015 8.8 2.54 17.78 0.020 0.787 0.346 0.100 0.700 7.1 5.1 3.3 DIP16PW.TBL Dimensions PMDIP16W.EPS F 16 0.280 0.201 0.130 1.27 0.050 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 15/15