FODM8071 3.3V/5V Logic Gate Output Optocoupler with High Noise Immunity Features Description ■ High noise immunity characterized by common mode The FODM8071 is a 3.3V/5V high-speed logic gate output Optocoupler, which supports isolated communications allowing digital signals to communicate between systems without conducting ground loops or hazardous voltages. It utilizes Fairchild’s patented coplanar packaging technology, Optoplanar®, and optimized IC design to achieve high noise immunity, characterized by high common mode rejection specifications. rejection – 20kV/µs minimum common mode rejection ■ High speed – 20Mbit/sec date rate (NRZ) – 55ns max. propagation delay – 20ns max. pulse width distortion – 30ns max. propagation delay skew 3.3V and 5V CMOS compatibility ■ ■ Speciﬁcations guaranteed over 3V to 5.5V supply voltage and -40°C to +110°C temperature range ■ Safety and regulatory approvals – UL1577, 3750 VACRMS for 1 min. – IEC60747-5-2 (pending) Applications This high-speed logic gate output optocoupler, housed in a compact 5-Pin Mini-Flat package, consists of a highspeed AlGaAs LED at the input coupled to a CMOS detector IC at the output. The detector IC comprises an integrated photodiode, a high-speed transimpedance amplifier and a voltage comparator with an output driver. The CMOS technology coupled with a high efficiency LED achieves low power consumption as well as very high speed (55ns propagation delay, 20ns pulse width distortion). ■ Microprocessor system interface ■ ■ ■ ■ – SPI, I2C Industrial fieldbus communications – DeviceNet, CAN, RS485 Programmable logic control Isolated data acquisition system Voltage level translator Related Resources ■ www.fairchildsemi.com/products/opto/ ■ www.fairchildsemi.com/pf/FO/FOD8001.html ■ www.fairchildsemi.com/pf/FO/FOD0721.html Functional Schematic Truth Table ANODE 1 6 VDD 5 VO CATHODE 3 ©2008 Fairchild Semiconductor Corporation FODM8071 Rev. 1.0.6 LED Output Off High On Low 4 GND www.fairchildsemi.com FODM8071 — 3.3V/5V Logic Gate Output Optocoupler with High Noise Immunity December 2009 Number Name 1 ANODE 3 CATHODE 4 GND Function Description Anode Cathode Output Ground 5 VO Output Voltage 6 VDD Output Supply Voltage Safety and Insulation Ratings for Mini-Flat Package (SO5 Pin) As per IEC60747-5-2 (Pending Certification). This optocoupler is suitable for “safe electrical insulation” only within the safety limit data. Compliance with the safety ratings shall be ensured by means of protective circuits. Symbol Parameter Min. Typ. Max. Unit Installation Classiﬁcations per DIN VDE 0110/1.89 Table 1 For rated main voltage < 150Vrms I-IV For rated main voltage < 300Vrms I-III Climatic Classiﬁcation 40/110/21 Pollution Degree (DIN VDE 0110/1.89) 2 CTI Comparative Tracking Index 175 VPR Input to Output Test Voltage, Method b, VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC 1060 V VPR Input to Output Test Voltage, Method a, VIORM x 1.5 = VPR, Type and Sample Test with tm = 60 sec, Partial Discharge < 5 pC 848 V VIORM Max Working Insulation Voltage 565 Vpeak VIOTM Highest Allowable Over Voltage 4000 Vpeak External Creepage 5.0 mm External Clearance 5.0 mm Insulation Thickness 0.5 mm Safety Limit Values, Maximum Values allowed in the event of a failure, Case Temperature 150 °C Insulation Resistance at TSTG,VIO = 500V 109 Ω TCase RIO ©2008 Fairchild Semiconductor Corporation FODM8071 Rev. 1.0.6 www.fairchildsemi.com 2 FODM8071 — 3.3V/5V Logic Gate Output Optocoupler with High Noise Immunity Pin Definitions Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. . Symbol Parameter Value Units TSTG Storage Temperature -40 to +125 ºC TOPR Operating Temperature -40 to +110 ºC Junction Temperature -40 to +125 ºC 260 for 10sec ºC TJ TSOL Lead Solder Temperature (Refer to Reﬂow Temperature Proﬁle) IF Forward Current 20 mA VR Reverse Voltage 5 V VDD Supply Voltage 0 to 6.0 V VO Output Voltage -0.5 to VDD+0.5 V IO Average Output Current 10 mA 40 mW 70 mW PDI PDO Input Power Dissipation(1)(3) Output Power Dissipation(2)(3) Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Min. Max. Unit Ambient Operating Temperature -40 +110 ºC VDD Supply Voltages(4) 3.0 5.5 V VFL Logic Low Input Voltage 0 0.8 V IFH Logic High Input Current 5 16 mA IOL Logic Low Output Current 0 7 mA TA Parameter Isolation Characteristics (Apply over all recommended conditions, typical value is measured at TA = 25ºC) Symbol Parameter Conditions VISO Input-Output Isolation Voltage freq = 60Hz, t = 1.0min, II-O ≤ 10µA(5)(6) RISO Isolation Resistance CISO Isolation Capacitance VI-O = 500V(5) VI-O = 0V, freq = 1.0MHz(5) Min. Typ. Max. Units 3750 VacRMS 1011 Ω 0.2 pF Notes: 1. Derate linearly from 95˚C at a rate of -1.4mW/˚C 2. Derate linearly from 100˚C at a rate of -3.47mW/˚C. 3. Functional operation under these conditions is not implied. Permanent damage may occur if the device is subjected to conditions outside these ratings. 4. 0.1µF bypass capacitor must be connected between 4 and 6. 5. Device is considered a two terminal device: Pins 1, and 3 are shorted together and Pins 4, 5, and 6 are shorted together. 6. 3,750 VACRMS for 1 minute duration is equivalent to 4,500 VACRMS for 1 second duration. ©2008 Fairchild Semiconductor Corporation FODM8071 Rev. 1.0.6 www.fairchildsemi.com 3 FODM8071 — 3.3V/5V Logic Gate Output Optocoupler with High Noise Immunity Absolute Maximum Ratings (TA = 25ºC unless otherwise speciﬁed) Symbol Parameter Test Conditions Min. Typ. Max. Units 1.05 1.35 1.8 V 5 15 INPUT CHARACTERISTICS VF Forward Voltage IF = 10mA, Fig. 1 BVR Input Reverse Breakdown Voltage IR = 10µA IFHL Threshold Input Current Fig. 2 2.8 5 mA VDD = 3.3V, IF = 10mA, Fig. 3, 5 3.3 4.8 mA VDD = 5.0V, IF = 10mA, Fig. 3, 6 4.0 5.0 mA V OUTPUT CHARACTERISTICS IDDL IDDH VOH VOL Logic Low Output Supply Current Logic High Output Supply Current VDD = 3.3V, IF = 0mA, Fig. 4 3.3 4.8 mA VDD = 5.0V, IF = 0mA, Fig. 4 4.0 5.0 mA Logic High Output Voltage VDD = 3.3V, IO = -20µA, IF = 0mA VDD – 0.1V 3.3 V VDD = 3.3V, IO = -4mA, IF = 0mA VDD – 0.5V 3.1 V VDD = 5.0V, IO = -20µA, IF = 0mA VDD – 0.1V 5.0 V VDD = 5.0V, IO = -4mA, IF = 0mA VDD – 0.5V Logic Low Output Voltage ©2008 Fairchild Semiconductor Corporation FODM8071 Rev. 1.0.6 4.9 V IO = 20µA, IF = 10mA 0.0027 0.01 V IO = 4mA, IF = 10mA 0.27 0.8 V www.fairchildsemi.com 4 FODM8071 — 3.3V/5V Logic Gate Output Optocoupler with High Noise Immunity Electrical Characteristics (Apply over all recommended conditions) (TA = -40ºC to +110ºC, 3.0V ≤ VDD ≤ 5.5V), unless otherwise specified. Typical value is measured at TA = 25ºC and VDD = 3.3V. (TA = -40ºC to +110ºC, 3.0V ≤ VDD ≤ 5.5V, IF = 5mA), unless otherwise specified. Typical value is measured at TA = 25ºC and VDD = 3.3V Symbol Parameter Test Conditions Min. Typ. Date Rate(7) Max. Units 20 Mbps tPW Pulse Width tPHL Propagation Delay Time to Logic Low Output CL = 15pF, Fig. 7, 8, 12 50 31 55 ns ns tPLH Propagation Delay Time to Logic High Output CL = 15pF, Fig. 7, 8, 12 25 55 ns PWD Pulse Width Distortion, | tPHL - tPLH| CL = 15pF, Fig. 9, 10 5.5 20 ns tPSK Propagation Delay Skew CL = 15pF(8) 30 ns tR Output Rise Time (10% to 90%) Fig. 11, 12 5.8 ns tF Output Fall Time (90% to 10%) Fig. 11, 12 5.3 ns | CMH | Common Mode Transient Immunity at Output High IF = 0mA, VO > 0.8VDD, VCM = 1000V, TA = 25ºC, Fig. 13(9) 20 40 kV/µs | CML | Common Mode Transient Immunity at Output Low IF = 5mA, VO < 0.8V, VCM = 1000V, TA = 25ºC, Fig. 13(9) 20 40 kV/µs CPDO Output Dynamic Power Dissipation Capacitance(10) 4 pF Notes: 7. Data rate is based on 10MHz, 50% NRZ pattern with a 50nsec minimum bit time. 8. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between any two units from the same manufacturing date code that are operated at same case temperature (±5°C), at same operating conditions, with equal loads (RL = 350Ω and CL = 15pF), and with an input rise time less than 5ns. 9. Common mode transient immunity at output high is the maximum tolerable positive dVcm/dt on the leading edge of the common mode impulse signal, Vcm, to assure that the output will remain high. Common mode transient immunity at output low is the maximum tolerable negative dVcm/dt on the trailing edge of the common pulse signal, Vcm, to assure that the output will remain low. 10.Unloaded dynamic power dissipation is calculated as follows: CPD x VDD x f + IDD + VPD where f is switched time in MHz. ©2008 Fairchild Semiconductor Corporation FODM8071 Rev. 1.0.6 www.fairchildsemi.com 5 FODM8071 — 3.3V/5V Logic Gate Output Optocoupler with High Noise Immunity Switching Characteristics (Apply over all recommended conditions) Fig. 2 Input Threshold Current vs. Ambient Temperature Fig. 1 Input Forward Current vs. Forward Voltage 4.0 IFHL – INPUT THRESHOLD CURRENT (mA) IF – INPUT FORWARD CURRENT (mA) 100 10 1 0.1 TA = 110°C 0.01 0.8 0.9 TA = 25°C TA = -40°C 1.0 1.1 1.2 1.3 1.4 VF – FORWARD VOLTAGE (V) 1.5 3.5 VDD = 5.0V 3.0 VDD = 3.3V 2.5 2.0 -40 1.6 IDDH – LOGIC HIGH OUTPUT SUPPLY CURRENT (mA) IDDL – LOGIC LOW OUTPUT SUPPLY CURRENT (mA) IF = 10mA 4.5 V DD = 5.0V 4.0 VDD = 3.3V 3.5 3.0 2.5 2.0 0 20 40 60 80 TA – AMBIENT TEMPERATURE (°C) 100 IDDL – DYNAMIC LOGIC LOW OUTPUT SUPPLY CURRENT (mA) IDDL – DYNAMIC LOGIC LOW OUTPUT SUPPLY CURRENT (mA) 80 100 IF = 0mA 4.5 V DD = 5.0V 4.0 V 3.5 DD = 3.3V 3.0 2.5 2.0 -40 5.5 4.0 TA = 25°C 3.5 TA = 110°C 60 -20 0 20 40 60 80 TA – AMBIENT TEMPERATURE (°C) 100 Fig. 6 Dynamic Logic Low Output Supply Current vs. Input Frequency (VDD = 5.0V) Frequency = 10MHz Duty Cycle = 50% IF = 10mA VDD = 3.3V 4.5 40 5.0 Fig. 5 Dynamic Logic Low Output Supply Current vs. Input Frequency (VDD = 3.3V) 5.0 20 Fig 4. Logic High Output Supply Current vs. Ambient Temperature 5.0 -20 0 TA – AMBIENT TEMPERATURE (°C) Fig 3. Logic Low Output Supply Current vs. Ambient Temperature -40 -20 TA = -40°C 3.0 2.5 Frequency = 10MHz Duty Cycle = 50% IF = 10mA VDD = 5.0V 5.0 T = 25°C A 4.5 TA = -40°C 4.0 TA = 110°C 3.5 3.0 0 2000 4000 6000 8000 f – INPUT FREQUENCY (kHz) ©2008 Fairchild Semiconductor Corporation FODM8071 Rev. 1.0.6 0 10000 2000 4000 6000 8000 10000 f – INPUT FREQUENCY (kHz) www.fairchildsemi.com 6 FODM8071 — 3.3V/5V Logic Gate Output Optocoupler with High Noise Immunity Typical Performance Curves (Continued) Fig 7. Propagation Delay vs. Ambient Temperature 50 tP – PROPAGATION DELAY (ns) Frequency = 10MHz Duty Cycle = 50% IF = 5mA 45 tP – PROPAGATION DELAY (ns) Fig 8. Propagation Delay vs. Pulse Input Current 40 40 35 tPHL 30 tPHL tPLH 25 tPLH 20 Frequency = 10MHz Duty Cycle = 50% TA = 25°C 35 tPLH 30 tPLH 25 tPHL 20 tPHL 15 15 VDD = 3.3V V = 5.0V DD VDD = 3.3V VDD = 5.0V 10 10 -40 -20 0 20 40 60 80 4 100 6 TA – AMBIENT TEMPERATURE (°C) Frequency = 10MHz Duty Cycle = 50% IF = 5mA 15 10 VDD = 3.3V 5 VDD = 5.0V 0 -5 -40 14 16 Fig 10. Pulse Width Distortion vs Pulse Input Current (| tPHL – tPLH |) – PULSE WIDTH DISTORTION (ns) (| tPHL – tPLH |) – PULSE WIDTH DISTORTION (ns) Fig 9. Pulse Width Distortion vs. Ambient Temperature 20 8 10 12 IF – PULSE INPUT CURRENT (mA) 15 Frequency = 10MHz Duty Cycle = 50% TA = 25°C 12 9 VDD = 3.3V 6 3 VDD = 5.0V 0 -20 0 20 40 60 80 TA – AMBIENT TEMPERATURE (°C) 100 4 6 8 10 12 14 IF – PULSE INPUT CURRENT (mA) 16 Fig 11. Rise and Fall Time vs. Ambient Temperature 10 tR, tF – RISE, FALL TIME (ns) Frequency = 10MHz Duty Cycle = 50% I = 5mA 9 F 8 7 tR 6 tF tR 5 tF 4 3 -40 -20 0 VDD = 3.3V VDD = 5.0V 20 40 60 80 100 TA – AMBIENT TEMPERATURE (°C) ©2008 Fairchild Semiconductor Corporation FODM8071 Rev. 1.0.6 www.fairchildsemi.com 7 FODM8071 — 3.3V/5V Logic Gate Output Optocoupler with High Noise Immunity Typical Performance Curves (Continued) FODM8071 — 3.3V/5V Logic Gate Output Optocoupler with High Noise Immunity Schematics VCC Pulse Gen. tf = tr = 5ns ZO = 50Ω 0.1µF Input Monitoring Node VO Monitoring Node CL = 15pF RIN IF = 5mA 50% Input tPHL tPLH tf Output tr 90% 90% 50% 10% VOL 10% Figure 12. Test Circuit for Propagation Delay Time, Rise Time and Fall Time IF VDD 0.1µF Bypass A Output (Vo) B VFF VCM Pulse Gen VCM GND VOH Switching Pos. (A), IF = 0 CMH 0.8 x VDD 0.8V VOL Switching Pos. (B), IF = 5mA CML Figure 13. Test Circuit for Instantaneous Common Mode Rejection Voltage ©2008 Fairchild Semiconductor Corporation FODM8071 Rev. 1.0.6 www.fairchildsemi.com 8 FODM8071 — 3.3V/5V Logic Gate Output Optocoupler with High Noise Immunity Package Dimensions Notes: 1. No standard applies to this package. 2. All dimensions are in millimeters. 3. Dimensions are exclusive of burrs, mold flash, and tie bar extrusion. 4. Drawings filesname and revision: MKT-MFP05A. Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2008 Fairchild Semiconductor Corporation FODM8071 Rev. 1.0.6 www.fairchildsemi.com 9 8.0 ± 0.1 3.5 ± 0.2 2 ± 0.05 0.3 MAX 4.0 ± 0.1 Ø1.5 MIN 1.75 ± 0.10 5.5 ± 0.05 12.0 ± 0.3 8.3 ± 0.1 0.1 MAX 5.2 ± 0.2 6.4 ± 0.2 Ø1.5 + 0.1/-0 User Direction of Feed Note: All dimensions are in millimeters. ©2008 Fairchild Semiconductor Corporation FODM8071 Rev. 1.0.6 www.fairchildsemi.com 10 FODM8071 — 3.3V/5V Logic Gate Output Optocoupler with High Noise Immunity Carrier Tape Specification Option Order Entry Identifier No Suffix FODM8071 R2 FODM8071R2 Description Mini-Flat 5-pin, shipped in tubes (100 units per tube) Mini-Flat 5-pin, tape and reel (2,500 units per reel) All packages are lead free per JEDEC: J-STD-020B standard. Marking Information 1 V 3 M8071 2 X YY M 6 4 5 Definitions 1 Fairchild logo 2 Device number 3 IEC60747-5-2 (VDE marking) 4 One digit year code, e.g., ‘9’ 5 Two digit work week ranging from ‘01’ to ‘53’ 6 Assembly package code ©2008 Fairchild Semiconductor Corporation FODM8071 Rev. 1.0.6 www.fairchildsemi.com 11 FODM8071 — 3.3V/5V Logic Gate Output Optocoupler with High Noise Immunity Ordering Information FODM8071 — 3.3V/5V Logic Gate Output Optocoupler with High Noise Immunity Reflow Profile Temperature (°C) TP 260 240 TL 220 200 180 160 140 120 100 80 60 40 20 0 Max. Ramp-up Rate = 3°C/S Max. Ramp-down Rate = 6°C/S tP Tsmax tL Preheat Area Tsmin ts 120 240 360 Time 25°C to Peak Time (seconds) Profile Feature Pb-Free Assembly Profile Temperature Min. (Tsmin) 150°C Temperature Max. (Tsmax) 200°C Time (tS) from (Tsmin to Tsmax) 60–120 seconds Ramp-up Rate (tL to tP) 3°C/second max. Liquidous Temperature (TL) 217°C Time (tL) Maintained Above (TL) 60–150 seconds Peak Body Package Temperature 260°C +0°C / –5°C Time (tP) within 5°C of 260°C 30 seconds Ramp-down Rate (TP to TL) 6°C/second max. Time 25°C to Peak Temperature ©2008 Fairchild Semiconductor Corporation FODM8071 Rev. 1.0.6 8 minutes max. www.fairchildsemi.com 12 AccuPower™ Auto-SPM™ Build it Now™ CorePLUS™ CorePOWER™ CROSSVOLT™ CTL™ Current Transfer Logic™ DEUXPEED® Dual Cool™ EcoSPARK® EfficientMax™ EZSWITCH™* ™* ® ® Fairchild Fairchild Semiconductor® FACT Quiet Series™ FACT® ® FAST FastvCore™ FETBench™ FlashWriter®* FPS™ F-PFS™ ® FRFET SM Global Power Resource Green FPS™ Green FPS™ e-Series™ Gmax™ GTO™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ MotionMax™ Motion-SPM™ OPTOLOGIC® ® OPTOPLANAR ® PDP SPM™ Power-SPM™ PowerTrench® PowerXS™ Programmable Active Droop™ QFET® QS™ Quiet Series™ RapidConfigure™ ™ Saving our world, 1mW/W/kW at a time™ SignalWise™ SmartMax™ SMART START™ SPM® STEALTH™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SupreMOS™ SyncFET™ Sync-Lock™ ® * ® The Power Franchise TinyBoost™ TinyBuck™ TinyCalc™ TinyLogic® TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™ TriFault Detect™ TRUECURRENT™* µSerDes™ ® UHC Ultra FRFET™ UniFET™ VCX™ VisualMax™ XS™ * Trademarks of System General Corporation, used under license by Fairchild Semiconductor. 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Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Advance Information Formative / In Design Preliminary First Production No Identification Needed Full Production Obsolete Not In Production Definition Datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I45 ©2008 Fairchild Semiconductor Corporation FODM8071 Rev. 1.0.6 www.fairchildsemi.com 13 FODM8071 — 3.3V/5V Logic Gate Output Optocoupler with High Noise Immunity TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.