TS5070 TS5071 PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION COMPLETE CODEC AND FILTER SYSTEM INCLUDING : – TRANSMIT AND RECEIVE PCM CHANNEL FILTERS – µ-LAW OR A-LAW COMPANDING CODER AND DECODER – RECEIVE POWER AMPLIFIER DRIVES 300 Ω – 4.096 MHz SERIAL PCM DATA (max) PROGRAMMABLE FUNCTIONS : – TRANSMIT GAIN : 25.4 dB RANGE, 0.1 dB STEPS – RECEIVE GAIN : 25.4 dB RANGE, 0.1 dB STEPS – HYBRID BALANCE CANCELLATION FILTER – TIME-SLOT ASSIGNMENT: UP TO 64 SLOTS/FRAME – 2 PORT ASSIGNMENT (TS5070) – 6 INTERFACE LATCHES (TS5070) – A OR µ-LAW – ANALOG LOOPBACK – DIGITAL LOOPBACK DIRECT INTERFACE TO SOLID-STATE SLICs SIMPLIFIES TRANSFORMER SLIC, SINGLE WINDING SECONDARY STANDARD SERIAL CONTROL INTERFACE 80 mW OPERATING POWER (typ) 1.5mW STANDBY POWER (typ) MEETS OR EXCEEDS ALL CCITT AND LSSGR SPECIFICATIONS TTL AND CMOS COMPATIBLE DIGITAL INTERFACES DESCRIPTION The TS5070series are the second generationcombined PCM CODEC and Filter devices optimized for digital switching applications on subscriber and trunk line cards. Using advanced switched capacitor techniques the TS5070 and TS5071 combine transmit bandpass and receive lowpass channel filters with a companding PCM encoder and decoder. The devices are A-law and µ-law selectable and employ a conventional serial PCM interface capable of being clocked up to 4.096 MHz. A number of programmable functions may be controlled via a serial control port. December 1997 DIP20 (Plastic) ORDERING NUMBER:TS5071N PLCC28 ORDERING NUMBERS: TS5070FN TS5070FNTR Channel gains are programmable over a 25.4 dB range in each direction, and a programmable filter is included to enable Hybrid Balancing to be adjusted to suit a wide range of loop impedance conditions. Both transformer and active SLIC interface circuits with real or complex termination impedances can be balanced by this filter, with cancellation in excess of 30 dB being readily achievable when measured across the passbandagainst standardtest termination networks. To enable COMBO IIG to interface to the SLIC control leads, a number of programmable latches are included ; each may be configured as either an input or an output. The TS5070 provides 6 latches and the TS5071 5 latches. 1/32 TS5070 - TS5071 TS5070 PIN FUNCTIONALITY (PLCC28) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name GND VFR0 VSS NC NC IL3 IL2 FSR D R1 D R0 CO CI CCLK CS MR BCLK MCLK DX0 DX1 TSX0 TSX1 FSX IL5 IL4 IL1 IL0 VCC VFXI Function Ground Input (+0V) Analog Output Supply Input (-5V) Not Connected Not Connected Digital Input or Output defined by LDR register content Digital Input or Output defined by LDR register content Digital input Digital input sampled by BCLK falling edge Digital input sampled by BCLK falling edge Digital output (shifted out on CCLK rising edge) Digital input (sampled on CCLK falling edge) Digital input (clock) Digital input (chip select for CI/CO) Digital Input Digital input (clock) Digital input Digital output clocked by BCLK rising edge Digital output clocked by BCLK rising edge Open drain output (pulled low by active DX0 time slot) Open drain output (pulled low by active DX1 time slot) Digital input Digital input or output defined by LDR register content Digital input or output defined by LDR register content Digital input or output defined by LDR register content Digital input or output defined by LDR register content Supply input (+5V) Analog input TS5070 FUNCTIONAL DIAGRAM VCC=+5V VSS=-5V VFXI ENCODER TX GAIN HYBRID BALANCE FILTER HYBAL 1 TX TIME SLOT AZ TX REGISTER DX0 DX1 TSX0 Vref TIME-SLOT ASSIGNMENT TSX1 FSX BCLK CTL REG. HYBAL 2 FSR HYBAL 3 VFRO GND RX REGISTER TS5070/71 DR0 DR1 RX TIME SLOT MCLK DECODER MR IL5 RX GAIN IL4 IL3 IL2 INTERFACE LATCHES LATCH DIR LATCH CONT. CS CONTROL INTERFACE IL1 CO CI IL0 D94TL135 2/32 CCLK TS5070 - TS5071 BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VCC VCC to GND 7 V VSS VSS to GND –7 V Voltage at VFXI VCC + 0.5 to VSS – 0.5 V VIN Voltage at Any Digital Input VCC + 0.5 to GND – 0.5 V Current at VFRO ± 100 mA IO Current at Any Digital Output ± 50 mA Tstg Storage Temperature Range – 65, + 150 °C Tlead Lead Temperature Range (soldering, 10 seconds) 300 °C 3/32 TS5070 - TS5071 PIN CONNECTIONS DIP20 TS5071N PLCC28 TS5070FN POWER SUPPLY, CLOCK Name Pin Type TS5070 FN TS5071 N VCC S 27 19 VSS S 3 3 GND S 1 BCLK I MCLK I 4/32 Function Description +5V±5% 1 Positive Power Supply Negative Power Supply Ground 16 12 Bit Clock Bit clock input used to shift PCM data into and out of the DR and DX pins. BCLK may vary from 64 kHz to 4.096 MHz in 8 kHz increments, and must be synchronous with MCLK (TS5071 only). 17 12 Master Clock Master clock input used by the switched capacitor filters and the encoder and decoder sequencing logic. Must be 512 kHz, 1. 536/1. 544 MHz, 2.048 MHz or 4.096 MHz and synchronous with BCLK. BCLK and MCLK are wired together in the TS5071. – 5 V± 5% All analog and digital signals are referenced to this pin. TS5070 - TS5071 TRANSMIT SECTION Name Pin Type TS5070 FN TS5071 N FSX I 22 15 Transmit Frame Sync. Normally a pulse or squarewave waveform with an 8 kHz repetition rate is applied to this input to define the start of the transmit time-slot assigned to this device (non-delayed data mode) or the start of the transmit frame (delayed data mode using the internal time-slot assignment counter). VFXI I 28 20 Transmit Analog This is a high–impedance input. Voice frequency signals present on this input are encoded as an A–law or µ–law PCM bit stream and shifted out on the selected DX pin. D X0 D X1 0 0 18 19 13 – Transmit Data DX1 is available on the TS5070 only, DX0 is available on all devices. These transmit data TRI–STATE outputs remain in the high impedance state except during the assigned transmit time–slot on the assigned port, during which the transmit PCM data byte is shifted out on the rising edges of BCLK. TSX0 TSX1 0 0 20 21 14 – Transmit Time–slot TSX1 is available on the TS5070 only. TSX0 is available on all devices. Normally these opendrain outputs are floating in a high impedance state except when a time–slot is active on one of the D X outputs, when the apppropriate TSX output pulls low to enable a backplane line–driver. Should be strapped to ground (GND) when not used. Function Description RECEIVE SECTION Name Pin Type TS5070 FN TS5071 N FSR I 8 VFR0 0 DR0 DR1 I I Function Description 6 Receive Frame Sync. Normally a pulse or squarewave waveform with an 8 kHz repetition rate is applied to this input to define the start of the receive time–slot assigned to this device (non-delayed frame mode) or the start of the receive frame (delayed frame mode using the internal time-slot assignment counter. 2 2 Receive Analog The receive analog power amplifier output, capable of driving load impedances as low as 300 Ω (depending on the peak overload level required). PCM data received on the assigned DR pin is decoded and appears at this output as voice frequency signals. 10 9 7 – Receive Data DR1 is available on the TS5070 only, DR0 is available on all devices. These receive data input(s) are inactive except during the assigned receive time–slot of the assigned port when the receive PCM data is shifted in on the falling edges of BCLK. 5/32 TS5070 - TS5071 INTERFACE, CONTROL, RESET Name Pin Type TS5070 FN TS5071 N IL5 IL4 IL3 IL2 IL1 IL0 I/O I/O I/O I/O I/O I/O 23 24 6 7 25 26 – 16 4 5 17 18 Interface Latches IL5 through IL0 are available on the TS5070, IL4 through IL0 are available on the TS5071. Each interface Latch I/O pin may be individually programmed as an input or an output determined by the state of the corresponding bit in the Latch Direction Register (LDR) . For pins configured as inputs, the logic state sensed on each input is latched into the interface Latch Register (ILR) whenever control data is written to COMBO IIG, while CS is low, and the information is shifted out on the CO (or CI/O) pin. When configured as outputs, control data written into the ILR appears at the corresponding IL pins. CCLK I 13 9 Control Clock This clock shifts serial control information into or out of CI or CO (or CI/O) when the CS input is low depending on the current instruction. CCLK may be asynchronous with the other system clocks. CI/O I/O – 8 Control Data Input/output This is Control Data I/O pin wich is provided on the TS5071. Serial control information is shifted into or out of COMBO IIG on this pin when CS is low. The direction of the data is determined by the current instruction as defined in Table 1. CI I 12 – These are separate controls, availables only on the TS5070. They can be wired together if required. CO O 11 – Control Data Input Control Data Output CS I 14 10 Chip Select When this pins is low, control information can be written to or read from the COMBO IIG via the CI and CO pins (or CI/O). MR I 15 11 Master Reset This logic input must be pulled low for normal operation of COMBO IIG. When pulled momentarily high, all programmable registers in the device are reset to the states specified under ”Power–on Initialization”. Function FUNCTIONAL DESCRIPTION POWER-ON INITIALIZATION When power is first applied, power-on reset circuitry initializes COMBO IIG and puts it into the power-down state. The gain control registers for the transmit and receive gain sections are programmed for no output, the hybrid balance circuit is turned off, the power amp is disabled and the device is in the non-delayed timing mode. The Latch Direction Register (LDR) is pre-set with all IL pins programmed as inputs, placing the SLIC interface pins in a high impedance state. The 6/32 Description CI/O pin is set as an input ready for the first control byte of the initialization sequence. Other initial states in the Control Register are indicated in Table 2. A reset to these same initial conditions may also be forced by driving the MR pin momentarilyhigh. This may be done either when powered-up or down. For normal operation this pin must be pulled low. If not used, MR should be hard-wired to ground. The desired modes for all programmable functions may be initialized via the control port prior to a Power-up command. TS5070 - TS5071 POWER-DOWN STATE Following a period of activity in the powered-up state the power-down state may be re-entered by writing any of the control instructions into the serial control port with the ”P” bit set to ”1” It is recommended that the chip be powered down before writing any additional instructions. In the power-down state, all non-essential circuitry is de-activated and the DX0 and DX1 outputs are in the high impedance TRI-STATE condition. The coefficients stored in the Hybrid Balance circuit and the Gain Control registers, the data in the LDR and ILR, and all control bits remain unchanged in the power-down state unless changed by writing new data via the serial control port, which remains operational. The outputs of the Interface Latches also remain active, maintaining the ability to monitor and control a SLIC. TRANSMIT FILTER AND ENCODER The Transmit section input, VFXI, is a high impedance summing input which is used as the differencing point for the internal hybrid balancecancellation signal. No external components are needed to set the gain. Following this circuit is a programmable gain/attenuationamplifier which is controlled by the contents of the Transmit Gain Register (see Programmable Functions section). An active prefilter then precedes the 3rd order high-pass and 5th order low-pass switched capacitor filters. The A/D converter has a compressingcharacteristicaccording to the standard CCITT A or µ255 coding laws, which must be selected by a controlinstructionduring initialization (see table 1 and 2). A precision onchip voltage reference ensures accurate and highly stable transmission levels. Any offset voltage arising in the gain-set amplifier, the filters or the comparator is cancelled by an internal auto-zero circuit. Each encode cycle begins immediately following the assigned Transmit time-slot. The total signal delay referenced to the start of the time-slot is approximately 165 µs (due to the Transmit Filter) plus 125 µs (due to encoding delay), which totals 290 µs. Data is shifted out on DX0 or DX1 during the selected time slot on eight rising edges of BCLK. DECODER AND RECEIVE FILTER PCM data is shifted into the Decoder’s Receive PCM Register via the DR0 or DR1 pin during the selected time-slot on the 8 fallingedges of BCLK. The Decoder consists of an expanding DAC with either A or µ255 law decoding characteristic, which is selected by the same control instructionused to select the Encode law during initialization. Following the Decoder is a 5th order low-pass switched capacitor filter with integral Sin x/x correction for the 8 kHz sample and hold. A programmable gain amplifier, which must be set by writing to the Receive Gain Register,is included,and finally a Post-Filter/Power Amplifier capable of driving a 300 Ω load to ± 3.5 V, a 600 Ω load to ± 3.8 V or 15 kΩ load to ± 4.0 V at peak overload. A decode cycle begins immediately after each receive time-slot, and 10 µs later the Decoder DAC output is updated. The total signal delay is 10 µs plus 120 µs (filter delay) plus 62.5 µs (1/2 frame) which gives approximately 190 µs. PCM INTERFACE The FSX and FSR frame sync inputs determine the beginning of the 8-bit transmit and receive timeslots respectively. They may have any duration from a single cycle of BCLK to one MCLK period LOW. Two different relationships may be established betweenthe framesync inputs and theactual time-slots on the PCM busses by setting bit 3 in the Control Register (see table 2). Non delayed data mode is similar to long-frame timing on the ETC5050/60 series of devices : time-slots being nominally coincident with the rising edge of the appropriate FS input. The alternative is to use Delayed Data mode which is similar to short-frame sync timing, in which each FS input must be high at least a half-cycle of BCLK earlier than the timeslot. The Time-Slot Assignment circuit on the device can only be used with Delayed Data timing. When using Time-Slot Assignment, the beginning of the first time-slot in a frame is identified by the appropriate FS input. The actual transmit and receive time-slots are then determined by the internal Time-Slot Assignment counters. Transmit and Receive frames and time-slots may be skewed from each other by any number of BCLK cycles. During each assigned transmit time-slot, the selected DX0/1 output shifts data out from the PCM register on the rising edges of BCLK. TSX0 (or TSX1 as appropriate) also pulls low for the first 7 1/2 bit times of the time-slot to control the TRISTATE Enable of a backplane line driver. Serial PCM data is shifted into the selected DR0/1 input during each assigned Receive time slot on the falling edges of BCLK. DX0 or DX1 and DR0 or DR1 are selectable on the TS5070 only. SERIAL CONTROL PORT Control information and data are written into or readback from COMBO IIG via the serial control port consistingof the controlclock CCLK ; the serial data input/ou tput CI/O (or separate input CI, and output CO on the TS5070 only) ; and the Chip Select input CS. All control instructions require 2 bytes,as listed in table 1, with the exceptionof a single byte power-up/down command. The byte 1 bits are used as follows: bit 7 specifies power-up or power-down; bits 6, 5, 4 and 3 specify the register address; bit 2 specifies whether the instructions is read or write; bit 1 specifies a one or two byte in7/32 TS5070 - TS5071 struction; and bit 0 is not used. To shift control data into COMBO IIG, CCLK must be pulsed high 8 timeswhile CS is low. Data on the CI or CI/O input is shifted into the serial input register on the falling edge of each CCLK pulse. After all data is shifted in, the content s of the input shift register are decoded, and may indicate that a 2nd byte of control data will follow. This second byte may either be defined by a secondbyte-wide CS pulse or may follow the first continuously,i.e. it is not mandatory for CS to return high in between the first and second control bytes. On the falling edge of the 8th CCLK clock pulse in the 2nd control byte the data is loaded into the appropriateprogrammable register. CS may remain low continuouslywhen programming succes- sive registers, if desired.However CS shouldbe set high when no data transfers are in progress. To readbackinterface Latch data or status information from COMBO IIG, the first byte of the appropriate instruction is strobed in during the first CS pulse, as defined in table 1. CS must then be taken low for a further 8 CCLK cycles, during which the data is shifted onto the CO or CI/O pin on the rising edges of CCLK. When CS is high the CO or CI/O pin is in the high-impedanceTRI-STATE, enabling the CI/O pins of many devices to be multiplexed together. Thus, to summarize, 2-byte READ and WRITE instructions may use either two 8-bit wide CS pulses or a single 16-bit wide CS pulse. Table 1: Programmable Register Instructions Byte 1 Function Byte 2 7 6 5 4 3 2 1 0 Single Byte Power–up/down P X X X X X 0 X None Write Control Register Read–back Control Register P P 0 0 0 0 0 0 0 0 0 1 1 1 X X See Table 2 See Table 2 Write Latch Direction Register (LDR) Read Latch Direction Register P P 0 0 0 0 1 1 0 0 0 1 1 1 X X See Table 4 See Table 4 Write Latch Content Register (ILR) Read Latch Content Register P P 0 0 0 0 0 0 1 1 0 1 1 1 X X See Table 5 See Table 5 Write Transmit Time–slot/port Read–back Transmit Time–slot/port P P 1 1 0 0 1 1 0 0 0 1 1 1 X X See Table 6 See Table 6 Write Receive Time–slot/port Read–back Receive Time–slot/port P P 1 1 0 0 0 0 1 1 0 1 1 1 X X See Table 6 See Table 6 Write Transmit Gain Register Read Transmit Gain Register P P 0 0 1 1 0 0 1 1 0 1 1 1 X X See Table 7 See Table 7 Write Receive Gain Register Read Receive Gain Register P P 0 0 1 1 0 0 0 0 0 1 1 1 X X See Table 8 See Table 8 Write Hybrid Balance Register ≠ 1 Read Hybrid Balance Register ≠ 1 P P 0 0 1 1 1 1 0 0 0 1 1 1 X X See Table 9 See Table 9 Write Hybrid Balance Register ≠ 2 Read Hybrid Balance Register ≠ 2 P P 0 0 1 1 1 1 1 1 0 1 1 1 X X See Table 10 See Table 10 Write Hybrid Balance Register ≠ 3 Read Hybrid Balance Register ≠ 3 P P 1 1 0 0 0 0 0 0 0 1 1 1 X X Notes: 1. Bit 7 of bytes 1 and 2 is always the first bit clocked into or out of the CI, CO or CI/CO pin. 2. ”P” is the power-up/down control bit, see ”Power-up” section (”0” = Power Up ”1” = Power Down). PROGRAMMABLE FUNCTIONS POWER-UP/DOWN CONTROL Following power-on initialization, power-up and power-down control may be accomplished by writing any of the control instructions listed in table 1 into COMBO IIG with the ”P” bit set to ”0” for power-up or ”1” for power-down. Normally it is recommended that all programmable functions be initially programmed while the device is powered down. Power state control can then be included with the last programming instruction or the sepa8/32 rate single-byte instruction. Any of the programmable registers may also be modified while the device is powered-up or down be setting the ”P” bit as indicated. When the power up or down control is entered as a single byte instruction, bit one (1) must be set to a 0. When a power-up command is given, all de-activated circuits are activated, but the TRI-STATE PCM output(s), DX0 (and DX1), will remain in the high impedance state until the second FSX pulse after power-up. TS5070 - TS5071 CONTROL REGISTER INSTRUCTION The first byte of a READ or WRITE instruction to the Control Register is as shown in table 1. The second byte functions are detailed in table 2. MASTER CLOCK FREQUENCY SELECTION A Master clock must be provided to COMBO IIG for operation of the filter and coding/decoding functions. The MCLK frequency must be either 512 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, or 4.096 MHz and must be synchronous with BCLK. Bits F1 and F0 (see table 2) must be set during initialization to select the correct internal divider. ANALOG LOOPBACK Analog Loopback mode is entered by setting the ”AL” and ”DL” bits in the Control Register as shown in table 2. In the analog loopback mode, the Transmit input VFXI is isolated from the input pin and internally connected to the VFRO output, forming a loop from the Receive PCM Register back to the Transmit PCM Register. The VFRO pin remains active, and the programmed settings of the Transmit and Receive gains remain unchanged, thus care must be taken to ensure that overload levels are not exceeded anywhere in the loop. Hybrid balancing must be disabled for meaning ful analog loopback Function. CODING LAW SELECTION Bits ”MA” and ”IA” in table 2 permit the selection of µ255 coding or A-law coding with or without even-bit inversion. DIGITAL LOOPBACK Digital Loopback mode is entered by setting the ”DL” bit in the Control Register as shown in table 2. Table 2: Control Register Byte 2 Functions Bit Number 7 6 5 4 3 2 1 0 F1 F0 MA IA DN DL AL PP 0 0 1 1 0 1 0 1 Function MCLK = MCLK = MCLK = MCLK = * Select µ. 255 Law A–law, Including Even Bit Inversion A–Law, No Even Bit Inversion X 0 1 0 1 1 512 kHz 1. 536 or 1. 544 MHz 2. 048 MHz * 4. 096 MHz 0 1 Delayed Data Timing Non–delayed Data Timing Normal Operation * Digital Loopback Analog Loopback 0 X 1 0 1 0 * 0 1 Power Amp Enabled in PDN Power Amp Disabled in PDN * (*) State at power-on initialization (bit 4 = 0) Table 3: Coding Law Conventions. m255 Law A-law without even bit inversion MSB LSB True A-law with even bit inversion MSB LSB MSB LSB VIN = +Full Scale 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 VIN = 0V 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VIN = -Full Scale 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 Note: The MSB is always the first PCM bit shifted in or out of COMBO IIG. 9/32 TS5070 - TS5071 This mode provides another stage of path verification by enabling data written into the Receive PCM Register to be read back from that register in any Transmit time-slot at DX0 or DX1. For Analog Loopback as well as for Digital Loopback PCM decoding continues and analog output appears at VFRO. The output can be disabled by pro gramming ”No Output” in the Receive Gain Register (see table 8). INTERFACE LATCH DIRECTIONS Immediately following power-on, all Interface Latches assume they are inputs, and therefore all IL pins are in a high impedance state. Each IL pin may be individually programmed as a logic input or output by writing the appropriate instruction to the LDR, see table 1 and 4. Bits L5-L0 must be set by writing the specific instruction to the LDR with the L bits in the second byte set as specified in table 4. Unused interface latches should be programmed as outputs. For the TS5071, L5 should always be programmed as an output. Table 4: Byte 2 Function of Latch Direction Register Bit Number 7 6 5 4 3 2 1 0 L0 L1 L2 L3 L4 L5 X X LN Bit IL Direction 0 1 Input * Output INTERFACE LATCH STATES Interface Latches configured as outputs assume the state determined by the appropriate data bit in the 2-byte instruction written to the Latch Content Register (ILR) as shown in tables 1 and 5. Latches configured as inputs will sense the state applied by an external source, such as the OffHook detect output of a SLIC. All bits of the ILR, i.e. sensed inputs and the programmed state of outputs, can be read back in the 2nd byte of a READ from the ILR. It is recommended that, during initialization, the state of IL pins to be configured as outputs should first be programmed, followed immediately by the Latch Direction Register. Table 5: Interface Latch Data Bit Order Bit Number 7 6 5 4 3 2 1 0 D0 D1 D2 D3 D4 D5 X X TIME-SLOT ASSIGNMENT COMBO IIG can operate in either fixed time-slot or time-slot assignment mode for selecting the Transmit and Receive PCM time-slots. Following poweron, the deviceis automaticallyin Non-Delayed Timing mode, in which the time-slot always begins with the leading (rising) edge of frame sync inputs FSX and FSR. Time-Slot Assignment may only be used with Delayed Data timing : see figure 6. FSX and FSR may have any phase relationship with each other in BCLK period increments. (*) State at power-on initilization. Note: L5 should be programmed as an output for the TS5071. Table 6: Byte 2 of Time-slot and Port Assignment Instructions Bit Number 5 6 7 T5 PS EN (note 1) (note 2) 0 X X Function 4 T4 3 T3 2 T2 1 T1 0 T0 X X X X X Assign One Binary Coded Time-slot from 0–63 1 0 Assign One Binary Coded Time-slot from 0–63 Assign One Binary Coded Time-slot from 0–63 1 1 Assign One Binary Coded Time-slot from 0–63 Notes: 1. The ”PS” bit MUST always be set to 0 for the TS5071. 2. T5 is the MSB of the time-slot assignment. (*) State at power-on initialization 10/32 Disable DX Outputs (transmit instruction) * Disable DR Inputs (receive instruction) * Enable DX0 Output, Disable D X1 Output (Transmit instruction) Enable DR0 Input, Disable D R1 Input (Receive Instruction) Enable DX1 Output, Disable D X0 Output (Transmit instruction) Enable DR1 Input, Disable D R0 Input (Receive Instruction) TS5070 - TS5071 Alternatively, the internal time-slot assignment counters and comparators can be used to access any time-slot in a frame,using the framesync inputs as marker pulses for the beginning of transmit and receive time-slot 0. In this mode, a frame may consist of up to 64 time-slots of 8 bits each. A time-slot is assignedby a 2-byte instructionas shown in table 1 and 6. The last 6 bits of the second byte indicate the selected time-slot from 0-63 using straight binary notation. A new assignment becomes active on the second frame following the end of the Chip Select for the second control byte. The ”EN” bit allows the PCM inputs DR0/1 or outputs DX0/1 as appropriate, to be enabled or disabled. Time-Slot Assignment mode requires that the FSX and FSR pulses must conformto the delayedtiming format shown in figure 6. PORT SELECTION On the TS5070 only, an additional capability is available : 2 Transmit serial PCM ports, DX0 and DX1, and 2 receive serial PCM ports, DR0 and DR1, are provided to enable two-way space switching to be implemented. Port selections for transmit and receive are made within the appropriate time-slot assignmentinstruction using the ”PS” bit in the second byte. On the TS5071, only ports DX0 and DR0 are available, therefore the ”PS” bit MUST always be set to 0 for these devices. Table 6 shows the format for the second byte of both transmitand receive time-slot and port assignment instructions. TRANSMIT GAIN INSTRUCTION BYTE 2 The transmit gain can be programmed in 0.1 dB steps by writing to the Transmit Gain Register as defined in tables 1 and 7. This corresponds to a range of 0 dBm0 levels at VFXI between 1.619 Vrms and 0.087 Vrms (equivalent to + 6.4 dBm to – 19.0 dBm in 600 Ω). To calculate the binary code for byte 2 of this instruction for any desired input 0 dBm0 level in Vrms, take the nearest integer to the decimal number given by : 200 X log10 (V/√ 6 ) + 191 and convert to the binary equivalent. Some examples are given in table 7. Table 7: Byte 2 of Transmit Gain Instructions. Bit Number 0dBm0 Test Leve at VFXI 7 6 5 4 3 2 1 0 In dBm (Into 600Ω) 0 0 0 0 0 0 0 0 No Output In Vrms (approx.) 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 – 19 – 18.9 0.087 0.088 1 0 1 1 1 1 1 1 0 0.775 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 +6.3 +6.4 1.60 1.62 (*) State at power initialization RECEIVE GAIN INSTRUCTION BYTE 2 The receive gain can be programmed in 0.1 dB steps by writing to the Receive GainRegister as defined in table 1 and 8. Note the following restriction on output drive capability : a) 0 dBm0 levels ≤ 8.1dBm at VFRO may be driven into a load of ≥ 15 kΩ to GND, b) 0 dBm0 levels ≤ 7.6dBm at VFRO may be driven into a load of ≥ 600 Ω to GND, c) 0 dBm levels ≤ 6.9dBm at VFRO may be driven into a load of ≥ 300 Ω to GND. To calculate the binary code for byte 2 of this instruction for any desired output 0 dBm0 level in Vrms, take the nearest integer to the decimal number given by : 6 ) + 174 200 X log10 (V/√ a n d convert to the binary equivalent. Some examples are given in table 8. 11/32 TS5070 - TS5071 Table 8: Byte 2 of Receive Gain Instructions. Bit Number 0dBm0 Test Leve at VFR0 7 6 5 4 3 2 1 0 In dBm (Into 600Ω) 0 0 0 0 0 0 0 0 No Output 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 – 17.3 – 17.2 0.106 0.107 1 0 1 0 1 1 1 0 0 0.775 1 1 1 1 0 0 1 1 + 6.9 (note 1) 1.71 1 1 1 1 1 0 1 0 + 7.6 (note 2) 1.86 1 1 1 1 1 1 1 1 + 8.1 (note 3) 1.07 Notes: 1. Maximum level into 300Ω ; 2. Maximum level into 600Ω; 3. RL ≥15KΩ HYBRID BALANCE FILTER The Hybrid Balance Filter on COMBO IIG is a programmable filter consisting of a second-order Bi-Quad section, Hybal1, followed by a first-order section, Hybal2, and a programmable attenuator. Either of the filter sections can be bypassed if only one is required to achieve good cancellation. A selectable 180 degree inverting stage is included to compensate for interface circuits which also invert the transmit input relative to the receive output signal. The Bi-Quad is intended mainly to balance low frequency signals across a transformer SLIC, and the first order section to balance midrange to higher audio frequency signals. The attenuator can be programmed to compensate for VF RO to VFXI echos in the range of -2.5 to – 8.5 dB. As a Bi-Quad, Hybal1 has a pair of low frequency zeroes and a pair of complex conjugate poles. When configuring the Bi-Quad, matching the phase of the hybrid at low to midband frequencies is most critical. Once the echo path is correctly balanced in phase, the magnitude of the cancellation signal can be corrected by the programmable In Vrms (approx.) (*) State at power on initialization attenuator. The Bi-Quad mode of Hybal1 is most suitable for balancing interfaces with transformers having high inductance of 1.5 Henries or more. An alternative configuration for smaller transformers is available by converting Hybal1 to a simple first-order section with a single real low frequency pole and 0 Hz zero. In this mode, the pole/zero frequency may be programmed. Many line interfaces can be adequately balanced by use of the Hybal1 section only, in which case the Hybal2 filter should be de-selected to bypass it. Hybal2, the higher frequency first-order section, is provided for balancing an electronic SLIC, and is also helpful with a transformer SLIC in providing additional phase correction for mid and high-band frequencies, typically 1 kHz to 3.4 kHz. Such a correction is particularly useful if the test balance impedance includes a capacitor of 100 nF or less, such as the loaded and non-loaded loop test networks in the United States. Independent placement of the pole and zero location is provided. Table 9: Hybrid Balance Register 1 Byte 2 Instruction. Bit State 7 0 Disable Hybrid Balance Circuit Completely. * No internal cancellation is provided. 1 Enable Hybrid Balance Cancellation Path 0 Phase of the internal cancellation signal assumes inverted phase of the echo path from VFRO to VFXI. 1 Phase of the internal cancellation signal assumes no phase inversion in the line interface. 0 Bypass Hybal 2 Filter Section 1 Enable Hybal 2 Filter Section 6 5 G4–G0 (*) State at power on initialization Setting = Please refer to software TS5077 2 12/32 Function Attenuation Adjustment for the Magnitude of the Cancellation Signal. Range is – 2.5 dB (00000) to – 8.5 dB (11000) TS5070 - TS5071 Figure 1 shows a simplified diagram of the local echo path for a typical application with a transformer interface. The magnitude and phase of the local echo signal, measured at VFXI, are a function of the termination impedance ZT, the line trans- former and the impedanceof the 2 W loop, ZL. If the impedance reflected back into the transformer primary is expressed as ZL’ then the echo path transfer function from VFRO to VFXI is : H(W) = ZL’ /(ZT + ZL’) (1) Figure 1: Simplified Diagram of Hybrid Balance Circuit PROGRAMMING THE FILTER On initial power-up the Hybrid Balance filter is disabled. Before the hybrid balance filter can be programmed it is necessary to design the transformer and terminationimpedancein orderto meet system 2 W input return loss specifications, which are normally measured against a fixed test impedance (600 or 900 Ω in most countries). Only then can the echo path be modeled and the hybrid balance filter programmed. Hybrid balancing is also measured against a fixed test impedance, specified by each national Telecom administration to provide adequate control of talker and listener echo over the majority of their network connections. This test impedance is ZL in figure 1. The echo signal and the degree of transhybrid loss obtained by the programmable filter must be measured from the PCM digital input DR0, to the PCM digital output DX0, either by digital test signalanalysisor by conversion back to analog by a PCM CODEC/Filter. Three registers must be programmed in COMBO IIG to fully configure the Hybrid Balance Filter as follows : Register 1: select/de-select Hybrid Balance Filter; invert/non-invert cancellation signal; select/de-select Hybal2 filter section; attenuatorsetting. Register 2: select/de-select Hybal1 filter; set Hybal1 to Bi-Quad or 1st order; program pole and zero frequency. Table 10: Hybrid Balance Register 2 Byte 2 instructions Bit Number Function 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 By Pass Hybal 1 Filter X X X X X X X X Pole/zero Setting Register 3 : programpole frequency in Hybal2 filter; program zero frequencyin Hybal2 filter; settings = Please refer to software TS5077-2. Standard filter design techniques may be used to model the echo path (see equation (1)) and design a matching hybrid balance filter configuration.Alternatively, the frequency response of the echo path can be measured and the hybrid balance filter programmed to replicate it. An Hybrid Balance filter design guide and software optimization program are available under license from SGS-THOMSON Microelectronics (order TS5077-2). 13/32 TS5070 - TS5071 APPLICATION INFORMATION Figure 2 shows a typical application of the TS5070 together with a transformer SLIC. The design of the transformer is greatly simplified due to the on-chip hybrid balancecancellation filter. Only one single secondary winding is required (see application note AN.091 - Designing a subscriber line card module using the TS5070/COMBO IIG). Figures 3 and 4 show an arrangement with SGSThomson monolithic SLICS. POWER SUPPLIES While the pins of the TS5070 and TS5071/COMBO IIG devices are well protected against electrical misuse, it is recommended that the standard CMOS practice of applying GND to the device be- 14/32 fore any otherconnectionsare made shouldalways be followed.In applicationswhere the printedcircuit card may be plugged into a hot socket with power and clocks already present, an extra long ground pin on the connectorshould be used and a Schottky diode connected between VSS and GND. To minimize noise sources all ground connections to each device should meet at a common point as close as possible to the GND pin in order to prevent the interaction of ground return currents flowing through a common bus impedance. Power supply decoupling capacitors of 0.1 µF shouldbe connectedfrom this common device ground point to VCC and VSS as closeto thedevice pins as possible.VCC and VSS should also be decoupled with low effective series resis-tance capacitorsof at least10 µF locatednear the card edge connector. TS5070 - TS5071 Figure 2: Transformer SLIC + COMBO IIG. 15/32 TS5070 - TS5071 L3000 L3092 Figure 4: Interface with L3092 + L3000 Silicon SLIC. 16/32 TS5070 - TS5071 ELECTRICAL OPERATING CHARACTERISTICS Unless otherwise noted, limits in BOLD characters are guaranteed for VCC = + 5 V ± 5 % ; VSS = – 5 V ± 5 %. TA = -40 °C to 85 °C by correlation with 100% electrical testing at TA = 25 °C. All other limits are assured by correlation with other production tests and/or product design and characterisation. All signals referencedto GND. Typicals specified at VCC = + 5 V, VSS = − 5 V, TA = 25 °C. DIGITAL INTERFACE Symbol Parameter VIL Input Low Voltage All Digital Inputs (DC measurement) VIH Input High Voltage All Digital Inputs (DC measurement) VOL Output Low Voltage DX0 and DX1, TSX0, TSX1 and CO, IL = 3.2mA All Other Digital Outputs, IL = 1mA VOH Output High Voltage DX0 and DX1 and CO, IL = -3.2mA All other digital outputs except TSX, IL = -1mA All Digital Outputs, IL = -100µA Min. Typ. Max. Unit 0.7 V 2.0 V 0.4 2.4 VCC-0.5 V V V -10 10 µA IIL Input Low Current all Digital Inputs (GND < VIN < VIL) IIH Input High Current all Digital Inputs Except MR (VIH < VIN < VCC) -10 10 µA IIH Input High Current on MR -10 100 µA IOZ Output Current in High Impedance State (TRI-STATE) DX0 and DX1, CO and CI/O (as an input) IL5-IL0 as inputs (GND < VO < VCC) -10 10 µA Max. Unit 10 µA ANALOG INTERFACE Symbol Parameter Min. IVFXI Input Current VFXI (-3.3V < VFXI < 3.3V) -10 R VFXI Input Resistance VFXI (-3.3V < VFXI < 3.3V) 390 VOSX Input offset voltage at VFXI 0dBm0 = -19dBm 0dBm0 = +6.4dBm RLVFRO Load Resistance at VFRO 0dBm0 = 8.1dBm 0dBm0 = 7.6dBm 0dBm0 = 6.9dBm CLVFRO Load Capacitance CLVFRO from VFRO to GND ROVFRO Output Resistance VFRO (steady zero PCM code applied to DR0 or DR1) VOSR Output Offset Voltage at VFRO (alternating ±zero PCM code applied to DR0 or D R1, 0dBm0 = 8.1dBm) Typ. 620 kΩ 10 200 15 600 300 kΩ Ω Ω 1 -200 mV mV 200 pF 3 Ω 200 mV 17/32 TS5070 - TS5071 ELECTRICAL OPERATING CHARACTERISTICS (continued) POWER DISSIPATION Symbol Typ. Max. Unit ICC0 Power Down Current (CCLK, CI/O, CI = 0.4V, CS = 2.4V) Interface Latches set as Outputs with no load All over Inputs active, Power Amp Disabled Parameter 0.3 1.5 mA -ISS0 Power Down Current (as above) 0.1 0.3 mA ICC1 Power Up Current (CCLK, CI/O, CI = 0.4V, CS = 2.4V) No Load on Power Amp Interface Latches set as Outputs with no Load 7 11 mA -ISS1 Power Up Current (as above) 7 11 mA ICC2 Power Down Current with Power Amp Enabled 2 4 mA -ISS2 Power Down Current with Power Amp Enabled 2 4 mA TIMING SPECIFICATIONS Unless otherwisenoted,limits in BOLDcharactersare guaranteed for VCC = + 5 V ± 5 %; VSS = -5V ± 5 %. T A = -40 °C to 85 °C by correlation with 100 % electrical testing at TA = 25 °C. All other limits are assured by correlation with other production tests Min. and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = + 5 V, VSS = -5 V, T A = 25 °C. All timing parametersaremeasuredatVOH =2.0V andVOL = 0.7 V. See Definitions and Timing Conventions section for test methods information. MASTER CLOCK TIMING Symbol Parameter Min. Typ. Max. Unit kHz MHz MHz MHz MHz fMCLK Frequency of MCLK (selection of frequency is programmable, see table 2) tWMH Period of MCLK High (measured from VIH to VIH, see note 1) 80 ns tWML Period of MCLK Low (measured from VIL to VIL, see note 1 ) 80 ns tRM Rise Time of MCLK (measured from VIL or VIH) 30 tFM Fall Time of MCLK (measured from VIH to VIL) 30 tHBM Hold Time, BCLK Low to MCLK High (TS5070 only) 50 ns tWFL Period of FSX or FSR Low (Measured from VIL to VIL) 1 (*) (*) MCLK period 18/32 512 1.536 1.544 2.048 4.096 ns TS5070 - TS5071 TIMING SPECIFICATIONS (continued) PCM INTERFACE TIMING Symbol Parameter Min. 64 Typ. Max. Unit 4096 kHz fBCLK Frequency of BCLK (may vary from 64KHz to 4.096MHz in 8KHz increments, TS5070 only) tWBH Period of BCLK High (measured from VIH to VIH) 80 ns tWBL Period of BCLK Low (measured from VIL to VIL) 80 ns tRB Rise Time of BCLK (measured from VIL to VIH) 30 ns tFB Fall Time of BCLK (measured from VIH to VIL) 30 ns tHBF Hold Time, BCLK Low to FSX/R High or Low 30 tSFB Setup Time FSX/R High to BCLK Low 30 tDBD Delay Time, BCLK High to Data Valid (load = 100pF plus 2 LSTTL loads) tDBZ Delay Time from BCLK8 Low to Dx Disabled (if FSx already low); FSx Low to Dx Disabled (if BCLK8 low); BCLK9 High to Dx Disabled (if FSx still high) tDBT Delay Time from BCLK and FSx Both High to TSx Low (Load = 100pF plus 2 LSTTL loads) 15 15 ns ns 80 ns 80 ns 60 ns 60 ns 80 ns tZBT Delay Time from BCLK8 low to TSx Disabled (if FSx already low); FSx Low to TSx Disabled (if BCLK8 low); BCLK9 High to TSx Disabled (if FSx still high); tDFD Delay Time, FSx High to Data Valid (load = 100pF plus 2 LSTTL loads, applies if FSx rises later than BCLK rising edge in nondelayed data mode only) tSDB Setup Time, DR 0/1 Valid to BCLK Low 30 ns tHBD Hold Time, BCLK Low to DR0/1 Invalid 20 ns Figure 5: Non Delayed Data Timing (short frame mode) 19/32 TS5070 - TS5071 Figure 6: Delayed Data Timing (short frame mode) SERIAL CONTROL PORT TIMING Symbol Parameter Min. Typ. Max. Unit 2.048 MHz fCCLK Frequency of CCLK tWCH Period of CCLK High (measured from VIH to VIH) 160 ns tWCL Period of CCLK Low (measured from VIL to VIL) 160 ns tRC Rise Time of CCLK (measured from VIL to VIH) 50 ns tFC Fall Time of CCLK (measured from VIH to VIL) 50 ns tHCS Hold Time, CCLK Low to CS Low (CCLK1) 10 ns tHSC Hold Time, CCLK Low to CS High (CCLK8) 100 ns tSSC Setup Time, CS Transition to CCLK Low 70 ns tSSCO Setup Time, CS Transition to CCLK High (to insure CO is not enabled for single byte) 50 ns tSDC Setup Time, CI (CI/O) Data in to CCLK low 50 ns tHCD Hold Time, CCLK Low to CI (CI/O) Invalid 50 ns tDCD Delay Time, CCLK High to CO (CI/O) Data Out Valid (load = 100 pF plus 2 LSTTL loads) 80 ns tDSD Delay Time, CS Low to CO (CI/O) Valid (applies only if separate CS used for byte 2) 80 ns tDDZ Delay Time, CS or CCLK9 High to CO (CI/O) High Impedance (applies to earlier of CS high or CCLK9 high) 80 ns Max. Unit 15 INTERFACE LATCH TIMING Symbol Parameter Min. tSLC Setup Time, IL Valid to CCLK 8 of Byte 1 Low. I L as Input 100 tHCL Hold Time, IL Valid from CCLK 8 of Byte 1 Low. IL as Input 50 tDCL Delay Time, CCLK 8 of Byte 2 Low to IL. CL = 50 pF. IL as Output Typ. ns ns 200 ns Max. Unit MASTER RESET PIN Symbol tWMR Parameter Duration of Master Reset High Min. 1 Typ. µs 20/32 TS5070 - TS5071 Figure 7: Control Port Timing 21/32 TS5070 - TS5071 TRANSMISSION CHARACTERISTICS Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = + 5 V ± 5 % ; VSS = – 5 V ± 5 %, TA =-40 °Cto 85 °C by correlation with 100 % electrical testing at TA = 25 °C (-40°C to 85°C for TS5070-X and TS5071-X). f = 1031.25 Hz, VFXI = 0 dBm0, DR0 or DR 1 = 0 dBm0 PCM code, Hybrid Balance filter disabled. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. dBm levels are into 600 ohms. Typicals specified at VCC = + 5 V, VSS = -5 V, TA = 25 °C. AMPLITUDE RESPONSE Symbol Parameter Min. Typ. Max. Unit Absolute levels The nominal 0 dBm 0 levels are : 0 dB Tx Gain VFXI 25.4 dB Tx Gain VFRO 1.618 86.9 Vrms mVrms 1.968 1.858 1.714 105.7 Vrms Vrms Vrms mVrms 0 dB Tx Gain 25.4 dB Tx Gain 2.323 124.8 Vrms mVrms 0 dB Rx Attenuation (R L ≥ 15 kΩ) 0.5 dB Rx Attenuation (R L ≥ 300 Ω) 1.2 dB Rx Attenuation (R L ≥ 300 Ω) 25.4 dB Rx Attenuation 2.825 2.667 2.461 151.7 Vrms Vrms Vrms mVrms 0 dB Tx Gain 25.4 dB Tx Gain 2.332 125.2 Vrms mVrms 0 dB Rx Attenuation (R L ≥ 15 kΩ) 0.5 dB Rx Attenuation (R L ≥ 600 Ω) 1.2 dB Rx Attenuation (R L ≥ 300 Ω) 25.4 dB Rx Attenuation 2.836 2.677 2.470 152.3 Vrms Vrms Vrms mVrms 0 dB Rx Attenuation (RL ≥ 15 kΩ) 0.5 dB Rx Attenuation (RL ≥ 600 Ω) 1.2 dB Rx Attenuation (RL ≥ 300 Ω) 25.4 dB Rx Attenuation Maximum Overload The nominal overload levels are : A-law VFXI VFRO µ-law VFXI VFRO Transmit Gain Absolute Accurary GXA Transmit Gain Programmed for 0 dBm0 = 6.4 dBm, A-law Measure Deviation of Digital Code from Ideal 0 dBm0 PCM Code at DX0/1, f = 1031.25 Hz TA = 25 °C, VCC = 5 V, VSS = – 5 V – 0.15 0.15 dB – 0.1 0.1 dB – 0.3 0.3 dB Transmit gain Variation with Programmed Gain GXAG Programmed level from -12.6dBm ≤ 0dBm ≤ 6.4dBm Programmed level from -19dBm ≤ 0dBm ≤ 12.7dBm Note: ±0.1dB min/max is available as a selected part Calculate the Deviation from the Programmed Gain Relative to GXA i.e., GXAG = Gactual – Gprog – GXA TA = 25 °C, VCC = 5 V, VSS = – 5 V 22/32 TS5070 - TS5071 AMPLITUDE RESPONSE (continued) Symbol GXAF Parameter GXAT Transmit Gain Variation with Temperature Measured Relative to GXA,VCC = 5V, VSS= -5V -19dBm < 0dBm < 6.4dBm GXAV Transmit Gain Variation with Supply VCC = 5V ± 5%, VSS = -5V ± 5% Measured Relative to GXA TA = 25 °C, o dBm0 = 6.4dBm -26 -0.1 0.15 0 -14 -32 dB dB dB dB dB dB -24.9 -0.1 0.15 0.15 0.15 0 -13.5 -32 -32 -32 dB dB dB dB dB dB dB dB dB dB -0.1 0.1 dB -0.05 0.05 dB -0.2 -0.4 -1.2 0.2 0.4 1.2 dB dB dB -0.15 0.15 dB -0.1 0.1 dB -0.3 0.3 dB -1.8 -0.15 -0.7 -1.7 -0.15 -0.15 -0.15 -0.74 Receive Gain Variation with Programmed Gain Programmed level from -10.9dBm ≤ 0dBm ≤ 8.1dBm Programmed level from -17.3dBm ≤ 0dBm ≤ -11dBm Note: ±0.1dB min/max is available as a selected part Calculate the Deviation from the Programmed Gain Relative to GRA I.e. GRAG = Gactual - Gprog - GRA TA = 25°C, VCC = 5V, VSS = -5V 23/32 Unit Receive Gain Absolute Accuracy 0 dBm0 = 8.1 dBm, A-law Apply 0 dBm0 PCM Code to DR0 or D R1 Measure VFRO, f =1015.625Hz TA = 25 °C, VCC = 5V, VSS = -5V GRAG Max. Transmit Gain Variation with Signal Level Sinusoidal Test Method, Reference Level = 0 dBm0 VFXI = -40 dBm0 to + 3 dBm0 VFXI = -50 dBm0 to -40 dBm0 VFXI = -55 dBm0 to -50 dBm0 GRA Typ. Transmit Gain Variation with Frequency Relative to 1031.25 Hz (note 2) -19 dBm < o dBm0 < 6.4 dBm DR0 (or D R1) = 0 dBm0 Code f = 60Hz f = 200 Hz f = 300 Hz to 3000 Hz f = 3400 Hz f = 4000 Hz f > 4600 Hz Measure Response at Alias Frequency from 0 kHz to 4 kHz 0 dBm0 = 6.4 dBm VFXI = -4 dBm0 (note2) f = 62.5 Hz f = 203.125 Hz f = 2093.750 Hz f = 2984.375 Hz f = 3296.875 Hz f = 3406.250 Hz f = 3984.375 Hz f = 5250 Hz, Measure 2750 Hz f = 11750Hz, Measure 3750 Hz f = 49750 Hz, Measure 1750 Hz GXAL Min. TS5070 - TS5071 AMPLITUDE RESPONSE (continued) Symbol GRAT Parameter Unit -0.1 0.1 dB -0.05 0.05 dB -0.25 -0.15 -0.7 0.15 0.15 0 -14 dB dB dB dB -0.15 -0.15 -0.15 -0.15 -0.74 0.15 0.15 0.15 0.15 0 -13.5 dB dB dB dB dB dB -0.2 -0.4 -1.2 0.2 0.4 1.2 dB dB dB -0.2 -0.2 0.2 0.2 dB dB Receive Gain Variation with Frequency Relative to 1015.625 Hz, (note 2) DR0 or DR1 = 0 dBm0 Code -17.3dBm < 0 dBm0 < 8.1dBm f = 200Hz f = 300Hz to 3000Hz f = 3400Hz f = 4000Hz GR = 0dBm0 = 8.1dBm DR0 = -4dBm0 Relative to 1015.625 (note 2) f = 296.875 Hz f = 1906.250Hz f = 2812.500Hz f = 2984.375Hz f = 3406.250Hz f = 3984.375Hz GRAL Max. Receive Gain Variation with Supply Measured Relative to GRA VCC = 5V ± 5%, VSS = -5V ± 5% TA = 25°C, 0dBm 0 = 8.1 dBm GRAF Typ. Receive Gain Variation with Temperature Measure Relative to GRA VCC = 5V, VSS = -5V -17dBm < 0dBm0 < 8.1dBm GRAV Min. Receive Gain Variation with Signal Level Sinusoidal Test Method Reference Level = 0dBm0 DR0 = -40dBm0 to +3dBm0 DR0 = -50dBm0 to -40dBm0 DR0 = -55dBm0 to -50dBm0 DR0 = 3.1dBm0 RL = 600Ω, 0dBm0 = 7.6dBm RL = 300Ω, 0dBm0 = 6.9dBm 24/32 TS5070 - TS5071 ENVELOPE DELAY DISTORTION WITH FREQUENCY Symbol DXA Parameter Min. 500 – 600 Hz 600 – 800 Hz 800 – 1000 Hz 1000 – 1600 Hz 1600 – 2600 Hz 2600 – 2800 Hz 2800 – 3000 Hz µs 220 145 75 40 75 105 155 µs µs µs µs µs µs µs 200 µs 90 125 175 µs µs µs µs µs Rx Delay, Relative to DRA f= f= f= f= f= 25/32 315 Rx Delay, Absolute f = 1600 Hz DRR Unit Tx Delay, Relative to DXA f= f= f= f= f= f= f= DRA Max. Tx Delay Absolute f = 1600 Hz DXR Typ. 500 – 1000 Hz 1000 – 1600 Hz 1600 – 2600 Hz 2600 – 2800 Hz 2800 – 3000 Hz – 40 – 30 TS5070 - TS5071 NOISE Symbol Typ. Max. Unit NXC Transmit Noise, C Message Weighted µ-law Selected (note 3) 0 dBm0 = 6.4dBm 12 15 dBrnC0 NXP Transmit Noise, Psophometric Weighted A-law Selected (note 3) 0 dBm0 = 6.4dBm -74 -67 dBm0p NRC Receive Noise, C Message Weighted µ-law Selected PCM code is alternating positive and negative zero 8 11 dBrnC0 NRP Receive Noise, Psophometric Weighted A-law Selected PCM Code Equals Positive Zero -82 -79 dBm0p NRS Noise, Single Frequency f = 0Hz to 100kHz, Loop Around Measurement VFXI = 0Vrms -53 dBm0 PPSRX NPSRX PPSRR NPSRR SOS Parameter Min. Positive Power Supply Rejection Transmit VCC = 5VDC + 100mVrms f = 0Hz to 4000Hz (note 4) f = 4kHz to 50kHz 30 30 dBp dBp Negative Power Supply Rejection Transmit VSS = -5VDC + 100mVrms f = 0Hz to 4000Hz (note 4) f = 4kHz to 50kHz 30 30 dBp dBp Positive Power Supply Rejection Receive PCM Code Equals Positive Zero VCC = 5VDC + 100mVrms Measure VFR0 f = 0Hz to 4000Hz f = 4kHz to 25kHz f = 25kHz to 50kHz 30 40 36 dBp dB dB Negative Power Supply Rejection Receive PCM Code Equals Positive Zero VSS = -5VDC + 100mVrms Measure VFR0 f = 0Hz to 4000Hz f = 4kHz to 25kHz f = 25kHz to 50kHz 30 40 36 dBp dB dB Spurious Out-of Band Signals at the Channel Output 0dBm0 300Hz to 3400Hz input PCM code applied at DR0 (DR1) Relative to f = 1062.5Hz 4600Hz to 7600Hz 7600Hz to 8400Hz 8400Hz to 50000Hz -30 -40 -30 dB dB dB 26/32 TS5070 - TS5071 DISTORTION Symbol STDX Parameter Level = 3dBm0 Level = -30dBm0 to 0dBm0 Level = -40dBm0 Level = -45dBm0 STDR Min. Typ. Max. Unit Signal to Total Distortion Transmit Sinusoidal Test Method Half Channel 33 36 30 25 dBp dBp dBp dBp 33 36 30 25 dBp dBp dBp dBp Signal to Total Distortion Receive Sinusoidal Test Method Half Channel Level = 3dBm0 Level = -30dBm0 to 0dBm0 Level = -40dBm0 Level = -45dBm0 SFDX Single Frequency Distortion Transmit -46 dB SFDR Single Frequency Distortion Receive -46 dB Intermodulation Distortion Transmit or Receive Two Frequencies in the Range 300Hz to 3400Hz -41 dB IMD CROSSTALK Symbol Typ. Max. Unit CTX-R Transmit to Receive Crosstalk, 0dBm0 Transmit Level f = 300 to 3400Hz DR = Idle PCM Code Parameter Min. -90 -75 dB CTR-X Receive to Transmit Crosstalk, 0dBm0 Receive Level f = 300 to 3400Hz (note 4) -90 -70 dB Notes: 1. Applies only to MCLK frequencies ≥ 1.536 MHz. At 512 kHz A 50:50 ± 2 % duty cycle must be used. 2. A multi-tone test technique is used (peak/rms ≤ 9.5 dB). 3. Measured by grounded input at VFXI. 4. PPSRX, NPSRX and CTR-X are measured with a – 50 dBm0 activation signal applied to VF XI. A signal is Valid if it is above VIH or below VIL and invalid if it is between VIL and VIH. For the purpose of the specification the following conditions apply : a) All input signals are defined as VIL = 0.4 V, VIH = 2.7 V, tR < 10 ns, tF 10 ns b) tR is measured from V IL to VIH, tF is measured from VIH to VIL c) Delay Times are measured from the input signal Valid to the clock input invalid d) Setup Times are measured from the data input Valid to the clock input invalid e) Hold Times are measured from the clock signal Valid to the data input invalid f) Pulse widths are measured from V IL to VIL or from VIH to VIH 27/32 TS5070 - TS5071 DEFINITIONS AND TIMING CONVENTIONS DEFINITIONS VIH VIH is the D.C. input level above which an input level is guaranteed to appear as a logical one. This parameter is to be measured by performing a functional test at reduced clock speeds and nominal timing (i.e. not minimum setup and hold times or output strobes), with the high level of all driving signals set to VIH and maximum supply voltages applied to the device. VIL VIL is the D.C. input level below which an input level is guaranteed to appear as a logical zero the device. This parameter is measured in the same manner as VIH but with all driving signal low levels set to VIL and minimum supply voltage applied to the device. VOH VOH is the minimmum D.C. output level to which an output placed in a logical one state will converge when loaded at the maximum specified load current. VOL VOL is the maximum D.C. output level to which an output placed in a logical zero state will converge when loaded at the maximum specified load current. Threshold Region Valid Signal The threshold region is the range of input voltages between VIL and VIH . A signal is Valid if it is in one of the valid logic states. (i.e. above VIH or below VIL). In timing specifications, a signal is deemed valid at the instant it enters a valid state. Invalid signal A signal is invalid if it is not in a valid logic state, i.e., when it is in the threshold region between VIL and VIH. In timing specifications, a signal is deemed Invalid at the instant it enters the threshold region. TIMING CONVENTIONS For the purpose of this timing specifications the following conventions apply : Input Signals All input signals may be characterized as : VL = 0.4 V, VH = 2.4 V, tR < 10 ns, tF < 10 ns. Period The period of the clock signal is designated as tPxx where xx represents the mnemonic of the clock signal being specified. Rise Time Rise times are designated as tRyy, where yy represents a mnemonic of the signal whose rise time is being specified, tRyy is measured from VIL to VIH . Fall Time Fall times are designated as tFyy, where yy represents a mnemonic of the signal whose fall time is being specified, tFyy is measured from VIH to VIL. Pulse Width High The high pulse width is designated as tWzzH, where zz represents the mnemonic of the input or output signal whose pulse width is being specified. High pulse width are measured from VIH to VIH. Pulse Width Low The low pulse is designated as tWzzL’ where zz represents the mnemonic of the input or output signal whose pulse width is being specified. Low pulse width are measured from VIL to VIL. Setup Time Setup times are designated as tSwwxx where ww represents the mnemonic of the input signal whose setup time is being specified relative to a clock or strobe input represented by mnemonic xx. Setup times are measured from the ww Valid to xx Invalid. Hold Time Hold times are designated as THwwxx where ww represents the mnemonic of the input signal whose hold time is being specified relative to a clock or strobe input represented by the mnemonic xx. Hold times are measured from xx Valid to ww Invalid Delay Time Delay times are designated as TDxxyy [H/L], where xx represents the mnemonic of the input reference signal and yy represents the mnemonic of the output signal whose timing is being specified relative to xx. The mnemonic may optionally be terminated by an H or L to specify the high going or low going transition of the output signal. Maximum delay times are measured from xx Valid to yy Valid. Minimum delay times are measured from xx Valid to yy Invalid. This parameter is tested under the load conditions specified in the Conditions column of the Timing Specifications section of this datasheet. 28/32 TS5070 - TS5071 COMBO II SALES TYPE LIST Ordering Number Electrical Package Marking Packing description TS5070FN Stdandard PLCC28 TS5070FN Tubes Selection Datasheet PLCC28 TS5070FN Tape December and reel 1997 PDIP20 TS5071N Tubes TS5070FNTR TS5071N Relaxed PLCC28 TS5070FN Tubes Param Page selection TSW5070FNTR (Gxa, Gra, PLCC28 TS5070FN Tape Gxa 22 Grag, Gxag) and reel TSW5070FN TSW5071N PDIP20 TS5071N Tubes Gxag 22 Conditions Min Max Unit -- -0.2 0.2 dB -6.3dBm<0dbm0<6.4dBm -0.1 0.1 dB -12.7dBm<0dBm0<-6.4dBm -0.2 0.2 dB -19dBm<0dBm0<-12.8dBm -0.5 0.5 TSP5070FN TSP5070FNTR TSP5071N 29/32 dB Gra 23 -- -0.2 0.2 dB Grag 23 -4.6dBm<0dBm0<8.1dBm -0.1 0.1 dB -11dBm<0dBm0<-4.7dBm -0.2 0.2 dB -17.3dBm<0dBm0<-11.1dBm -0.5 0.5 dB PLCC28 TS5070FN Tubes Param Page Special selection PLCC28 TS5070FN Tape Gxag 22 for and reel Grag/Gxag PDIP20 TS5071N Tubes Grag 23 Conditions Min Max Unit all programmed gains -0.1 0.1 dB all programmed gains -0.1 0.1 dB TS5070 - TS5071 PLCC28 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 12.32 12.57 0.485 0.495 B 11.43 11.58 0.450 0.456 D 4.2 4.57 0.165 0.180 D1 2.29 3.04 0.090 0.120 D2 0.51 E 9.91 0.020 10.92 0.390 0.430 e 1.27 0.050 e3 7.62 0.300 F 0.46 0.018 F1 0.71 0.028 G 0.101 0.004 M 1.24 0.049 M1 1.143 0.045 30/32 TS5070 - TS5071 DIP20 PACKAGE MECHANICAL DATA mm DIM. MIN. a1 0.254 B 1.39 TYP. MAX. MIN. TYP. MAX. 0.010 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D 25.4 1.000 E 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 I 3.93 0.155 L Z 31/32 inch 3.3 0.130 1.34 0.053 TS5070 - TS5071 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGSTHOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1997 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 32/32