TSA1201 12-BIT, 50MSPS, 150mW A/D CONVERTER ■ 0.5Msps to 50Msps sampling frequency ■ 40mW @5Msps, 150mW @ 50Msps ■ 2.5V supply voltage with 2.5V/3.3V compati■ ■ ■ ■ ■ bility for digital I/O Input range: 2Vpp differential SFDR up to 77dB @ 50Msps, Fin=15MHz ENOB up to10.5 bits @ 50Msps, Fin=15MHz Built-in reference voltage with external bias capability Pinout compatibility with TSA0801, TSA1001 and TSA1002 ORDER CODE Temperature Range Part Number Package Conditioning Marking TSA1201IF -40°C to +85°C TQFP48 Tray SA1201I TSA1201IFT -40°C to +85°C TQFP48 Tape & Reel SA1201I EVAL1201/AA Evaluation board PIN CONNECTIONS (top view) DESCRIPTION AVCC DFSB OEB SRC NC VCCBI GNDBE VCCBE DR 48 47 46 45 44 43 42 41 40 39 38 37 NC AVCC index corner AGND IPOL 1 36 NC VREFP 2 35 D0 (LSB) VREFM 3 34 D1 AGND 4 33 D2 VIN 5 32 D3 AGND 6 31 D4 VINB 7 AGND 8 29 D6 INCM 9 28 D7 TSA1201 30 D5 AGND 10 27 D8 AVCC 11 26 D9 25 D10 AVCC 12 18 19 20 21 22 23 24 GNDBI GNDBE VCCBE OR D11 (MSB) DGND 17 NC DGND DVCC 16 DGND 14 15 CLK 13 DVCC The TSA1201 is a 12-bit, 50MHz maximum sampling frequency Analog to Digital converter using a CMOS technology combining high performances and very low power consumption. The TSA1201 is based on a pipeline structure and digital error correction to provide excellent static linearity and achieve 10.5 effective bits at Fs=50Msps, and Fin=15MHz, with a global power consumption of 150mW. The TSA1201 features adaptative behaviour to the application. Its architecture allows to sample from 0.5Msps up to 50Msps, with a programmable power consumption which makes the application board even more optimized. It integrates a proprietary track-and-hold structure to ensure an high analog bandwidth of 1GHz and enable IF-sampling. Several features are available on the device. A voltage reference is integrated in the circuit. Differential or single-ended analog inputs can be applied. The output data can be coded into two differential formats. A Data Ready signal is raised as the data is valid on the output and can be used for synchronization purposes. The TSA1201 is available in extended (-40°C to +85°C) temperature range, in small 48 pins TQFP package. PACKAGE 7 x 7 mm TQFP48 APPLICATIONS ■ ■ ■ ■ ■ High speed data acquisition Medical imaging and ultrasound Portable instrumentation High speed DSP interface Digital communication - IF sampling March 2001 1/20 TSA1201 ABSOLUTE MAXIMUM RATINGS Symbol AVCC DVCC Parameter Analog Supply voltage 1) 1) Values Unit 0 to 3.3 V 0 to 3.3 V VCCBI Digital buffer Supply voltage 1) 0 to 3.3 V VCCBE Digital buffer Supply voltage 1) Storage temperature Electrical Static Discharge 0 to 3.6 V +150 °C 2 KV Tstg ESD Digital Supply voltage - HBM - CDM-JEDEC Standard 1.5 1. All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must never exceed -0.3V or VCC+0V OPERATING CONDITIONS Symbol Parameter Test conditions Min Typ Max Unit AVCC Analog Supply voltage 2.25 2.5 2.7 V DVCC Digital Supply voltage 2.25 2.5 2.7 V VCCBI Internal (quiet) buffer Supply voltage 2.25 2.5 2.7 V VCCBE External (noisy) buffer Supply voltage 2.25 2.5 3.5 V VREFP Forced top voltage reference 0.8 - AVCC V VREFM Bottom internal reference voltage input 1 V 0 BLOCK DIAGRAM VREFP +2.5V +2.5V/3.3V GNDA VIN stage 1 INCM stage 2 stage n Reference circuit VINB IPOL VREFM DFSB SRC Sequencer-phase shifting OEB CLK Timing Digital data correction DR DO Buffers TO D11 OR GND 2/20 TSA1201 PIN CONNECTIONS (top view) AVCC AVCC DFSB OEB SRC NC VCCBI GNDBE VCCBE DR 48 47 46 45 44 43 42 41 40 39 38 37 NC AGND index corner IPOL 1 36 NC VREFP 2 35 D0 (LSB) VREFM 3 34 D1 AGND 4 33 D2 VIN 5 32 D3 AGND 6 31 D4 VINB 7 AGND 8 29 D6 INCM 9 28 D7 AGND 10 27 D8 AVCC 11 26 D9 AVCC 12 25 D10 TSA1201 18 19 20 21 22 23 24 GNDBI GNDBE VCCBE OR D11 (MSB) DGND 17 NC DGND DVCC DVCC 16 DGND 14 15 CLK 13 30 D5 PIN DESCRIPTION Pin No Name Description Observation Analog bias current input Pin No Name Description Observation 1 IPOL 25 D10 Digital output CMOS output (2.5V/3.3V) 2 VREFP Top voltage reference 1V 26 D9 Digital output CMOS output (2.5V/3.3V) 3 VREFM Bottom voltage reference 0V 27 D8 Digital output CMOS output (2.5V/3.3V) 4 AGND Analog ground 0V 28 D7 Digital output CMOS output (2.5V/3.3V) 5 VIN Analog input 1Vpp 29 D6 Digital output CMOS output (2.5V/3.3V) 6 AGND Analog ground 0V 30 D5 Digital output CMOS output (2.5V/3.3V) 7 VINB Inverted analog input 1Vpp 31 D4 Digital output CMOS output (2.5V/3.3V) 8 AGND Analog ground 0V 32 D3 Digital output CMOS output (2.5V/3.3V) 9 INCM Input common mode 0.5V 33 D2 Digital output CMOS output (2.5V/3.3V) 10 AGND Analog ground 0V 34 D1 Digital output CMOS output (2.5V/3.3V) 11 AVCC Analog power supply 2.5V 35 D0(LSB) Least Significant Bit output CMOS output (2.5V/3.3V) 12 AVCC Analog power supply 2.5V 36 NC Non connected 13 DVCC Digital power supply 2.5V 37 NC Non connected 14 DVCC Digital power supply 2.5V 38 DR Data Ready output CMOS output (2.5V/3.3V) 15 DGND Digital ground 0V 39 VCCBE Digital Buffer power supply 2.5V/3.3V 16 CLK Clock input 2.5V compatible CMOS input 40 GNDBE Digital Buffer ground 0V 17 DGND Digital ground 0V 41 VCCBI Digital Buffer power supply 2.5V 18 NC Non connected 42 NC 19 DGND Digital ground 0V 43 SRC Slew rate control input 2.5V/3.3V CMOS input 20 GNDBI Digital buffer ground 0V 44 OEB Output Enable input 2.5V/3.3V CMOS input 21 GNDBE Digital buffer ground 0V 45 DFSB Data Format Select input 2.5V/3.3V CMOS input 22 VCCBE Digital buffer power supply 2.5V/3.3V 46 AVCC Analog power supply 2.5V 23 OR Out Of Range output CMOS output (2.5V/3.3V) 47 AVCC Analog power supply 2.5V CMOS output (2.5V/3.3V) 48 AGND Analog ground 0V 24 D11(MSB) Most Significant Bit output Non connected 3/20 TSA1201 ELECTRICAL CHARACTERISTICS AVCC = DVCC = VCCBE = VCCBI = 2.5V,Fs= 50Msps,Fin=2MHz, Vin@ -1dBFS, VREFM=0V Tamb = 25°C (unless otherwise specified) TIMING CHARACTERISTICS Symbol Parameter Test conditions Min Typ Max Unit 50 MHz 55 % FS Sampling Frequency 0.5 DC Clock Duty Cycle 45 50 TC1 Clock pulse width (high) 9 10 ns TC2 Clock pulse width (low) 9 10 ns Tod Data Output Delay (Fall of Clock 6pF load capacitance to Data Valid) 8 ns Tpd Data Pipeline delay 5.5 cycles Ton Falling edge of OEB to digital output valid data 1 ns Toff Rising edge of OEB to digital output tri-state 1 ns TIMING DIAGRAM N+2 N+3 N+1 N+4 N N-3 N-2 N+5 N-1 N+6 CLK Tpd + Tod OEB DATA OUT Ton Toff Tod N-9 N-8 N-7 N-6 N-5 N-4 N-1 N-3 DR HZ state 4/20 N TSA1201 CONDITIONS AVCC = DVCC = VCCBE = VCCBI = 2.5V,Fs= 50Msps,Fin=2MHz, Vin@ -1dBFS, VREFM=0V Tamb = 25°C (unless otherwise specified) ANALOG INPUTS Symbol Parameter Test conditions Min VIN-VINB Full scale reference voltage Cin Input capacitance Rin Differential input resistance BW Analog Input Bandwitdh ERB Effective Resolution Bandwidth1) Vin@Full Scale, Fs=50Msps Typ Max Unit 2.0 Vpp 7.0 pF 5 MΩ 1000 MHz 90 MHz 1. See parameters definition for more information. REFERENCE VOLTAGE Symbol VREFP Parameter Top internal reference voltage Test conditions Tmin= -40°C to Tmax= 85°C1) Min Typ Max Unit 0.79 1.0 1.16 V 1.16 V 1.22 V 1.23 V 0.65 V 0.65 V 0.79 1.08 Vpol Analog bias voltage Tmin= -40°C to Tmax= 85°C1) 1.07 0.40 VINCM Input common mode voltage Tmin= -40°C to Tmax= 85°C1) 1.15 0.4 0.55 1. Not fully tested over the temperature range. Guaranted by sampling. 5/20 TSA1201 CONDITIONS AVCC = DVCC = VCCBE = VCCBI = 2.5V,Fs= 50Msps,Fin=2MHz, Vin@ -1dBFS, VREFP=1V, VREFM=0V Tamb = 25°C (unless otherwise specified) POWER CONSUMPTION Symbol Pd Parameter Power consumption in normal operation mode Test conditions Min 1) Tmin= -40°C to Tmax= ICCBI Digital Buffer Supply Current 158 mW 165 mW 51 mA 55 mA 2.2 mA 2.2 mA 0.4 mA 0.4 mA 10.8 mA 10.8 mA 5 mA 1.9 Tmin= -40°C to Tmax= 85°C2) 0.3 1) Tmin= -40°C to Tmax= 85°C2) 9.8 1) ICCBE 150 85°C2) 1) Digital Supply Current Unit 46 Analog Supply current ICCD Max Tmin= -40°C to Tmax= 85°C2) 1) ICCA Typ Digital Buffer Supply Current 2) Tmin= -40°C to Tmax= 85°C ICCBEZ Digital Buffer Supply Current in High Impedance Mode 4 Rthja Junction-ambient thermal resistance (TQFP48) 80 °C/W 1. Equivalent load: Rload= 470Ω and Cload= 6pF 2. Not fully tested over the temperature range. Guaranted by sampling. DIGITAL INPUTS AND OUTPUTS Symbol Parameter Test conditions Min Typ Max Unit 0 0.8 V Clock input VIL Logic "0" voltage VIH Logic "1" voltage 2.0 2.5 V Digital inputs VIL Logic "0" voltage VIH Logic "1" voltage 0 0.25 x VCCBE 0.75 x VCCBE VCCBE V V Digital Outputs VOL VOH Logic "0" voltage Logic "1" voltage Iol=10µA Ioh=10µA IOZ High Impedance leakage current OEB set to VIH CL Output Load Capacitance 6/20 0 0.1 x VCCBE 0.9 x VCCBE VCCBE -2.5 V V 2.5 µA 15 pF TSA1201 CONDITIONS AVCC = DVCC = VCCBE = VCCBI = 2.5V,Fs= 50Msps, Vin@ -1dBFS, VREFP=1V, VREFM=0V Tamb = 25°C (unless otherwise specified) ACCURACY Symbol Parameter Test conditions Min Typ Max Unit OE Offset Error Fin= 2MHz, VIN@+1dBFS 2.45 mV DNL Differential Non Linearity Fin= 2MHz, VIN@+1dBFS ±0.6 LSB INL Integral Non Linearity Fin= 2MHz, VIN@+1dBFS ±1.7 LSB - Monotonicity and no missing codes Guaranted DYNAMIC CHARACTERISTICS Symbol Parameter Test conditions Min Fin= 15MHz1) SFDR Typ Max Unit -77.2 -68 dBc -67 dBc Spurious Free Dynamic Range Fin= 15MHz2) SNR Signal to Noise Ratio Fin= 15MHz1) 61.6 Fin= 15MHz2) 60.7 Fin= 15MHz1) THD 64.9 dB -74.3 ENOB -68 dB -64 dB Total Harmonics Distorsion Fin= 15MHz2) SINAD dB Signal to Noise and DistorsionRatio Fin= 15MHz1) 61 Fin= 15MHz2) 60 Fin= 15MHz1) 10 Fin= 15MHz2) 9.9 64.4 dB dB 10.5 bits Effective Number of Bits bits 1. Equivalent load: Rload= 470Ω and Cload= 6pF 2. Tmin= -40°C to Tmax= 85°C. Not fully tested over the temperature range. Guaranted by sampling. 7/20 TSA1201 DEFINITIONS OF SPECIFIED PARAMETERS STATIC PARAMETERS Static measurements are performed through method of histograms on a 2MHz input signal, sampled at 50Msps, which is high enough to fully characterize the test frequency response. The input level is +1dBFS to saturate the signal. Differential Non Linearity (DNL) The average deviation of any output code width from the ideal code width of 1LSB. Integral Non linearity (INL) An ideal converter presents a transfer function as being the straight line from the starting code to the ending code. The INL is the deviation for each transition from this ideal curve. DYNAMIC PARAMETERS Dynamic measurements are performed by spectral analysis, applied to an input sinewave of various frequencies and sampled at 50Msps. Spurious Free Dynamic Range (SFDR) The ratio between the power of the worst spurious signal (not always an harmonic) and the amplitude of fundamental tone (signal power) over the full Nyquist band. It is expressed in dBc. Total Harmonic Distortion (THD) The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. It is expressed in dB. 8/20 Signal to Noise Ratio (SNR) The ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the Nyquist band (f s/2) excluding DC, fundamental and the first five harmonics. SNR is reported in dB. Signal to Noise and Distorsion Ratio (SINAD) Similar ratio as for SNR but including the harmonic distortion components in the noise figure (not DC signal). It is expressed in dB. From the SINAD, the Effective Number of Bits (ENOB) can easily be deduced using the formula: SINAD= 6.02 × ENOB + 1.76 dB. When the applied signal is not Full Scale (FS), but has an A0 amplitude, the SINAD expression becomes: SINAD= 6.02 × ENOB + 1.76 dB + 20 log (2A0/FS) The ENOB is expressed in bits. Analog Input Bandwidth The maximum analog input frequency at which the spectral response of a full power signal is reduced by 3dB. Higher values can be achieved with smaller input levels. Effective Resolution Bandwidth (ERB) The band of input signal frequencies that the ADC is intended to convert without loosing linearity i.e. the maximum analog input frequency at which the SINAD is decreased by 3dB or the ENOB by 1/2 bit. Pipeline delay Delay between the initial sample of the analog input and the availability of the corresponding digital data output,on the output bus. Also called data latency. It is expressed as a number of clock cycles. TSA1201 Static parameter: Integral Non Linearity Fs=50MSPS; Fin=1MHz; Icca=45mA; N=131072pts 3 2 INL (LSBs) 1 0 -1 -2 -3 0 500 1000 1500 2000 2500 3000 3500 4000 2500 3000 3500 4000 O u tp u t C o d e Static parameter: Differential Non Linearity Fs=50MSPS; Fin=1MHz; Icca=45mA; N=131072pts 2 1 .5 DNL (LSBs) 1 0 .5 0 - 0 .5 -1 - 1 .5 -2 0 500 1000 1500 2000 O u tp u t C o d e 12 66.5 11.8 66 11.6 65.5 11.4 SNR 65 11.2 64.5 11 SINAD 64 10.8 63.5 10.6 63 10.4 ENOB 62.5 10.2 62 2.25 10 2.35 2.45 2.55 VCCA (V) 2.65 ENOB (bits) Dynamic parameters (dB) 67 Distortion vs. VCCA Fs=50MSPS; Icca=45mA; Fin=10MHz Dynamic Parameters (dB) Linearity vs. VCCA Fs=50MSPS; Icca=45mA; Fin=10MHz -72 -73 -74 -75 -76 THD -77 -78 -79 SFDR -80 -81 -82 2.25 2.35 2.45 2.55 2.65 VCCA (V) 9/20 TSA1201 Linearity vs. VCCD Fs=50MSPS; Icca=45mA; Fin=10MHz 11.8 65 11.6 SNR 64.5 11.4 64 11.2 SINAD 63.5 11 63 10.8 62.5 10.6 62 10.4 ENOB 61.5 10.2 61 2.25 Dynamic parameters (dB) 12 65.5 ENOB (bits) Dynamic parameters (dB) 66 Distortion vs. VCCD Fs=50MSPS; Icca=45mA; Fin=10MHz 10 2.35 2.45 2.55 -71 -73 -75 SFDR -77 -79 THD -81 -83 -85 2.65 2.25 2.35 2.45 VCCD (V) Linearity vs. VCCBE Fs=50MSPS; Icca=45mA; Fin=10MHz 11.8 SNR 11.6 11.4 SINAD 11.2 63 11 10.8 62 10.6 10.4 ENOB 61 10.2 60 Dynamic Parameters (dB) 12 64 10 2.25 2.35 2.45 2.55 -72 -73 -74 -75 THD -76 -77 -78 SFDR -79 -80 -81 -82 2.25 2.65 2.35 2.45 VCCBE (V) 11.5 SINAD 62 11 60 58 10.5 ENOB 54 10 52 50 9.5 15 25 35 45 Fs (MHz) 55 65 75 Dynamic parameters (dB) 66 10/20 -50 ENOB (bits) Dynamic parameters (dB) 12 SNR 56 2.65 Distortion vs. Fs Icca=45mA; Fin=10MHz 70 64 2.55 VCCBE (V) Linearity vs. Fs Icca=45mA; Fin=10MHz 68 2.65 Distortion vs. VCCBE Fs=50MSPS; Icca=45mA; Fin=10MHz ENOB (bits) Dynamic parameters (dB) 66 65 2.55 VCCD (V) -55 -60 -65 THD -70 -75 -80 SFDR -85 -90 15 25 35 45 Fs (MHz) 55 65 75 TSA1201 Linearity vs. Fin Fs=50MHz; Icca=45mA Distortion vs. Fin Fs=50MHz; Icca=45mA 11.5 75 11 ENOB 10.5 70 10 SNR 65 9.5 9 60 8.5 SINAD 8 55 7.5 50 Dynamic parameters (dB) Dynamic parameters (dB) -60 12 80 20 40 60 -70 THD -75 SFDR -80 -85 -90 7 0 -65 0 80 20 40 Fin (MHz) 12 69 11.5 67 SNR 11 63 SINAD 10.5 61 ENOB 59 10 57 9.5 55 -40 10 60 80 Distortion vs. Temperature Fs=49.7MSPS; Icca=45mA; Fin=15MHz 90 Dynamic Parameters (dB) Dynamic Parameters (dB) Linearity vs.Temperature Fs=49.7MSPS; Icca=45mA; Fin=15MHz 65 60 Fin (MHz) 85 THD 80 75 SFDR 70 65 60 55 50 -40 110 10 Temperature (°C) 60 110 Temperature (°C) Single-tone 16K FFT at 50Msps Fin=94.5MHz; Icca=45mA, [email protected] Power Spectrum (dB) 0 -20 -40 -60 -80 -100 -120 -140 0 5 10 15 20 Frequency (MHz) 11/20 TSA1201 APPLICATION NOTE DETAILED INFORMATION The TSA1201 is a High Speed analog to digital converter based on a pipeline architecture and the latest deep submicron CMOS process to achieve the best performances in terms of linearity and power consumption. The pipeline structure consists of 11 internal conversion stages in which the analog signal is fed and sequencially converted into digital data. Each 10 first stages consists of an Analog to Digital converter, a Digital to Analog converter, a Sample and Hold and a gain of 2 amplifier. A 1.5-bit conversion resolution is achieved in each stage. The latest stage simply is a comparator. Each resulting LSB-MSB couple is then time shifted to recover from the delay caused by conversion. Digital data correction completes the processing by recovering from the redundancy of the (LSB-MSB) couple for each stage. The corrected data are outputed through the digital buffers. Signal input is sampled on the rising edge of the clock while digital outputs are delivered on the falling edge of the clock. The advantages of such a converter reside in the combination of pipeline architecture and the most advanced technologies. The highest dynamic performances are achieved while consumption remains at the lowest level. Some functionalites have been added in order to simplify as much as possible the application board. These operational modes are described in the following table. The TSA1201 is pin to pin compatible with the 8bits/40Msps TSA0801, the 10bits/25Msps TSA1001 and the 10bits/50Msps TSA1002. This ensures a conformity with the product family and above all, an easy upgrade of the application OPERATIONAL MODES DESCRIPTION Inputs Analog input differential level (VIN-VINB) > RANGE -RANGE > (VIN-VINB) RANGE> (VIN-VINB) >-RANGE (VIN-VINB) > RANGE -RANGE > (VIN-VINB) RANGE> (VIN-VINB) >-RANGE X X X Outputs DFSB OEB H H H L L L X X X L L L L L L H X X SRC OR DR Most Significant Bit (MSB) X X X X X X X H L H H L H H L HZ X X CLK CLK CLK CLK CLK CLK HZ CLK CLK D11 D11 D11 D11 Complemented D11 Complemented D11 Complemented HZ 25Msps compliant slew rate 50Msps compliant slew rate Data Format Select (DFSB) Output Enable (OEB) When set to low level (VIL), the digital input DFSB provides a two’s complement digital output MSB. This can be of interest when performing some further signal processing. When set to high level (VIH), DFSB provides a standard binary output coding. When set to low level (VIL), all digital outputs remain active and are in low impedance state. When set to high level (VIH), all digital outputs buffers are in high impedance state while the converter goes on sampling. When OEB is set to a low level again, the data are then present on the output with a very short Ton delay. Therefore, this allows the chip select of the device. The timing diagram summarizes this functionality. 12/20 TSA1201 Slew Rate Control (SRC) When set to high level (VIH), all digital outputs currents are limited to a clamp value so that digital noise power is reduced to its minimum. Rise and fall times just match 25MHz sampling rate assuming the load capacitance on each digital output remains below 10pF. When set to low level (VIL), the maximum digital output current increases so that rise and fall times just match the 50MHz sampling rate assuming the load capacitance on each digital output remains below 10pF. also use a higher impedance ratio (1:2 or 1:4) to reduce the driving requirement on the analog signal source. Each analog input can drive a 1Vpp amplitude input signal, so the resultant differential amplitude is 2Vpp. Figure 1 : Differential input configuration Analog source ADT1-1 1:1 VIN 50Ω TSA1201 100pF VINB Out of Range (OR) This function is implemented on the output stage in order to set up an "Out of Range" flag whenever the digital data is over the full scale range. Typically, there is a detection of all the data being at ’0’ or all the data being at ’1’. This ends up with an output signal OR which is in low level state (VOL) when the data stay within in the range, or in high level state (VOH) when the data are out of the range. Data Ready (DR) The Data Ready output is an image of the clock being synchronized on the output data (D0 to D11). This is a very helpful signal that simplifes the synchronization of the measurement equipment or the controling DSP. As digital output, DR goes into high impedance state when OEB is asserted to high level as described in the timing diagram. DRIVING THE ANALOG INPUT 330pF 10nF INCM 470nF Single-ended input configuration Some applications may require a single-ended input. This is easily achieved with the configuration reported on Figure 2 for an AC-coupled input or on Figure 3 and 4 for a DC-coupled input.. In the case of AC-coupled analog input, it is recommended to connect the other analog input to the common mode voltage of the circuit (INCM) so as to properly bias the ADC. The INCM may remain at the same internal level (0.56V) thus driving only a 1Vpp input amplitude, or it must be increased to 1V to drive a 2Vpp input amplitude. Figure 2 : AC-coupled Single-ended input Differential inputs The TSA1201 has been designed to obtain optimum performances when being differentially driven. An RF transformer is a good way to achieve such performances. Figure 1 describes the schematics. The input signal is fed to the primary of the transformer, while the secondary drives both ADC inputs. The common mode voltage of the ADC (INCM) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set to 0.56V. It determines the DC component of the analog signal. As being an high impedance input, it acts as an I/O and can be externally driven to adjust this DC component. The INCM is decoupled to maintain a low noise level on this node. Our evaluation board is mounted with a 1:1 ADT1-1 transformer from Minicircuits. You might Signal source 100nF VIN TSA1201 50Ω VINB 330pF 10nF INCM 470nF 1V In the case of DC-coupled analog input, Figure 3 shows the configuration for a 2Vpp input signal. The DC component is driven by VREFP which is connected to INCM and VINB and therefore imposes its voltage. VREFM being connected to ground, a dynamic of 2Vpp is achievable. Figure 4 describes the configuration for a 1Vpp analog signal. In this case, VREFM is connected 13/20 TSA1201 to VINB and INCM. The latest imposes its voltage. VREFP being internally set to 1V, the dynamic is then 1Vpp. Figure 3 : DC-coupled 2Vpp analog input Analog Analog+DC DC VIN VREFP TSA1201 VINB VREFM INCM 330pF 10nF 470nF REFERENCE CONNECTION Internal reference In the standard configuration, the ADC is biased with the internal reference voltage. VREFM pin is connected to Analog Ground while VREFP is internally set to a voltage of 1.0V. It is recommended to decouple the VREFP in order to minimize low and high frequency noise. Refer to Figure 5 for the schematics. Figure 5 : Internal reference setting 1.0V Figure 4 : DC-coupled 1Vpp analog input 330pF 10nF 470nF VREFP VIN TSA1201 VINB VREFM Analog Analog+DC DC VIN TSA1201 VINB VREFM INCM 330pF 10nF 470nF IF-sampling Software radio has become a common mode for receiving data through RF receivers. Its main advantage being to digitally implement what was originally done with analog functions such as discriminators, demodulation and filtering. Originally, bipolar process was mainly used because they provided high transistor transit frequency, while pure CMOS technology showed a lower one. With new CMOS process and circuit topology, higher frequencies are now achieved. The TSA1201 has been specifically designed to meet the requirement of sampling at Intermediate Frequency. For this purpose, the Track-and-Hold of the first pipeline stage has been built to ensure the global linearity of the overall ADC to perform the right characteristics. Our proprietary Track-and-Hold has a patented switch control system to enable the performances not to be degraded as input signal frequency increases. As a result, an analog bandwidth of 1GHz is achieved. 14/20 External reference It is possible to use an external reference voltage instead of the internal one for specific applications requiring even better linearity or enhanced temperature behaviour. In this case, the amplitude of the external voltage must be at least equal to the internal one (1.0V). Using the STMicroelectronics Vref TS821 leads to optimum performances when configured as shown on Figure 6. Figure 6 : External reference setting 1kΩ 330pF VCCA VREFP VIN TSA1201 VINB VREFM 10nF 470nF TS821 external reference This can be very helpful for example for multichannel application to keep a good matching over the sampling frequency range. TSA1201 Clock input Figure 7 : Optimized power consumption Fin=1MHz 200 70 180 The duty cycle must be between 45% and 55%. It is recommended to always keep the circuit clocked, even at the lowest specified sampling frequency of 0.5Msps, before applying the supply voltages. Rpol(kOhms) The clock power supplies must be separated from the ADC output ones to avoid digital noise modulation at the output. 60 160 50 140 120 30 80 60 20 40 0 0 25 The internal architecture of the TSA1201 enables to optimize the power consumption according to the sampling frequency of. For this purpose, a resistor is placed between IPOL and the analog Ground pins. Therefore, the total dissipation is adjustable from 0.5Msps up to 50Msps. This feature is of highest importance when power saving conditions the application. The TSA1201 will combine highest performances and lowest consumption at 50Msps when Rpol is equal to 12kΩ. At lower sampling frequency range, this value of resistor may be adjusted in order to decrease the analog current without any degradation of dynamic performances. As an example, 40mW total power consumption is achieved at 5 Msps with Rpol equal to 190kΩ and 35mW is dissipated at 1Msps with Rpol equal to 350kΩ. The table below sums up the relevant data. Figure 7 describes the behaviour of the converter as sampling frequency increases and shows the optimum in terms of analog current and polarization resistor. Total power consumption optimization depending on Rpol value Optimized power (mW) 45 65 85 Fs(MHz) Power consumption optimization Rpol (kΩ) 10 RPOL 20 5 Fs (Msps) 40 ICCA 100 Icca(mA) The quality of your converter is very dependant on your clock input accuracy, in terms of aperture jitter; the use of low jitter crystal controlled oscillator is recommended. 5 190 35 29 50 12 40 100 150 Layout precautions To use the ADC circuits in the best manner at high frequencies, some precautions have to be taken for power supplies: - First of all, the implementation of 4 separate proper supplies and ground planes (analog, digital, internal and external buffer ones) on the PCB is mandatory for high speed circuit applications to provide low inductance and low resistance common return. The separation of the analog signal from the digital part is essential to prevent noise from coupling onto the input signal. - Power supply bypass capacitors must be placed as close as possible to the IC pins in order to improve high frequency bypassing and reduce harmonic distortion. - Proper termination of all inputs and outputs must be incorporated with output termination resistors; then the amplifier load will be only resistive and the stability of the amplifier will be improved. All leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance. - To keep the capacitive loading as low as possible at digital outputs, short lead lengths of routing are essential to minimize currents when the output changes. To minimize this output capacitance, buffers or latches close to the output pins will relax this constraint. - Choose component sizes as small as possible (SMD). 15/20 TSA1201 EVAL1201 evaluation board The characterization of the board has been made with a fully ADC devoted test bench as shown on Figure 8. The analog signal must be filtered to be very pure. The dataready signal is the acquisition clock of the logic analyzer. The ADC digital outputs are latched by the octal buffers 74LCX573. All characterization measurements have been made with: - SFSR=+0.5dB for static parameters. - SFSR=-0.5dB for dynamic parameters. Figure 8 : Analog to Digital Converter characterization bench Power HP8644B Sine wave Generator Vin ADC evaluation board data Logic Analyzer dataready ck TLA704 16/20 HP8133A Pulse Generator HP8644B Sine Wave Generator 1 2 1 2 R1 50 3 1 GndB1 1 2 22 GndB2 1 2 21 DGND 1 2 20 AGND 1 2 19 AVCC 2 1 Mes com Mode 12 1 2 Regl com mode 8 7 VrefM 5 VrefP 1 2 2 6 + C42 47µF C41 10µF 470nF 10nF 330pF C5 C6 C7 C8 330pF C9 C1 100pF 470nF 10nF C10 4 T2-AT1-1WT T2 AVCC 470nF C32 10nF C31 C4 10µ 1 2 3 4 5 6 7 8 9 10 11 12 J16 CON2 C36 47µ 470nF C23 10nF C22 330pF C21 C20 330pF C2 330pF C11 J15 DVCC 470nF 10nF C3 C13 C12 C30 330pF 470nF 10nF R2 1K Raj1 47K Ipol VrefP VrefM AGND Vin AGND VINB AGND INCM AGND AVCC AVCC 330pF 10nF C14 470nF C15 C16 AVCC 47K R13 47K R12 47K R11 47K R10 1 2 8-14bits ADC TSA1002 TSA1201 50 R3 CLJ/SMB J4 6 1 2 + 2 J11 J13 330pF 10nF C25 470nF C27 C29 C35 47µ 10µ 470nF C24 10nF C19 10µF C17 T1 T2-AT1-1WT 330pF C18 J18 VccB1 36 35 34 33 32 31 30 29 28 27 26 25 VCCB1 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 R14 R15 R16 R17 R18 R19 47K 47K 47K 47K 47K 47K C28 VCCB1 1 2 J10 OEB + 2 1 1 2 4 3 + 2 1 1 2 48 47 46 45 44 43 42 41 40 39 38 37 AGND AVCC AVCC DFSB OEB NC NC 2.5VCCBUFF GNDBUFF 2.5VCCBUFF DR D0 DVCC DVCC DGND CLK DGND NC DGND GNDBUFF GNDBUFF 2.5VCCBUFF OR D13 13 14 15 16 17 18 19 20 21 22 23 24 330pF 10nF C33 470nF C40 C38 74LCX573 OEB VCC D0 Q0 D1 Q1 U3 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 GND LE 74LCX573 OEB VCC D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 U2 D5 Q5 D6 Q6 D7 Q7 GND LE 330pF 10nF C26 470nF C39 47µ C37 C34 + 2 1 20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11 J17 VDDBUFF3V VCCB2 1 2 J9 DFSB OR D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO DR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 32PIN J6 TSA1201 Figure 9 : TSA1201 Evaluation board schematic 17/20 TSA1201 Figure 10 : Printed circuit of evaluation board. Printed circuit board - List of components P a rt D e s ig n F o o t p rin t P a rt D e s ig n F o o t prin t P a rt D e s ig n F o o t p rint P a rt D e s ig n T yp e a to r Typ e a to r Typ e ato r T yp e ato r 10 uF C24 12 10 33 0 pF C33 603 4 70 nF C7 805 A VC C J 12 10 uF C23 12 10 33 0 pF C20 603 4 70 nF C 16 805 C LJ / S M B J4 SMB /H 10 uF C41 12 10 33 0 pF C8 603 4 70 nF C 19 805 A GN D J 19 F IC H E2 M M 10 uF C29 12 10 33 0 pF C2 603 4 70 nF C3 805 D FS B J9 F IC H E2 M M 10 0 p F C1 603 33 0 pF C5 603 4 7KΩ R 12 603 D GN D J2 0 F IC H E2 M M 10 nF C 12 603 33 0 pF C 11 603 4 7KΩ R 14 603 D VC C J 15 F IC H E2 M M 10 nF C39 603 33 0 pF C30 603 4 7KΩ R 11 603 G n dB 1 J2 2 F IC H E2 M M 10 nF C 15 603 33 0 pF C 17 603 4 7KΩ R a j1 VR 5 G n dB 2 J2 1 F IC H E2 M M 10 nF C40 603 33 0 pF C 14 603 4 7KΩ R 10 603 M e s c o m m o de J 8 F IC H E2 M M 10 nF C27 603 47 uF C36 CAP 4 7KΩ R 19 603 O EB F IC H E2 M M 10 nF C4 603 47 uF C34 CAP 4 7KΩ R 13 603 R e gl c o m m o de J7 F IC H E2 M M 10 nF C21 603 47 uF C35 CAP 4 7KΩ R 15 603 T 2 - A T 1- 1WT ADT 10 nF C31 603 47 uF C42 CAP 4 7KΩ R 16 603 T 2 - A T 1- 1WT T1 ADT 10 nF C6 603 47 0 nF C22 805 4 7KΩ R 17 603 Vc c B 1 J 18 F IC H E2 M M 10 nF C9 603 47 0 nF C32 805 4 7KΩ R 18 603 VD D B UF F 3 V J 17 F IC H E2 M M 10 nF C 18 603 47 0 nF C37 805 50 Ω R3 603 Vin J1 SMB /H 1KΩ R2 603 47 0 nF C38 805 50 Ω R1 603 Vre f M J5 F IC H E2 M M 3 2 P IN J6 ID C 3 2 47 0 nF C 13 805 7 4 LC X5 7 3 U3 T S S OP 2 0 Vre f P J2 F IC H E2 M M 3 3 0 pF C25 603 47 0 nF C28 805 7 4 LC X5 7 3 U2 T S S OP 2 0 T S A 10 0 2 TSA1201 U1 TQ F P 4 8 3 3 0 pF C26 603 47 0 nF C 10 805 CON2 S IP 2 18/20 J 16 J 10 T2 F o o t p rin t F IC H E2 M M TSA1201 PACKAGE MECHANICAL DATA 48 PINS - PLASTIC PACKAGE A A2 e 48 A1 37 36 12 25 E3 E1 E B 1 0,10 mm .004 inch SEATING PLANE c 24 L1 D3 D1 D L 13 K 0,25 mm .010 inch GAGE PLANE Millimeters Inches Dim. Min. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.05 1.35 0.17 0.09 0.45 Typ. 1.40 0.22 9.00 7.00 5.50 0.50 9.00 7.00 5.50 0.60 1.00 Max. Min. 1.60 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.004 0.75 0.018 Typ. 0.055 0.009 0.354 0.276 0.216 0.0197 0.354 0.276 0.216 0.024 0.039 Max. 0.063 0.006 0.057 0.011 0.008 0.030 0° (min.), 7° (max.) Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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