TSH110-111-112-113-114 WIDE BAND, LOW NOISE OPERATIONAL AMPLIFIERS ■ ■ ■ ■ ■ ■ ■ ■ ■ LOW NOISE: 3nV/√Hz LOW SUPPLY CURRENT: 3.2mA 47mA OUTPUT CURRENT BANDWIDTH: 100MHz TSH110 : SOT23-5 Output 1 5V to 12V SUPPLY VOLTAGE SLEW-RATE: 450V/µs SPECIFIED FOR 100Ω Load VERY LOW DISTORTION TINY: SOT23-5, TSSOP and SO PACKAGES DESCRIPTION The singles TSH110 and TSH111, the dual TSH112, the triple TSH113 and the quad TSH114 are current feedback operational amplifiers featuring a very high slew rate of 450V/µs and a large bandwidth of 100MHz, with only a 3.2mA quiescent supply current. The TSH111 and TSH113 feature a Standby function for each operator. This function is a power down mode with a high output impedance. These devices operate from ±2.5V to ±6V dual supply voltage or from 5V to 12V single supply voltage. They are able to drive a 100Ω load with a swing of 9V minimum (for a 12V power supply). The harmonic and intermodulation distortions of these devices are very low, making this circuit a good choice for applications requiring wide bandwidth with multiple carriers. For board space and weight saving, the TSH110 comes in miniature SOT23-5 package, the TSH111 comes in SO8 and TSSOP8 packages, the TSH112 comes in SO8 and TSSOP8 packages, the TSH113 and TSH114 comes in SO14 and TSSOP14 packages. APPLICATIONS ■ ■ ■ ■ PIN CONNECTIONS (top view) Receiver for xDSL +- Non Inverting Input 3 4 Inverting Input TSH111 : SO8/TSSOP8 NC 1 8 STANDBY Inverting Input 2 _ 7 VCC + Non Inverting Input 3 + 6 Output 5 NC VCC - 4 TSH112 : SO8/TSSOP8 Output1 1 8 VCC + Inverting Input1 2 _ Non Inverting Input1 3 + VCC - 4 7 Output2 _ 6 Inverting Input2 + 5 Non Inverting Input2 TSH113 : SO14/TSSOP14 STANDBY1 1 14 Output3 STANDBY2 2 _ 13 Inverting Input3 STANDBY3 3 + 12 Non Inverting Input3 VCC + 4 Non Inverting Input1 5 Inverting Input1 6 11 VCC + _ + _ 10 Non Inverting Input2 9 Inverting Input2 8 Output2 Output1 7 TSH114 : SO14/TSSOP14 Output1 1 14 Output4 Inverting Input1 2 _ _ 13 Inverting Input4 Non Inverting Input1 3 + + 12 Non Inverting Input4 VCC + 4 Non Inverting Input2 5 High End Video Drivers 5 VCC + VCC - 2 Inverting Input2 6 Output2 7 11 VCC + _ + _ 10 Non Inverting Input3 9 Inverting Input3 8 Output3 A/D Converter Driver High End Audio Applications February 2002 1/19 TSH110-TSH111-TSH112-TSH113-TSH114 ABSOLUTE MAXIMUM RATINGS Symbol Parameter 1) VCC Supply Voltage Vid Differential Input Voltage 2) Vi Input Voltage 3) Operating Free Air Temperature Range Storage Temperature Toper Tstg Tj Rthjc Rthja ESD Maximum Junction Temperature Thermal resistance junction to case SOT23-5 SO8 SO14 TSSOP8 TSSOP14 Thermal resistance junction to ambiante area SOT23-5 SO8 SO14 TSSOP8 TSSOP14 Human Body Model Machine Model Charged Device Model Value Unit 14 V ±1 V ±6 V -40 to +85 -65 to +150 °C °C 150 °C 80 28 22 37 32 250 157 125 130 110 2.0 0.2 1.5 °C/W °C/W kV ouput short circuit duration 4) 1. 2. 3. 4. All voltages values, except differential voltage are with respect to network ground terminal Differential voltages are non-inverting input terminal with respect to the inverting terminal The magnitude of input and output must never exceed V CC +0.3V Short-circuits can cause excessive heating. Destructive dissipation can result. OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage Vicm Common Mode Input Voltage Range Value Unit 5 to 12 V VCC-+1.5 to VCC+-1.5 V ORDER CODES Type TSH110ILT (code K302) TSH111ID TSH111IDT TSH111IPT TSH112ID TSH112IDT TSH112IPT TSH113ID TSH113IDT TSH113IPT TSH114ID TSH114IDT TSH114IPT Temperature Package -40° to +85°C SOT23-5 SO8 SO8 TSSOP8 SO8 SO8 TSSOP8 SO14 SO14 TSSOP14 SO14 SO14 TSSOP14 D = Small Outline Package (SO) - also available in Tape & Reel (DT) P = Thin Shrink Small Outline Package (TSSOP) - only available in Tape & Reel (PT) L = Tiny Package (SOT23-5) - only available in Tape & Reel (LT) 2/19 TSH110-TSH111-TSH112-TSH113-TSH114 ELECTRICAL CHARACTERISTICS (pages 3 and 4) Dual Supply Voltage, VCC= ±2.5Volts, R*fb = 680Ω, Tamb = 25°C (unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit -1.5 0.3 2.0 mV DC PERFORMANCE Vio ∆Vio Input Offset Voltage Tmin. < Tamb < Tmax. 1 mV Input Offset Voltage Drift vs. Temperature Tmin. < Tamb < Tmax. 5 µV/°C Iib+ Non Inverting Input Bias Current Iib- Inverting Input Bias Current ROL ICC Tamb Transimpedance Supply Current per Operator Tamb -10 Tmin. < Tamb < Tmax. Tamb 13 µA µA 2.5 7 µA -3 1.9 2.5 µA 500 750 kΩ Tmin. < Tamb < Tmax. RL=100Ω 1.4 Tamb 3.2 Tmin. < Tamb < Tmax. 3.5 mA 4 mA CMR Common Mode Rejection Ratio (∆Vic/∆Vio) 56 60 dB SVR Supply Voltage Rejection Ratio (∆VCC/∆Vio) 70 80 dB PSR Power Supply Rejection Ratio (∆VCC/∆Vout) 48 dB 2 V Tmin. < Tamb < Tmax. RL = 100Ω GND 1.9 V Tamb RL = 100Ω -1.8 Tmin. < Tamb < Tmax. RL = 100Ω -1.7 V Gain=1, Rload=3.9kΩ DYNAMIC PERFORMANCE and OUTPUT CHARACTERISTICS Voh Vol High Level Output Voltage Low Level Output Voltage Tamb RL = 100Ω 1.4 -1.3 V | Isink | Output Sink current Tmin. < Tamb < Tmax. 20 mA Isource Output Source current Tmin. < Tamb < Tmax. 18 mA 81 MHz 230 V/µs 9 ns 9 ns Vout=1Vpk, Rfb*=820Ω//2pF BW -3dB Bandwidth Load=100Ω SR Slew Rate AVCL =+2, 2V step Load=100Ω Tr Rise Time AVCL =+2 Tf Fall Time Ov Overshoot St Settling Time @ 0.05% ∆G Differential gain ∆φ Differential phase for 200mV step AVCL =+2, Rfb*=820Ω//2pF Load=100Ω AVCL =+2, RL=100Ω F=4.5MHz, Vout=1Vpeak 160 16 % 60 0.05 ns % 0.05 ° 3/19 TSH110-TSH111-TSH112-TSH113-TSH114 Symbol Parameter NOISE AND HARMONIC PERFORMANCE en Equivalent Input Voltage Noise in THD Equivalent Input Current Noise Total Harmonic Distortion Test Condition Min. Typ. Max. Unit 3 nV/√Hz 8.5 pA/√Hz 64.4 dB @900kHz @1.2MHz 90 90 dBc @3.1MHz 86 @3.2MHz 83 Frequency : 1MHz AVCL =+2, F=2MHz RL=100Ω Vout=2Vpeak AVCL =+2, Vout=2Vpp RL=100Ω F1=1MHz, F2=1.1MHz IM3 Third order inter modulation product MATCHING CHARACTERISTICS Gf Gain Flatness Vo1/Vo2 Channel Separation F=(DC) to 6MHz AVCL =+2, Vout=2Vpp F=1MHz to 10MHz 0.1 dB 65 dB (*) Rfb is the feedback resistance between the output and the inverting input of the amplifier. 4/19 TSH110-TSH111-TSH112-TSH113-TSH114 ELECTRICAL CHARACTERISTICS (pages 5 and 6) Dual Supply Voltage, VCC=±6Volts, R*fb = 680Ω, Tamb = 25°C (unless otherwise specified) Symbol Parameter TestCondition Min. Typ. Max. Unit -1.0 0.9 3.0 mV DC PERFORMANCE Vio ∆Vio Input Offset Voltage Input Offset Voltage Drift vs Temperature Iib+ Non Inverting Input Bias Current Iib - Inverting Input Bias Current ROL Transimpedance ICC Supply Current per Operator Tamb Tmin. < Tamb < Tmax. 1.3 mV Tmin. < Tamb < Tmax. 5 µV/°C Tamb -12 Tmin. < Tamb < Tmax. Tamb 14 µA µA 3 3.4 µA 600 900 kΩ Tamb 4 Tmin. < Tamb < Tmax. 10 µA -4 Tmin. < Tamb < Tmax. RL=100Ω 1 1.7 5 mA 4.1 mA CMR Common Mode Rejection Ratio (∆Vic/∆Vio) 58 63 dB SVR Supply Voltage Rejection Ratio (∆Vcc/∆Vio) 72 80 dB PSR Power Supply Rejection Ratio (∆Vcc/∆Vout) 49 dB 4.7 V Tmin. < Tamb < Tmax. RL = 100Ω 4.6 V Tamb RL = 100Ω -4.7 Tmin. < Tamb < Tmax. RL = 100Ω -4.6 V Gain=1, Rload=3.9kΩ DYNAMIC PERFORMANCE and OUTPUT CHARACTERISTICS Voh Vol High Level Output Voltage Low Level Output Voltage Tamb RL = 100Ω 4.5 -4.3 V | Isink | Output Sink current Tmin. < Tamb < Tmax. 47 mA Isource Output Source current Tmin. < Tamb < Tmax. 46 mA 100 MHz 450 V/µs 10.4 ns 12.2 ns Vout=1Vpk, Rfb*=680Ω//2pF Bw -3dB Bandwidth Load=100Ω SR Slew Rate AVCL =+2, 6V step Load=100Ω Tr Rise Time AVCL =+2 Tf Fall Time Ov Overshoot St Settling Time @ 0.05% ∆G Differential gain ∆φ Differential phase for 200mV step AVCL =+2, Rfb*=680Ω//2pF Load=100Ω AVCL =+2, RL=100Ω F=4.5MHz, Vout=2Vpeak 240 17 % 40 0.05 ns % 0.05 ° 5/19 TSH110-TSH111-TSH112-TSH113-TSH114 Symbol Parameter NOISE AND HARMONIC PERFORMANCE en Equivalent Input Voltage Noise in THD Equivalent Input Current Noise Total Harmonic Distortion TestCondition Min. Typ. Max. Unit 3 nV/√Hz 8.6 pA/√Hz 67.7 dB @900kHz @1.2MHz 82 84 dBc @3.1MHz 77 @3.2MHz 73 Frequency : 1MHz AVCL =+2, F=2MHz RL=100Ω Vout=4Vpp AVCL =+2, Vout=4Vpp RL=100Ω F1=1MHz, F2=1.1MHz IM3 Third order inter modulation product MATCHING CHARACTERISTICS Gf Gain Flatness Vo1/Vo2 Channel Separation F=(DC) to 6MHz AVCL =+2, Vout=4Vpp F=1MHz to 10MHz 0.1 dB 65 dB (*) Rfb is the feedback resistance between the output and the inverting input of the amplifier. 6/19 TSH110-TSH111-TSH112-TSH113-TSH114 STANDBY MODE Tamb = 25°C (unless otherwise specified), VCC=±6Volts Symbol Parameter Test Condition Min. Typ. Max. Unit Vlow Standby Low Level VCC- (VCC+0.8) V Vhigh Standby High Level (VCC- +2) (VCC+) V 40 µA ICC SBY Isol Current Consumption per Operator in Standby mode 26 Input/Output Isolation F=1MHz -90 dB Zout Output Impedance (Rout // Cout) Rout Cout 31 25 MΩ pF Ton Time from Standby Mode to Active Mode 2 µs Toff Time from Active Mode to Standby Mode 13 µs Down to ICC SBY = 40µA TSH111 STANDBY CONTROL pin 8 (SBY) OPERATOR STATUS Vlow Standby Vhigh Active TSH113 STANDBY CONTROL OPERATOR STATUS pin 1 (SBY OP1) pin 2 (SBY OP2) pin 3 (SBY OP) OP1 OP1 OP3 Vlow x x Standby x x Vhigh x x Active x x x Vlow x x Standby x x Vhigh x Active x x x Vlow x x Standby x x Vhigh x x Active 7/19 TSH110-TSH111-TSH112-TSH113-TSH114 (fig.1) Closed Loop Gain vs. Frequency (fig.2) Closed Loop Gain vs. Frequency AV=+1, Rfb=2.2kΩ, Cfb=2pF, RL=100Ω, Vin=100mVp AV=-1, Rfb=2.2kΩ, Cfb=2pF, RL=100Ω, Vin=100mVp 2 2 40 -140 Vcc=±2.5V Vcc=±6V gain -160 20 0 0 0 -40 Vcc=±2.5V Vcc=±6V Vcc=±2.5V -4 -220 Vcc=±6V -240 -60 -6 -6 -260 -80 -8 -8 -280 -100 -10 -10 -120 10 -300 1 100 10 100 Frequency (MHz) Frequency (MHz) (fig.3) Closed Loop Gain vs. Frequency (fig.4) Closed Loop Gain vs. Frequency AV=+2, Rfb=680Ω, Cfb=2pF, RL=100Ω, Vin=100mVp AV=-2, Rfb=680kΩ, Cfb=2pF, RL=100Ω, Vin=100mVp -140 40 Vcc=±2.5V gain(dB)- AV 4 -20 2 -40 Vcc=±2.5V 0 -60 Vcc=±6V -2 phase 2 -200 Vcc=±2.5V -220 Vcc=±6V 0 -240 -260 -280 -100 -4 -4 -300 -120 10 -180 Vcc=±6V -2 -80 1 -160 4 0 phase gain 20 1 100 10 100 Frequency (MHz) Frequency (MHz) (fig.5) Closed Loop Gain vs. Frequency (fig.6) Closed Loop Gain vs. Frequency AV=+10, Rfb=510Ω, RL=100Ω, Vin=30mVp AV=-10, Rfb=510Ω, RL=100Ω, Vin=30mVp 22 40 22 0 -40 Vcc=±2.5V Vcc=±6V Vcc=±2.5V 18 -20 -60 gain(dB)- AV gain(dB)- AV Vcc=±2.5V Phase (°) Vcc=±6V phase -160 gain 20 18 16 -140 20 gain 20 phase Vcc=±6V -180 -200 Vcc=±2.5V 16 -220 Vcc=±6V -240 14 14 -260 -80 12 12 -280 -100 -120 10 1 10 Frequency (MHz) Phase (°) Vcc=±6V gain(dB)- AV gain Vcc=±2.5V 6 Phase (°) 6 100 -300 10 1 10 Frequency (MHz) 100 Phase (°) 1 8/19 Phase (°) -4 -200 gain(dB) -20 phase Phase (°) gain(dB)- AV -2 Vcc=±2.5V -2 -180 Vcc=±6V TSH110-TSH111-TSH112-TSH113-TSH114 AV=+2, Rfb=680Ω, Cfb=2pF, RL=100Ω, Vcc=±6V 1V /div. (fig.8): Negative Slew Rate AV=+2, Rfb=680Ω, Cfb=2pF, RL=100Ω, Vcc=±6V 1V /div. (fig.7): Positive Slew Rate 0V 0V 5ns /div. 5ns /div. AV=+2, Rfb=680Ω, Cfb=2pF, RL=100Ω, Vcc=±2.5V 0.4V /div. (fig.10): Negative Slew Rate AV=+2, Rfb=680Ω, Cfb=2pF, RL=100Ω, Vcc=±2.5V 0.4V /div. (fig.9): Positive Slew Rate 0V 0V 5ns /div. 5ns /div. (fig.12): Vio vs. Power Supply Open loop, no load 10 1000 9 900 8 800 7 700 6 Vio (µV) Voltage Noise (nV/√Hz) (fig.11): Input Voltage Noise Level AV=+100, Rfb=1kΩ, Input+ connected to Gnd via 10Ω 5 4 600 500 3 400 2 300 1 0 100 200 1k 10k Frequency (Hz) 100k 1M 5 6 7 8 9 10 11 12 Vcc (V) 9/19 TSH110-TSH111-TSH112-TSH113-TSH114 (fig.14): Icc(+) vs. Power Supply Open loop, no load Open loop, no load -3.3 3.9 -3.4 3.8 -3.5 3.7 Icc(+) (mA) Icc(-) (mA) (fig.13): Icc(-) vs. Power Supply -3.6 3.6 -3.7 3.5 -3.8 3.4 -3.9 5 6 7 8 9 10 11 3.3 12 5 6 7 8 V cc (V) 9 10 11 12 10 11 12 V cc (V) (fig.15): Iib(-) vs. Power Supply (fig.16): Iib(+) vs. Power Supply Open loop, no load Open loop, no load 1.0 3.2 3.0 0.8 Iib(+) (mA) Iib(-) (mA) 2.8 2.6 2.4 0.6 0.4 2.2 0.2 2.0 0.0 1.8 5 6 7 8 9 10 11 5 12 6 7 8 9 V cc (V) V cc (V) (fig.18): Voh vs. Power Supply Open loop, RL=100Ω -2.0 5.0 -2.5 4.5 -3.0 4.0 Voh (V) Vol (V) (fig.17): Vol vs. Power Supply Open loop, RL=100Ω -3.5 3.5 -4.0 3.0 -4.5 2.5 -5.0 2.0 5 6 7 8 9 Vcc (V) 10/19 10 11 12 5 6 7 8 9 V cc (V) 10 11 12 TSH110-TSH111-TSH112-TSH113-TSH114 (fig.19): Icc vs. Temperature (fig.20): Icc (Standby) vs. Temperaure Open loop, no load Open loop, no load 5 30 Icc(+) for Vcc=±6V 4 20 3 IccStand-By (µA) Icc(+) for Vcc=±2.5V 2 Icc (mA) 1 0 -1 -2 Icc(-) for Vcc=±2.5V 10 0 -10 -3 -20 -4 Icc(-) for Vcc=±6V -5 -40 -20 0 20 40 60 80 -30 100 -40 -20 0 20 40 60 80 100 Temperature (°C) Temperature (°C) (fig.21): ROL vs. Temperature (fig.22): CMR vs. Temperature Open loop, no load Open loop, no load 68 1000 Vcc=±6V 66 950 CMR (dB) ROL (kΩ) Vcc=±6V 900 64 62 Vcc=±2.5V 850 60 Vcc=±2.5V 800 -40 -20 0 20 40 60 80 58 100 -40 -20 0 20 Temperature (°C) (fig.23): VOH & VOL vs. Temperature 80 100 AV=+2, RL=100Ω 600 VOH for Vcc=±6V pos. SR for Vcc=±6V 5 550 4 500 Slew Rate (V/µs) V OH for Vcc=±2.5V 3 VOH and VOL (V) 60 (fig.24): Slew Rate vs. Temperature Open loop, RL=100Ω 6 40 Temperature (°C) 2 1 0 -1 V OL for Vcc=±2.5V -2 450 400 350 neg. SR for Vcc=±6V 300 250 pos. SR for Vcc=±2.5V 200 neg. SR for Vcc=±2.5V -3 V OL for Vcc=±6V -4 150 -5 -6 100 -40 -20 0 20 40 Temperature (°C) 60 80 100 -40 -20 0 20 40 60 80 100 Temperature (°C) 11/19 TSH110-TSH111-TSH112-TSH113-TSH114 (fig.25): Group Delay (fig.26): Gain Flatness AV=+2, Rfb=680Ω, Cfb=2pF, RL=100Ω AV=+2, Rfb=680Ω, Cfb=2pF, RL=100Ω 6.30 8 Vcc=±2.5V 6.25 Gain Flatness (dB) Delay Time (ns) 7 Vcc=±2.5V 6 5 4 6.20 6.15 6.10 6.05 6.00 3 Vcc=±6V 5.95 Vcc=±6V 5.90 2 0.1 1 10 1k 100 10k 100k 1M 10M 100M Frequency (Hz) Frequency (MHz) (fig.27): Frequency Response vs. Load (fig.28): Frequency Response vs. Load AV=+2, Rfb=680Ω, Cfb=2pF, VCC=±2.5V, (fig.29) AV=+2, Rfb=680Ω, Cfb=2pF, VCC=±6V, (fig.29) 7 7 C=30pF Rs=30 6 6 5 5 4 Gain(dB) - AV Gain(dB) - AV C=30pF Rs=39 C=100pF Rs=12 3 C=1nF Rs=6 3 2 C=1nF Rs=5 2 C=100pF Rs=12 4 1 1 0 0 1 10 1 100 (fig.29): Capacitive Load Schematic. measurements on (fig.27) and (fig.28) + OUT TSH11x Rs(Ω) _ 1kΩ RG 680Ω Rfb, 680Ω Cfb 2pF 12/19 10 Frequency (MHz) Frequency (MHz) C 100 TSH110-TSH111-TSH112-TSH113-TSH114 Vout=C0+C1(V in)+C2(Vin)2+C 3(Vin)3+...+C n(Vin)n due to a non-linearity in the input-output amplitude transfert. In the case of Vin=Asinωt, CO is the DC component, C1(Vin) is the fundamental, C nAn is the amplitude of the harmonics. A one-frequency or one-tone input signal contributes to a harmonic distortion. A two-tones input signal contributes to a harmonic distortion and intermodulation product. This intermodulation product or intermodulation distortion of a two-tones input signal is the first step of the amplifier study for driving capability in the case of a multitone signal. In this case Vin=Asinω1t+Bsinω2t, and : Vout= CO+C1(Asinω1t+Bsinω2t) + C2(Asinω1t+Bsinω2t)2+C3(Asinω1t+Bsinω2t)3 + ...Cn(Vin)n The following graphs show the IM3 of the amplifier in two cases as a function of the output amplitude. The two-tones input signal is achieved by the multisource generator Marconi 2026. Each tone has the same amplitude. The measurement is achieved by the spectrum analyser HP 3585A. Both instruments are phase locked to enhance measurement precision. (fig.30): 3rd Order Intermodulation (180kHz & 280kHz) AV=+4, Rfb=680Ω, no Cfb, RL=100Ω, Vcc=±6V -60 -65 -70 IM3 (dBc) Intermodulation Distortion A non-ideal output of the amplifier can be described by the following development : -75 -80 740kHz -85 380kHz -90 80kHz -95 640kHz -100 0 1 2 3 4 5 Output Amplitude (V peak ) (fig.31): 3rd Order Intermodulation (1MHz & 1.1MHz) AV=+2, Rfb=680Ω, Cfb=2pF, RL=100Ω, Vcc=±2.5V -60 -65 -70 IM3 (dBc) Vout= CO+C1(Asinω1t+Bsinω2t) + C2(A2+B2)/2-(C2/2)(A2cos2ω1t+B2cos2ω2t) + 2C2AB(cos(ω1-ω2)t-cos(ω1+ω2)t) + (3C3/4) (A3sinω1t+B 3sinω2t+2A2Bsinω2t+2B2Asinω1t) + (C3A3sin3ω1t+B3sin3ω2t) + (3C3A2B/2)(sin(2ω1-ω2)t-1/2sin(2ω1+ω2)t) + (3C3B2A/2)(sin(−ω1+2ω2)t- 1/2sin(ω1+2ω2)t) + ...Cn(Vin)n -75 3.2MHz -80 3.1MHz -85 1.2MHz -90 900kHz -95 In this expression, we can recognize the second order intermodulation IM2 by the frequencies (ω1-ω2) and (ω1+ω 2) and the third order intermodulation IM3 by the frequencies (2ω1-ω2), (2ω1+ω2), (−ω1+2ω2) and (ω1+2ω2). -100 0.0 0.5 1.0 1.5 2.0 Output Amplitude (V peak) 13/19 TSH110-TSH111-TSH112-TSH113-TSH114 Power Supply Bypassing A proper power supply bypassing comes very important for optimizing the performance in high frequency range. Bypass capacitors must be placed as close as possible to the IC pins to improve high frequency bypassing. A capacitor greater than 1µF is necessary to minimize the distortion. For a better quality bypassing a capacitor of 0.1µF will be added following the same condition of implementation. These bypass capacitors must be incorporated for the negative and the positive supplies. (fig.32): Circuit for power supply bypassing. +VCC 1µF 0.1µF + TSH11x _ Nevertheless, the PCB layout has also an effect on the crosstalk level. Capacitive coupling between signal wires, distance between critical signal nodes, power supply bypassing, are the most significant points. (fig.33): Crosstalk vs. Frequency. AV=+2, Rfb=680Ω, Cfb=2pF, RL=100Ω, Vcc=±6V, ±2.5V 0 -20 X-Talk (dB) Printed Circuit Board Layout Considerations In this range of frequency, printed circuit board parasitics can affect the closed-loop performance. The implementation of a proper ground plane in both sides of the PCB is mandatory to provide low inductance and low resistance common return. Most important for controlling the gain flatness and the bandwidth are stray capacitances at the output and inverting input. For minimizing the coupling, the space between signal lines and ground plane will be increased. Connections of the feedback components must be as short as possible on order to decrease the associated inductance which affect high frequency gain errors. It is very important to choose external components as small as possible such as surface mounted devices, SMD, in order to minimize the size of all the dc and ac connections. -40 -60 -80 -100 10k 100k 1M 10M 100M Frequency (Hz) Single Power Supply The TSH11x operates from 12V down to 5V power supplies. This is achieved with a dual power supply of ±6V and ±2.5V or a single power supply of 12V and 5V referenced to the ground. In the case of this asymmetrical supplying, a biasing is necessary to assume a positive output dynamic range between 0V and +Vcc supply rails. Considering the values of VOH and VOL, the amplifier will provide an ouput dynamic from +1.35V to 10.75V for a 12V supplying, from 0.6V to 4.5V for a 5V supplying. The following figure show the case of a 5V single power supply configuration. (fig.34): Circuit for +5V single supply. 0.1µF +5V 1µF 10µF + IN -VCC Channel Separation or Crosstalk The following figure show the crosstalk from an amplifier to a second amplifier. This phenomenon, accented in high frequencies, is unavoidable and intrinsic of the circuit. 14/19 +5V Rin 1kΩ 100µF 50Ω _ 50Ω R1 5kΩ R1 5kΩ + 1µF OUT TSH11x RG 680Ω 10nF + CG Rfb, 680Ω Cfb 2pF TSH110-TSH111-TSH112-TSH113-TSH114 Assuming a low level active onto the disable pins (1,2,3) as described on page 7 of the datasheet, any operator can be disable/enable independently. The two disabled operators will be in standby mode featuring a high ouput impedance with a high input/output isolation and a low quiescent current. (fig.36): Typical output response in standby mode on/off 0.4V /div. The amplifier must be biased with a mid supply (nominaly +Vcc/2), in order to maintain the DC component of the signal at this value. Several options are possible to provide this bias supply (such as a virtual ground using an operational amplifier), or a two-resistance divider which is the cheapest solution. A high resistance value is required to limit the current consumption. On the other hand, the current must be high enough to bias the non-inverting input of the amplifier. If we consider this bias current (5µA) as the 1% of the current through the resistance divider (500µA) to keep a stable mid supply, two 5kΩ resistances can be used. The input provides a high pass filter with a break frequency below 10Hz which is necessary to remove the original 0 volt DC component of the input signal, and to hold it at 2.5V. Enabled Output Disabled Output Video Multiplexing using the TSH113 +2.4V (fig.35): Circuit for switching 3 video signals with the tri- Standby Signal ple TSH113. -2.4V 100ns /div. IN1 + (fig.37): Typical output response in standby mode off/on TSH113 0.4V /div. _ ENABLE1 Rfb, 680Ω RG 680Ω Enabled Output Cfb, 2pF IN2 + 75Ω TSH113 75Ω cable Disabled Output Common OUT _ 75Ω +2.4V Standby Signal ENABLE2 -2.4V Rfb, 680Ω RG 680Ω 10µs /div. Cfb, 2pF IN3 + TSH113 _ ENABLE3 RG 680Ω Rfb, 680Ω Cfb, 2pF 15/19 TSH110-TSH111-TSH112-TSH113-TSH114 (fig.38): Input / Output Isolation vs. Frequency.. (tab.1): Closed-loop Gain and Feedback Components. VCC 0 (V) (pF) -3dB Bw (MHz) 0.1dB Bw (MHz) 510 - 46 14 -10 510 - 42 13 +2 680 2 105 50 -2 680 2 90 40 +1 2.2k 2 170 30 -1 2.2k 2 110 20 +10 510 - 37 13 -10 510 - 36 12 +2 680 2 93 25 -2 680 2 86 30 +1 2.2k 2 130 50 -1 2.2k 2 100 18 Rfb Cfb (Ω) +10 Gain Input/output Isolation (dB) -20 -40 -60 ±6 -80 Standby mode -100 -120 0.01 0.1 1 10 100 Frequency (MHz) ±2.5 Choice of the Feedback Circuit The TSH11x is a serie of current feedback amplifiers. For a current feedback structure the bandwidth depends on the value of the feedback components and the value of supply voltage. A good choice of these components is necessary to achieve the gain flatness and the stability. The following table shows the typical -3dB bandwidth and 0.1dB bandwidth assuming different gains and power supply on 100Ω load. Please see also the Closed Loop Gain vs. Frequency curves on page 8 of the datasheet. (fig.39): Non-inverting and Inverting Implementation.. Input Non-Inverting Gain = 1+ Rfb / RG + Output _ 49.9Ω Inverting Amplifier Biasing In this case a resistance (R on fig.40) is necessary to achieve a good input biasing. This resistance is calculated by assuming the negative and positive input bias current. The aim is to make the compensation of the offset bias current which could affect the input offset voltage and the output DC component. Assuming Ib-, Ib+, Rin, Rfb and a zero volt output, the resistance R comes : R = Rin // Rfb . (fig.40): Compensation of the Input Bias Current.. 50Ω Rfb Rfb RG Cfb Ib- Rin _ Vcc+ Output Rfb Input Rin _ Cfb Inverting Gain = - Rfb / Rin + Vcc- Ib+ Output + R 16/19 49.9Ω 50Ω R Load TSH110-TSH111-TSH112-TSH113-TSH114 PACKAGE MECHANICAL DATA 8 PINS - THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) PACKAGE MECHANICAL DATA 8 PINS - PLASTIC MICROPACKAGE (SO) k 0,25 mm .010 inch GAGE PLANE C SEATING PLANE E1 L1 L c A E A2 e aaa 1 8 C b D 5 4 A1 PIN 1 IDENTIFICATION Millimeters Inches Millimeters Dim. Min. A a1 a2 a3 b b1 C c1 D E e e3 F L M S Inches Dim. Typ. Max. Min. 0.1 0.65 0.35 0.19 0.25 4.8 5.8 1.27 3.81 3.8 0.4 Typ. 1.75 0.25 0.004 1.65 0.85 0.026 0.48 0.014 0.25 0.007 0.5 0.010 45° (typ.) 5.0 0.189 6.2 0.228 Max. 0.069 0.010 0.065 0.033 0.019 0.010 0.020 0.197 0.244 0.050 0.150 4.0 0.150 1.27 0.016 0.6 8° (max.) Min. A A1 A2 b c D E E1 e k l 0.05 0.80 0.19 0.09 2.90 4.30 0° 0.50 Typ. 1.00 3.00 6.40 4.40 0.65 0.60 Max. Min. 1.20 0.15 1.05 0.30 0.20 3.10 0.01 0.031 0.007 0.003 0.114 4.50 0.169 8° 0.75 0° 0.09 Typ. 0.039 0.118 0.252 0.173 0.025 Max. 0.05 0.006 0.041 0.15 0.012 0.122 0.177 8° 0.0236 0.030 0.157 0.050 0.024 17/19 TSH110-TSH111-TSH112-TSH113-TSH114 PACKAGE MECHANICAL DATA 14 PINS - THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) PACKAGE MECHANICAL DATA 14 PINS - PLASTIC MICROPACKAGE (SO) k c E D E A M C s b1 a1 e e3 SEATING PLANE E1 L1 c1 A a2 b L G C L 0,25 mm .010 inch GAGE PLANE A2 1 7 8 7 e 8 aaa C D F 14 b A1 14 1 PIN 1 IDENTIFICATION Millimeters Inches Millimeters Dim. Min. A a1 a2 b b1 C c1 D (1) E e e3 F (1) G L M S Typ. Max. 1.75 0.2 1.6 0.46 0.25 0.1 0.35 0.19 Min. 0.014 0.007 0.020 45° (typ.) 8.75 0.336 6.2 0.228 8.55 5.8 Max. 0.069 0.008 0.063 0.018 0.010 0.004 0.5 1.27 7.62 3.8 4.6 0.5 Typ. 0.344 0.244 0.050 0.300 4.0 0.150 5.3 0.181 1.27 0.020 0.68 8° (max.) 0.157 0.208 0.050 0.027 Note : (1) D and F do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (.066 inc) ONLY FOR DATA BOOK. 18/19 Inches Dim. Min. A A1 A2 b c D E E1 e k l 0.05 0.80 0.19 0.09 4.90 4.30 0° 0.50 Typ. 1.00 5.00 6.40 4.40 0.65 0.60 Max. Min. 1.20 0.15 1.05 0.30 0.20 5.10 0.01 0.031 0.007 0.003 0.192 4.50 0.169 8° 0.75 0° 0.09 Typ. 0.039 0.196 0.252 0.173 0.025 Max. 0.05 0.006 0.041 0.15 0.012 0.20 0.177 8° 0.0236 0.030 TSH110-TSH111-TSH112-TSH113-TSH114 PACKAGE MECHANICAL DATA 5 PINS - TINY PACKAGE (SOT23) 2 A E A2 D b A1 L C E1 Millimeters Inches Dim. A A1 A2 B C D D1 e E F L K Min. Typ. Max. Min. Typ. Max. 0.90 0 0.90 0.35 0.09 2.80 1.20 1.45 0.15 1.30 0.50 0.20 3.00 0.035 0.047 0.035 0.014 0.004 0.110 3.00 1.75 0.60 10d 0.102 0.059 0.004 0d 0.041 0.016 0.006 0.114 0.075 0.037 0.110 0.063 0.014 0.057 0.006 0.051 0.020 0.008 0.118 2.60 1.50 0.10 0d 1.05 0.40 0.15 2.90 1.90 0.95 2.80 1.60 0.5 0.0118 0.069 0.024 10d Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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