TSM112 3.3V 5V 12V HOUSEKEEPING IC ■ OVER VOLTAGE PROTECTION FOR 3.3V ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 5V AND 12V WITHOUT EXTERNAL COMPONENTS UNDER VOLTAGE PROTECTION FOR 3.3V 5V AND 12V WITHOUT EXTERNAL COMPONENTS OVER VOLTAGE PROTECTION FOR -12V OR -5V WITH EXTERNAL COMPONENTS EXTERNALLY ADJUSTABLE UNDER VOLTAGE BLANKING DURING POWER UP POWER GOOD INPUT/OUTPUT EXTERNALLY ADJUSTABLE PG DELAY FAULT OUTPUT REMOTE OUTPUT EXTERNALLY ADJUSTABLE REMOTE DELAY PRECISION VOLTAGE REFERENCE 2kV ESD PROTECTION The TSM112 integrated circuit incorporates all sensing circuitry to regulate and protect from over voltage and under voltage a multiple output power supply (3.3V, 5V and 12V). TSM112 incorporates all the necessary functions for Housekeeping features which allow safe operation in all conditions, and very high system integration. TSM112 integrates a precise voltage reference. APPLICATION ■ PC SMPS Triple Power Line Housekeeping IC (3.3V 5V 12V) ORDER CODE Temperature Range TSM112CN TSM112CD 0 to 85°C 0 to 85°C D SO14 (Plastic Micropackage) PIN CONNECTIONS (top view) DESCRIPTION Part Number N DIP14 (Plastic Package) Package Marking N VS33 1 14 VCC VS5 2 13 FAULT VS12 3 12 PG EP 4 11 TPG PI 5 10 TREM TUV 6 9 REM GND 7 8 VREF D • • TSM112C M112 N = Dual in Line Package (DIP) D = Small Outline Package (SO) - also available in Tape & Reel (DT) January 2001 1/7 TSM112 PIN DESCRIPTION Name Pin # Type Function Vcc Gnd Vs12 14 7 3 Power Supply Power Supply Analog Input Over and Under voltage Sense Input Dedicated to the 12V Line1) Vs5 2 Analog Input Over and Under voltage Sense Input Dedicated to the 5V Line1) Vs33 1 Analog Input Positive Power Supply Line Ground Line. 0V Reference For All Voltages Over and Under voltage Sense Input Dedicated to the 3.3V Line1) Tuv 6 Timing Capacitor Adjustable Under voltage Blanking Delay at Power Up (Setting Capacitor) Fault 13 Open Collector Fault Output. Fault is high when Over or Under Voltage has been Detected PI 5 Analog Input Power Good Input. Detection of the Power Conditions PG 12 Open Collector Power Good Output. PG output is High when the Power Conditions are OK Tpg 11 Timing Capacitor Adjustable Power Good Delay (Setting Capacitor) REM 9 Logic Input Input Remote Control of the Complete System by the Motherboard (µController). Remote is active high. Switch OFF/ON of the Power Supply. Reset of the Complete System after a FAULT Activation. Trem 10 Timing Capacitor Adjustable Remote Delay (Setting Capacitor). Vref 8 Voltage Reference 2.5V Reference for all Voltages EP 4 Analog Input Extra Protection Circuit. Can be used for -12V or -5V Over Voltage Protection. 1. Over and Under Voltage Inputs can go higher than Vcc within the allowed Max Rating range ABSOLUTE MAXIMUM RATINGS Symbol Vcc Iout Io VFault Top Pd Tstg ESD Tuv EP PI PG Tpg REM Trem DC Supply Voltage DC Supply Voltage 1) Output Current Power Good Output current for the Voltage reference Fault Ouput Operating Free Air Temperature Range Power Dissipation Storage Temperature Electrostatic Discharge Adjustable Under voltage Blanking At Power UP Extra Protection Power Good Input Power Good Output Adjustable Power Good Delay Remote Control Adjustable Remote Delay Value Unit 25 V 30 20 5 -55 to 125 0.7 -55 to 150 2 5 5 5 5 5 5 5 mA mA V °C W °C kV V V V V V V V Value Unit 4.5 to 24 0 to 85 V °C 1. All voltage values, except differential voltage are with respect to network ground terminal. OPERATING CONDITIONS Symbol Vcc Toper 2/7 Parameter DC Supply Conditions Operating Free Air Temperature Range TSM112 ELECTRICAL CHARACTERISTICS Tamb = 25°C and Vcc = 17V (unless otherwise Symbol Parameter specified) Test Condition Min Typ Max Unit 3 5 mA 3.8 4 4.2 V 5.8 6.1 6.4 V 13.4 14.2 15 V 2.1 3.7 9.2 2.3 4 10 1.28 100 2.5 4.3 10.8 V V V V µs 100 300 500 ms Total Current Consumption Icc Total Supply Current Over Voltage and Under Voltage Protection Vov33 Over Voltage Sense 3.3V Input can go higher than Vcc Input can go higher than Vcc Input can go higher than Vcc Vov5 Over Voltage Sense 5V Vov12 Over Voltage Sense12V Vuv33 Vuv5 Vuv12 Vep Tfault Under Voltage Sense 3.3V Under Voltage Sense 5V Under Voltage Sense 12V Extra Over voltage Protection Threshold Fault Delay Before Latching Internally Fixed Delay Under Voltage Blanking During Power Up Tuv Thuv Under Voltage Blanking During Power Up (Vcc rising) Cuv = 2.2µF Adjustable Blanking Blanking Threshold 1.28 V 1.28 70 V mV Power Good (PG) Vpgth Power Good Voltage Threshold Vpghyst Power Good Voltage Threshold Hysteresis Vpgol Low Output Open Collector Saturation Voltage Ipgoh High Output Open Collector Leakage Current Tpgr Power Good Output Rise Time Tpgf Power Good Output Fall Time Tpg Power Good Adjustable Delay PIth Power Input Detection Threshold PG Output = 5V Vfaultol Ifaultoh Fault Output Saturation Voltage Level Fault Output Leakage Current Level IFault = 1mA Vfault = 5V Vremth Vremih Iremil Trem1 Remote ON/OFF Input Voltage Threshold High Input Remote Voltage Low Input Remote Saturation Current Remote Adjustable Delay ON to OFF Trem2 Remote Adjustable Delay OFF to ON Collector Current = 15mA Load Capacitor = 100pF Load Capacitor = 100pF Load Capacitor Cpg=2.2µF 100 1 1 300 1.28 0.4 V 1 µA 500 µs µs ms V Fault 1 1 V µA Remote Control (REM) Load Capacitor Crem=0.1µF Load Capacitor Crem=0.1µF 0.7 0.8 3.3 3.4 1 V V mA ms 40 50 0.5 60 40 50 60 ms 2.46 2.5 4 2.54 10 V mV Voltage Reference Vref Regline Internal Voltage Reference Line regulation Regline Line regulation Regload Load regulation 1) Io = 0mA Io = 0mA 4.5V<Vcc<24V Io = 10mA 4.5V<Vcc<24V 0<Io<10mA 15 mV 25 mV 1. Do not short circuit the Vref Pin 3/7 TSM112 Figure 1 : Figure 1: Application Schematic ~ PRIMARY MAIN RECT. CONV. 12V 12V 5V 5V 3.3V 3.3V PWM + OPTO + Vref Vcc AUX. CONV. 5Vstby 5Vstby PWM + OPTO + Vref TSM112 Over & Undervoltage Protection FAULT Reference PG REM Logic Sequencer Figure 2 : Internal Schematic TO POWER SUPPLY 12V Vs12 5V Vs5 3.3V Vs33 TSM112 OVP LOGIC UVP SECONDARY OUTPUT HOUSEKEEPING Ep 5V MAIN 3.3V FAULT REM Tpg Vref UV BLANK Vref CONV. Gnd 4/7 PG Trem 12V FROM PI Tuv to MOTHERBOARD Vcc TSM112 Figure 3 : Figure 3 : Detailed Internal Schematic Vcc IN 12V TSM112 VS12 Vov12 OUT 12V OVP OVP FAULT Tfault Vref S Q 1k R UVP UVP Vcc Trem Crem Trem VS5 Vov5 OUT 5V OVP Vref Power Up UV blanking Tuv 3.47V Tuv Cuv Rem UVP 0.8V Vuv5 IN 3.3V Pg VS33 Tpg TO MOTHERBOARD Vuv12 IN 5V Vov33 OUT 3.3V OVP Vref Tpg Cpg UVP 1.25V PI Vuv33 EP OVP 1.25V VREF Vref Gnd 5/7 TSM112 PRINCIPLE OF OPERATION AND APPLICATION HINTS TSM112: Housekeeping IC. TSM112 is a one chip solution for all PC SMPS: it integrates on one chip the Housekeeping Circuitry (Over Voltage and Under Voltage protections, with adequate sequencing). Triple Power Line Protection. The TSM112 Housekeeping Circuit is dedicated to 3.3V, 5V and 12V power lines protection. It integrates a Precision Voltage Reference, a Triple Over Voltage Protection Circuit and a Triple Under Voltage Protection Circuit as well as all the necessary logic and transient timing management circuits for optimal and secure communication with the motherboard, during start up, switch off and stabilized conditions. Over Voltage Protection The Over Voltage Protection Circuit is made of three comparators with internal voltage thresholds (Vov33, Vov5, Vov12) which do not require any external components for proper operation. The outputs of these three comparators are ORed. Under Voltage Protection input whereas the Over Voltage circuit bears an additional Tfault delay time. This allows an efficient protection against Output Short Circuit conditions. Power Good The Over Voltage and Under Voltage Circuits are Ored to switch the Power Good output active (PG) to warn the motherboard that the voltage of at least one of the three power lines is out of range. The PG activation bears an internal Tpg delay circuitry which can be adjusted with an external capacitor (Cpg). Remote Control Thanks to this information link to the motherboard, a resetting signal to the latch is achievable with the Remote pin (REM). When the Remote pin is active, the external Fault link between Housekeeping circuit and the PWM generator is active (high = PWM OFF) and the PG pin is active (high). Note that to reset effectively the latch, a minimum width Remote pulse should be applied thanks to an internal delay circuitry (Trem) which can be adjusted with an external capacitor (Crem). The Under Voltage Protection Circuit is made of three comparators with internal voltage thresholds (Vuv33, Vuv5, Vuv12) which do not require any external components for proper operation. The outputs of these three comparators are ORed, and blanked by an internal delay circuitry (Power Up Blanking - Tuv) which can be adjusted with an external capacitor (Cuv). This allows that during power up, the under voltage protection circuit is inhibited. Latch OFF The Over Voltage and Under Voltage Circuits outputs are again ORed before activating a latch. When activated, this latch commands the full switch OFF of the three main power lines (3.3V, 5V, 12V) by an external link between the housekeeping and the primary PWM circuits via the main optocoupler or any other device . Note that the Under Voltage Circuit, after Power Up UV blanking, bears no other delay to the latch setting 6/7 TSM112 PACKAGE MECHANICAL DATA 14 PINS - PLASTIC PACKAGE Millimeters Inches Dim. Min. a1 B b b1 D E e e3 F i L Z Typ. 0.51 1.39 Max. Min. 1.65 0.020 0.055 0.5 0.25 Typ. 0.065 0.020 0.010 20 0.787 8.5 2.54 15.24 0.335 0.100 0.600 7.1 5.1 0.280 0.201 3.3 1.27 Max. 0.130 2.54 0.050 0.100 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom © http://www.st.com 7/7