STMICROELECTRONICS USBLC6-4SC6

USBLC6-4SC6
®
ASD
(Application Specific Devices)
VERY LOW CAPACITANCE
ESD PROTECTION
MAIN APPLICATIONS
■ USB2.0 ports up to 480Mb/s (high speed)
■ Backwards compatible with USB1.1 low and
full speed
■ Ethernet port: 10/100Mb/s
■ SIM card protection
■ Video line protection
■ Portable electronics
DESCRIPTION
The USBLC6-4SC6 is a monolithic Application
Specific Discrete dedicated to ESD protection of
high speed interfaces, such as USB2.0, Ethernet
links and Video lines.
Its very low line capacitance secures a high level
of signal integrity without compromising in
protecting sensitive chips against the most
stringent characterized ESD strikes.
SOT23-6L
Figure 1: Functional Diagram
FEATURES
■ 4 data lines protection
■ Protects VBUS
■ Very low capacitance: 3pF typ.
■ SOT23-6L package
■ RoHS compliant
BENEFITS
■ Very low capacitance between lines to GND for
optimized data integrity and speed
■ Low PCB space consuming, 9mm² maximum
foot print
■ Enhanced ESD protection
■ IEC61000-4-2 level 4 compliance guaranteed
at device level, hence greater immunity at
system level
■ ESD protection of VBUS. Allows ESD current
flowing to Ground when ESD event occurs on
data line
■ High reliability offered by monolithic integration
■ Low leakage current for longer operation of
battery powered devices
■ Fast response time
■ Consistent D+ / D- signal balance:
- Best capacitance matching tolerance
I/O to GND = 0.015pF
- Compliant with USB 2.0 requirements < 1pF
February 2005
I/O1
1
6
I/O4
GND
2
5
VBUS
I/O2
3
4
I/O3
Table 1: Order Code
Part Number
USBLC6-4SC6
Marking
UL46
COMPLIES WITH THE FOLLOWING STANDARDS:
■ IEC61000-4-2 level4:
15kV (air discharge)
8kV (contact discharge)
REV. 2
1/10
USBLC6-4SC6
Table 2: Absolute Ratings
Symbol
Parameter
VPP
Peak pulse voltage
Tstg
Storage temperature range
Value
At device level:
IEC61000-4-2 air discharge
IEC61000-4-2 contact discharge
MIL STD883C-Method 3015-6
Unit
15
15
25
kV
-55 to +150
°C
Tj
Maximum junction temperature
125
°C
TL
Lead solder temperature (10 seconds duration)
260
°C
Table 3: Electrical Characteristics (Tamb = 25°C)
Symbol
Parameter
Test Conditions
VRM
Reverse stand-off voltage
IRM
Leakage current
VRM = 5V
VBR
Breakdown voltage between VBUS
and GND
IR = 1mA
Forward voltage
IR = 10mA
VF
VCL
Ci/o-GND
Clamping voltage
∆Ci/o-i/o
2/10
Min.
Typ.
Max.
5
V
2
µA
6
V
V
IPP = 1A, tp = 8/20µs
Any I/O pin to GND
12
V
IPP = 5A, tp = 8/20µs
Any I/O pin to GND
17
V
Capacitance between I/O and GND VR = 1.65V
3
4
pF
0.015
Capacitance between I/O
Unit
0.86
∆Ci/o-GND
Ci/o-i/o
Value
VR = 1.65V
1.85
0.04
2.7
pF
USBLC6-4SC6
Figure 2: Capacitance versus voltage (typical
values)
Figure 3: Line capacitance versus frequency
(typical values)
C(pF)
C(pF)
5.0
5.0
F=1MHz
VOSC=30mVRMS
Tj=25°C
4.5
4.0
VOSC=30mVRMS
Tj=25°C
4.5
VCC=0V
4.0
3.5
3.5
CO=I/O-GND
VCC=1.65V
3.0
3.0
2.5
2.5
Cj=I/O-I/O
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
Data line voltage (V)
0.0
F(MHz)
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Figure 4: Relative variation of leakage current
versus junction temperature (typical values)
1
10
1000
Figure 5: Frequency response
USBLC6-4SC6
(50Ω)
0.00
IRM[Tj] / IRM[Tj=25°C]
100
100
VBUS=5V
S21(dB)
-5.00
10
-10.00
-15.00
Tj(°C)
F(Hz)
1
25
50
75
100
125
-20.00
100.0k
1.0M
10.0M
100.0M
1.0G
3/10
USBLC6-4SC6
TECHNICAL INFORMATION
1. SURGE PROTECTION
The USBLC6-4SC6 is particularly optimized to perform surge protection based on the rail to rail topology.
The clamping voltage VCL can be calculated as follow :
VCL+ = VBUS + VF for positive surges
VCL- = - VF for negative surges
with: VF = VT + Rd.Ip
(VF forward drop voltage) / (VT forward drop threshold voltage)
We assume that the value of the dynamic resistance of the clamping diode is typically:
Rd = 1.4Ω and VT = 1.2V.
For an IEC61000-4-2 surge Level 4 (Contact Discharge: Vg=8kV, Rg=330Ω), VBUS = +5V, and if in first
approximation, we assume that : Ip = Vg / Rg = 24A.
So, we find:
VCL+ = +39V
VCL- = -34V
Note: the calculations do not take into account phenomena due to parasitic inductances.
2. SURGE PROTECTION APPLICATION EXAMPLE
If we consider that the connections from the pin VBUS to VCC and from GND to PCB GND are done by
two tracks of 10mm long and 0.5mm large; we assume that the parasitic inductances Lw of these tracks
are about 6nH. So when an IEC61000-4-2 surge occurs, due to the rise time of this spike (tr=1ns), the
voltage VCL has an extra value equal to Lw.dI/dt.
The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns
The overvoltage due to the parasitic inductances is: Lw.dI/dt = 6 x 24 = 144V
By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping
voltage will be :
VCL+ = +39 + 144 = 183V
VCL- = -34 - 144 = -178V
We can reduce as much as possible these phenomena with simple layout optimization.
It’s the reason why some recommendations have to be followed (see paragraph “How to ensure a good
ESD protection”).
Figure 6: ESD behavior; parasitic phenomena due to unsuitable layout
VCL+
183V
Lw
VBUS
ESD
SURGE
+VCC
VF
Lw di
dt
Lw
di
dt
POSITIVE
SURGE
VCC+VF
t
I/O
tr=1ns
di
VCL+ = VBUS+VF+Lw dt surge >0
di
surge <0
VCL- = -VF-Lw
dt
VI/O
Lw di
dt
tr=1ns
t
-VF
-Lw
di
dt
NEGATIVE
SURGE
GND
-178V
VCL-
4/10
USBLC6-4SC6
3. HOW TO ENSURE A GOOD ESD PROTECTION
While the USBLC6-4SC6 provides a high immunity to ESD surge, an efficient protection depends on the
layout of the board. In the same way, with the rail to rail topology, the track from the VBUS pin to the power
supply +VCC and from the VBUS pin to GND must be as short as possible to avoid overvoltages due to
parasitic phenomena (see figure 6).
It’s often harder to connect the power supply near to the USBLC6-4SC6 unlike the ground thanks to the
ground plane that allows a short connection.
To ensure the same efficiency for positive surges when the connections can’t be short enough, we
recommend to put close to the USBLC6-4SC6, between VBUS and ground, a capacitance of 100nF to
prevent from these kinds of overvoltage disturbances (see figure 7).
The add of this capacitance will allow a better protection by providing during surge a constant voltage.
The figures 8, 9 and 10 show the improvement of the ESD protection according to the recommendations
described above.
Figure 7: ESD behavior: optimized layout and
add of a capacitance of 100nF
Figure 8: ESD behavior: measurements
conditions (with coupling capacitance)
ESD
SURGE
VCL+
TEST BOARD
Lw
ESD
SURGE
REF2=+VCC
POSITIVE
SURGE
USBLC6-4SC6
C=100nF
t
I/O
t
VCL+ = VCC+VF surge >0
VI/O
VCL- = -VF
surge <0
+5V
NEGATIVE
SURGE
REF1=GND
VCL-
C=100nF
Figure 9: Remaining voltage after the
USBLC6-4SC6 during positive ESD surge
Figure 10: Remaining voltage after the
USBLC6-4SC6 during negative ESD surge
IMPORTANT:
A main precaution to take is to put the protection device closer to the disturbance source (generally the
connector).
Note: The measurements have been done with the USBLC6-4SC6 in open circuit.
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USBLC6-4SC6
4. CROSSTALK BEHAVIOR
4.1. Crosstalk phenomena
Figure 11: Crosstalk phenomena
RG1
Line 1
VG1
RL1
RG2
α 1 VG1 + β12VG2
Line 2
VG2
RL2
DRIVERS
α 2VG2 + β21VG1
RECEIVERS
The crosstalk phenomena are due to the coupling between 2 lines. The coupling factor (β12 or β21)
increases when the gap across lines decreases, particularly in silicon dice. In the example above the
expected signal on load RL2 is α2VG2, in fact the real voltage at this point has got an extra value β21VG1.
This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2.
This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency
analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage
signal or high load impedance (few kΩ).
Figure 12: Analog crosstalk measurements
TRACKING GENERATOR
TEST BOARD
SPECTRUM ANALYSER
USBLC6-4SC6
50Ω
+5V
50Ω
Vg
Vin
Vout
C=100nF
Figure 12 gives the measurement circuit for the analog application. In usual frequency range of analog
signals (up to 240MHz) the effect on disturbed line is less than -55 dB (please see figure 13).
Figure 13: Analog crosstalk results
As the USBLC6-4SC6 is designed to protect high
speed data lines, it must ensure a good transmission of operating signals. The frequency response
(figure 5) gives attenuation information and shows
that the USBLC6-4SC6 is well suitable for data
line transmission up to 480 Mbit/s while it works
as a filter for undesirable signals like GSM
(900MHz) frequencies, for instance.
USBLC6-4SC6
Aplac 7.70 User: ST Microelectronics Oct 29 2004
0.00
dB
-30.00
-60.00
-90.00
-120.00
100.0k
1.0M
10.0M
100.0M
f/Hz
6/10
1.0G
USBLC6-4SC6
5. APPLICATION EXAMPLES
Figure 14: USB2.0 port application diagram using USBLC6-4SC6
+ 3.3V
DEVICEUPSTREAM
RPU
TRANSCEIVER
SW2
+ 5V
SW1
VBUS
RX LS/FS +
RX HS +
TX HS +
RX LS/FS RX HS TX HS GND
TX LS/FS +
TX LS/FS -
Protecting
Bus Switch
USB
connector
VBUS
RX LS/FS +
RX HS +
TX HS +
RX LS/FS RX HS TX HS -
VBUS
D+
DRS
USBLC6-2SC6
GND
RS
RS
RS
RPD
+ 3.3V
DEVICEUPSTREAM
RPU
TRANSCEIVER
SW2
TX LS/FS -
TX LS/FS -
RX LS/FS +
RX HS +
TX HS +
RX LS/FS RX HS TX HS -
D+
DRS
TX LS/FS +
RPD
VBUS
USBLC6-2P6
TX LS/FS +
GND
USB
connector
SW1
VBUS
RX LS/FS +
RX HS +
TX HS +
RX LS/FS RX HS TX HS GND
HUBDOWNSTREAM
TRANSCEIVER
GND
RS
TX LS/FS +
USBLC6-4SC6
RS
RS
RPD
Mode
SW1
SW2
Low Speed LS
Open
Closed
Full Speed FS
Closed
Open
High Speed HS
Closed then open Open
GND
TX LS/FS -
RPD
Figure 15: T1/E1/Ethernet protection
Tx
+VCC
100nF
USBLC6-4SC6
SMP75-8
DATA
TRANSCEIVER
Rx
SMP75-8
7/10
USBLC6-4SC6
6. PSPICE MODEL
Figure 16 shows the PSPICE model of one USBLC6-4SC6 cell. In this model, the diodes are defined by
the PSPICE parameters given in figure 17.
Figure 16: PSPICE model
Lbo ndso t 23
MODEL = Dhigh
io1
io2
io3
io4
Lpinsot 23
Lbo ndso t 23 100 m
Lpinsot 23
Lbo ndso t 23 100 m
Lpinsot 23
Lbo ndso t 23 100 m
Lpinsot 23
Lbo ndso t 23 100 m
MODEL = Dhigh
MODEL = Dhigh
100 m
Lpinsot 23
Lvc c
Rvc c
Vcc
MODEL = Dhigh
MODEL = Dzener
MODEL = Dlow
MODEL = Dlow
MODEL = Dlow
MODEL = Dlow
Lbo ndso t 23
100 m
Lpi nsot 23
Lgn d
Rgn d
Lbo ndso t 23 100 m
Note: This simulation model is available only for an ambient temperature of 27°C.
Figure 17: PSPICE parameters
8/10
Dlow
Dhigh
Dzener
BV
50
50
7.3
CJ0
2.4p
2.4p
20p
IBV
1m
1m
1m
IKF
0.038
0.018
2.42
IS
55.2p
2.27f
3.21p
ISR
100p
100p
100p
N
1.62
1.13
1.24
M
0.3333
0.3333
0.3333
RS
0.38
0.63
0.42
VJ
0.6
0.6
0.6
TT
0.1u
0.1u
0.1u
Figure 18: USBLC6-4SC6
considerations
Lbondsot23
0.564n
Lpinsot23
0.15n
Rgnd
350m
Lgnd
100p
Rvcc
350m
Lvcc
100p
D+1
PCB
layout
1
D-1
VBUS
CBUS = 100nF
GND
D+2
D-2
USBLC6-4SC6
USBLC6-4SC6
Figure 19: SOT23-6L Package Mechanical Data
DIMENSIONS
A
REF.
E
Millimeters
Min.
e
B
D
A
0.90
A1
0
Inches
Min.
Typ.
Max.
1.45 0.035
0.057
0.10
0.004
0
0.90
1.30 0.035
0.051
b
0.35
0.50 0.014
0.02
C
0.09
0.20 0.004
0.008
D
2.80
3.05 0.110
0.120
E
1.50
A2
e
A1
θ
Max.
A2
e
c
Typ.
L
H
1.75 0.059
0.95
0.069
0.037
H
2.60
3.00 0.102
0.118
L
0.10
0.60 0.004
0.024
θ
0°
10°
0°
10°
Figure 20: Foot Print Dimensions (in millimeters)
0.60
1.20
0.95
3.50
1.10
2.30
Table 4: Ordering Information
Ordering code
Marking
Package
Weight
Base qty
Delivery mode
USBLC6-4SC6
UL46
SOT23-6L
16.7 mg
3000
Tape & reel
Table 5: Revision History
Date
Revision
Description of Changes
10-Dec-2004
1
First issue.
28-Feb-2005
2
Minor layout update. No content change.
9/10
USBLC6-4SC6
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by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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